JPS60160648A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To alleviate limitation of the wiring routes among circuit units by forming the electrodes of a transistor with a conductor arranged by patterning in a wiring region filled with an insulator, providing one or more wirings among plural transistors and providing the other electrodes for connection on the surface of the wiring region. CONSTITUTION:On a P type silicon substrate 1, transistors Q1, Q2 consisting of an N type silicon collector 3a, a P type silicon base 4a and an N type silicon emitter 5a surrounded by a P type silicon isolation 2 holding in-between a wiring region 8 filled with an insulator are formed symmetrically. Each terminal of the collector 3a, the base 4a and the emitter 5a is exposed from the side of the wiring region 8. Within the wiring region 8, each electrode of the transistors Q1, Q2 is led out, wiring is also done between the transistors Q1, Q2 and the other electrodes for connection are led out from the surface of the wiring region 8. For the electrodes and the wiring of these connections in the wiring region 8, a patterned conductor, e.g., polycrystalline silicon is used.

Description

DETAILED DESCRIPTION OF THE INVENTION fal Technical Field of the Invention The present invention relates to a semiconductor device, and in particular to a bipolar IC structure and a manufacturing method thereof.

(b) Background of the Technology Bipolar integrated circuit devices (bipolar ICs) take advantage of the fact that bipolar transistors operate at higher speeds than field effect transistors.
Transistor Logi
c) and is widely used in logic circuits.

[C) Prior art and problems Figure 1 shows an example of a basic TTL circuit, and Figure 2 shows a plan view + al and cross-sectional view of an example of a conventional RC tank structure that forms the circuit shown in Figure 1. (In bl, ■ is the base, 2 is the isolation, 3 is the collector, 4 is the base, 5 is the emitter, 6 is the insulating layer, 7 is the buried layer, 11 to 15 are electrodes/wirings, 01.02 is the transistor, R1 , R2, and R3 are resistors, IN is an input, OUT is an output, G is a ground, and Vcc is a power supply line.

The circuit shown in Fig. 1 is a basic TTL circuit when there is only one input, and the emitter of the bipolar transistor (hereinafter referred to as transistor) mouth 1 becomes the input IN, the collector of Ql is connected to the base of transistor 02, Q2
The emitter of is connected to ground G, and also the old base, 0
The base and collector of 2 are resistors R1, R2, and R, respectively.
Q2 is connected to the power supply line Vcc through Q2, and the collector of Q2 becomes the output 01JT.

An example of a conventional IC structure forming this circuit is shown in the second example.
As shown in the figure.

A transistor Q1.02 is symmetrically arranged on a p-type silicon substrate 1, surrounded by a p-type silicon isolation 2, and consisting of an n-type silicon collector 3, a p-type silicon base 4, and an n-type silicon emitter 5. is formed.

Note that 7 is a buried layer for reducing the lead-out resistance of the collector 3.

Moreover, on the insulating layer 6 on the transistors Q1 and Q2,
For example, an aluminum electrode/wiring is formed to guide and wire the collector 3, base 4, and emitter 5 through the contact hole of the insulating layer 6.
Figure Ta) Emitter 5 of transistor Q1 as shown
Connect the base 4 of 11.01 to the input IN with the insulating layer 6
12, connecting the collector 3 of Ql to the resistor R1 formed under R1 and the base 4 of 02, 13 connecting the emitter 5 of Q2 to the ground G, There is 15 that connects the collector 3 of Q2 to a resistor R3 formed similarly to R1 and to the output OUT. Further, on the insulating layer 6, a power supply line Vcc made of, for example, aluminum is formed, which is connected to the resistors R1, R2, and R3.

In a bipolar IC that uses such circuits as units to form a logic circuit, it is necessary to have a plurality of circuit units and to connect them to each other, so the wiring on the insulating layer 6 is as described above. In addition to the electrodes/wirings 11 to 15 and the power supply line Vcc, a large number of others are also required. However, as the number of circuit units increases, the number of other wirings also tends to increase.

Therefore, in the conventional bipolar IC structure, due to the existence of wiring (13 in the figure) in the circuit unit as shown in FIG. It has the disadvantage that high integration, which increases the number of units, is suppressed.

Td+ OBJECTS OF THE INVENTION In view of the above-mentioned conventional drawbacks, an object of the present invention is to alleviate the restrictions on wiring paths between circuit units in a bipolar IC that includes a plurality of circuit units, each consisting of a plurality of transistors. An object of the present invention is to provide a structure of a semiconductor device and a method for manufacturing the same.

(e) Structure of the Invention The above object is to have a wiring region and a plurality of transistors in contact with the wiring region in a side-by-side manner in a surface layer of a semiconductor substrate, and a collector of the transistor at a junction surface between the wiring region and the transistor; A patterned conductor is disposed in the wiring region in which the base and emitter regions are exposed and filled with an insulating material, and the conductor forms an electrode of the transistor, and a conductor between the plurality of transistors. A semiconductor device characterized in that the above-mentioned wiring is performed and other connection electrodes are led out to the surface, and a first one-conductivity type semiconductor region and an insulator region are formed side by side and in contact with each other, and an impurity By diffusion, formation of a first semiconductor region of one conductivity type and in contact with the insulator region, and formation of a second semiconductor region of one conductivity type in the opposite conductivity type semiconductor region and in contact with the insulator region. A type semiconductor region is formed to form the collector, base, and emitter of the transistor, and then the insulator region is removed by selective etching, and an insulating layer and a patterned conductor layer are formed in the removed region. A semiconductor device comprising the step of alternately laminating electrodes and interconnections for each of the first one-conductivity type semiconductor region, the opposite conductivity type semiconductor region, and the second -conductivity type semiconductor region. This is achieved by the manufacturing method.

(f) Embodiments of the Invention Examples of the present invention will be described below with reference to the drawings. The same reference numerals indicate the same objects throughout the figures.

FIG. 3 shows an IC according to the invention forming the circuit shown in FIG.
A plan view f8) and a cross-sectional view (b) of one embodiment of the structure, and FIG. , 4a is a base, 4b is a p-type silicon region, 5a is an emitter, 8 is a wiring region, 98 to 9d are insulating layers, lla to
15a is an electrode/wiring, llb to 15b are wirings, and 21 is an insulator region.

An embodiment of the structure of an IC according to the present invention when forming the circuit shown in FIG. 1 is as shown in FIG. 3.

A collector 3a of n-type silicon, a base das of p-type silicon, and an emitter of n-type silicon are formed on a base l of p-type silicon, sandwiching a wiring region 8 filled with an insulator and surrounded by isolation 2 of p-type silicon. A transistor Q1.02 composed of transistors 5a and 5a is formed symmetrically, and the ends of the collector 3a, base 4a, and emitter 5a are exposed on the side surface of the wiring region 8.

Within the wiring region 8, each electrode of the transistors Q1 and Q2 is led out, wiring is also performed between the transistors Q1 and Q2, and other connection electrodes are led out to the surface of the wiring region 8. A patterned conductor, for example, polycrystalline silicon, is used for the electrodes/wirings for making these connections in the wiring region 8. That is, the electrode/wiring includes a wire 11a whose end is led out to the surface in order to connect the emitter 5a of the transistor 01 to the input IN, and a base 4a of the transistor 01 connected to the resistor R.
12a whose end is led out to the surface to connect to 1, Q
The collector 3a of L is connected to the base 4a of Q2 in the wiring area 8, and the end is led out to the surface in order to further connect it to the resistor R2.The end is led out to the surface in order to connect the emitter 5a of Q2 to the ground G. There are 14a and 15a whose ends are led out to the surface in order to connect the collector 3a of Q2 to the resistor R3 and the output 0υT.

Then, on the insulating layer 6 on the transistors Ql, Q2 and the wiring region 8, a wiring made of, for example, aluminum is formed, which leads out the electrode/wiring through a contact hole in the insulating layer 6 and connects it to a predetermined location. However, in the wiring,
As shown in FIG. A resistor R formed in the same way as the derivation R1
13b connected to 2, lead out the electrode/wiring 14a and ground G
14b, which is connected to 14b, and 1 which leads out the electrode/wiring 15a and connects it to the resistor R3 formed in the same way as R1 and the output 0tlT.
There is 5b. Further, as shown in FIG. 2+a1, a power supply line Vcc made of, for example, aluminum and connected to the resistors R1, R2, and R3 is formed on the insulating layer 6 to form a desired circuit.

Therefore, in the case shown in Figure 2 and the case shown in Figure 3, the first
The same circuit shown in the figure is formed, but in the case shown in Figure 3, the wiring between transistors Q1 and Q2 is provided under the insulation [6], so compare the wiring states shown in each figure. As is clear from the above, if the circuit is made into a circuit unit and an IC having a plurality of circuit units is formed with the structure shown in FIG. However, the transistor shown in FIG. 3 does not need to be limited to the size of the contact hole and can be made smaller, and the number of contact holes arranged in a row is reduced. The size of the area required to form the circuit unit becomes smaller, making it easier to achieve higher integration by increasing the number of circuit units, for example.

Furthermore, the transistor shown in FIG. 3 is smaller in size and has a lower collector series resistance than conventional transistors due to the difference in structure, and has improved various characteristics such as amplification factor, transition frequency, and noise. margin,
Temperature characteristics and other properties are improved, making it possible to improve the performance of ICs.

The IC structure shown in FIG. 3 can be manufactured by the steps shown in FIG.

First, as shown in Figure ia), n-type silicon jii3c is epitaxially grown on a p-type silicon substrate 1, and p
A shaped silicon isolation 2 is formed in a conventional manner. Next, as shown in FIG.
Two n-type silicon regions 3b surrounded by and insulating region 21 and sandwiching insulating region 21 are also formed. Next, for example, boron is diffused into the insulator region 3b in contact with the insulator region 8 as shown in the figure (C1
For example, phosphorus is diffused into the illustrated p-type silicon region 4b in contact with the insulator region 8 to form an emitter 5a illustrated in FIG. +d1.

Through this step, the remaining portion of the n-type silicon region 3b becomes the collector 3a, and the remaining portion of the p-type silicon region 4b becomes the base 4a, thereby forming the transistor Q1 and the opening 2.

After this, the insulator region 21 is etched by selective etching.
) When removed as shown in the figure, the ends of the collector 3a, base 4a, and emitter 5a are exposed on the removed side surface, so the electrode/wiring 11a is placed in the removed area, that is, the wiring area 8.
= 15a and the remaining part is filled with an insulator.

That is, first, for example, phosphosilicate glass is grown by a conventional method so as to fill the wiring region 8 to a height slightly above the lower side of the exposed end of the collector 3a, thereby forming the insulating layer 9a shown in FIG. The layer 9a may be formed by leaving the bottom portion of the insulator region 21 during etching.Next, a polycrystalline silicon layer, for example, is formed on the insulator layer 9a at a height below the upper side of the exposed end of the collector 3a. This layer is grown in a conventional manner and patterned to form the necessary electrode/wirings 13a and 15a in this layer as shown in FIG. The insulating layer 9 shown in FIG.
form b. Thereafter, in the same way, for example, by growing and patterning a polycrystalline silicon layer, a portion of the electrode/wiring 12a, a portion of 13a including a lead-out portion from the lower layer, and a lead-out portion from the lower layer of 15a are formed. As shown in FIG. Tg1, electrode/wirings 11a to 15a are formed while adding insulators jW9c and 9d to complete the wiring region 8.

After this, the process is similar to the conventional one, and as shown in Figure (h1), the insulating layer 6 is formed, the wirings 11b to 15b and the power supply line Vcc (not shown) are formed, and the structure shown in Figure 3 is completed. .

It can be easily inferred from the above description that such an IC structure and its manufacturing method are not limited to the case where the circuit forming the unit is shown in FIG.

(a) Effects of the Invention As explained above, according to the configuration according to the present invention, in a bipolar IC in which a circuit unit is configured with a plurality of transistors and has a plurality of circuit units, restrictions are placed on wiring paths between the circuit units. It is possible to provide a structure of a semiconductor device and a method for manufacturing the same, which can reduce the number of circuit units 1-, and also reduce the size of the circuit unit area and improve the transistor characteristics. This has the effect of facilitating high integration and improving IC characteristics.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a basic TTL circuit, Fig. 2 is a plan view (al and cross-sectional view Tbl) of an example of a conventional IC structure forming the circuit shown in Fig. FIG. 4 is a plan view (al) and a cross-sectional view (bl) of an embodiment of an IC structure according to the present invention forming the circuit shown in FIG. 4, and FIG. , 1 is the base, 2 is the isolation, 3.
3a is a collector, 3b is an n-type silicon region, 3c is an n-type silicon layer, 4.4a is a base, 4b is a p-type silicon region, 5.5a is an emitter, 6 is an insulating layer, 7 is a buried layer,
8 is a wiring area, 98-9d is an insulating layer, 11-15, ll
a to 15a are electrodes and wiring, 11b to 15b are wiring,
21 is an insulator region, dl, C2 is a transistor, R1,
R2 and R3 are resistors, IN is an input, OUT is an output, G is a ground, and Vcc is a power supply line. 1st rjJ Figure 2 ￥th

Claims (1)

[Scope of Claims] (υ The surface layer of a semiconductor substrate has a wiring region and a plurality of bipolar transistors that are in contact with the wiring region side by side, and a collector of the bipolar transistor is provided at a junction surface between the wiring region and the bipolar transistor. , a patterned conductor is disposed in the wiring region filled with an insulator, and the conductor forms an electrode of the bipolar transistor, and the plurality of bipolar transistors are connected to the plurality of bipolar transistors. A semiconductor device characterized in that one or more wirings are carried out between the semiconductor devices and other connection electrodes are led out to the surface. (2) Forming a first one-conductivity type semiconductor region and an insulator region that are side by side and in contact with each other. Then, by impurity diffusion, an opposite conductivity type semiconductor region is formed in the first one conductivity type semiconductor region and is in contact with the insulator region, and a second conductivity type semiconductor region is in the opposite conductivity type semiconductor region and is in contact with the insulator region. 〇-By forming one-conductivity type semiconductor regions, the collector, base, and
After that, the insulating region is removed by selective etching, and insulating layers and conductive layers that have been vacuum-coated are alternately laminated in the removed region, and the first one-conductivity type semiconductor region is formed. A method of manufacturing a semiconductor device, comprising the step of forming electrodes and interconnections for each of the opposite conductivity type semiconductor region and the second one conductivity type semiconductor region.