JPS60160098A - Programming voltage generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention relates to an erasable programmable read-only memory (EPROM, EEPROM) comprising a voltage source connected via a charging resistor to a memory stage to be programmed which is bridged by a (stray) capacitance. The programming voltage circuit for

EFROM (Erasable Programmable Read Only Memory) and I! The use of non-volatile programmable memories of the EPROM (Electrically Erasable Programmable Read Only Memory) type has increased significantly in recent times.

This is because these memories have the advantage of being easy to program and erase, as well as easy to update programming of the memory units of electrical computers or microprocessors, thus increasing the flexibility of inputting new programs. This is because it will be done. This kind of HEPR
OM or E1! PROMs are typically integrated into semiconductor bodies, often along with other arithmetic and control units that form part of a computer or microprocessor.

Programming an EPROM or HEPROM typically requires a voltage 1 higher than the operating voltage of other semiconductor devices in the semiconductor body.
very high operating voltage, i.e. EPROM or I! llROM
(junction yield)
A voltage only slightly lower than the breakdown voltage of the semiconductor junction is required.

However, llPROM and El! Not only do FROMs require high programming voltages, but we have found that EPROt4 and HEPROMs are prone to failure due to the high speed with which such programming voltages are applied to these memories. If the edges of the increasing programming voltage become too steep, (B) the injector-oxide
), a peak current occurs at (1 or IIPRO?).
l The service life (number of available reprogramming operations) of memory cells is adversely affected.

A possible solution to this problem is to bridge the memory stage to be programmed with a fairly large capacitor, for example 10009P, but it is quite difficult to form such a high capacitance capacitor in the semiconductor body. A large semiconductor surface area is required, which is of course undesirable. Another solution is to wire a voltage follower, e.g. a source follower, to the charging circuit between the voltage source and the memory stage and ground the gate of this voltage follower via a very small capacitor (e.g. 10 pF). There is also.

However, the voltage loss between the drain and source of such a source follower reduces the effective programming voltage, and furthermore, the programming speed may be reduced by a factor of, for example,
It will drop below 100.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit for generating a programming voltage of the type described above, which is suitably connected and arranged so as to be able to maintain the rise time of the programming voltage within safe limits and to eliminate the disadvantages mentioned above. be.

The circuit according to the invention connects a first transistor in parallel to the charging circuit of the memory stage bridged by the (stray) capacitance, the control electrode of the first transistor being connected in series with the conduction path of the second transistor, The first transistor is controlled by the voltage of a capacitor connected in parallel to the capacitance of the charging circuit, and the first and second transistors are connected as a current mirror, and the current mirror flows from the second transistor to the first transistor. It is characterized by being amplified.

Although such a circuit according to the present invention can be constructed using bipolar transistors, it is actually preferably constructed using field effect transistors. The reason is,
This is because the field effect transistor can have a sufficiently high current amplification factor (for example, 1000 times) by using an upper electromotive current mirror, and therefore a small capacitance capacitor can be used.

The invention will be explained below with reference to the drawings.

FIG. 1 shows a first example of a programming voltage generation circuit according to the present invention, in which 1! PRO? 1 shows an equivalent circuit of a memory 1 or an EBPROM type memory 1. In reality, the memory 1 itself has a leakage resistance 1' of more than 21'l ohm and a stray capacitance 2 of, for example, 10 pF. (indicated by the symbol) has a junction breakdown voltage of, for example, 20V. A voltage source 3, for example of the voltage multiplier or charge-pump type, serves to supply the memory 1 with a programming voltage.

This voltage source 3 is connected to the memory 1 via a charging resistor 4.

In practice, the charging resistor 4 (e.g. 4M ohm) and the memory 1
The time constant of the charging circuit formed by the capacitance 2 and the leakage resistance 1' is small, and the service life of the memory 1 is adversely affected when such a programming voltage is applied to the memory 1. Therefore, according to the present invention, a first transistor QI is connected in parallel to the stray capacitance 2 of the charging circuit, and the gate of this transistor is controlled by the voltage across the capacitor C. A capacitor C is connected in series to the channel of the second transistor Qt, and the series circuit is connected in parallel to the capacitance 2. First and second transistors Q r , Q
t is connected as a current mirror that amplifies the current from one of the transistors Q2 to Q.

A current-amplifying mirror consisting of bipolar transistors is
This can be easily realized by appropriately selecting the areas of the emitter regions of these transistors. However, as mentioned above, field effect transistors are more suitable. This is because the current amplification factor of such a transistor can be very high, for example 1000 times. The sources of transistors Q1 and Q8 are interconnected as are the gates, and the channel width to length ratio of transistor Q+ is much larger than that of transistor Q3. For example, the length of the channel of transistor Q (from the source to the drain) is 3 μm, and the width of the channel is 100 μm.
Let it be μm. In this case, transistor Q
The current flowing through transistor Q2 is 1000 times larger than the current flowing through transistor Q2.

When the voltage source 3 is switched on, most of the charging current flows through the resistor 4 initially through the transistor Q.

Only a small portion of the charging current flows through the circuit Qt-C and reaches the capacitance 2 and the resistor 1'. Therefore, capacitor C (eg 1 pF) is a charging resistor 4. It charges much more slowly (1000 times slower in the numerical example given above) than the rate corresponding to the time constant of capacitor C and capacitance 2 alone. As capacitor C charges further, transistors Q and Q2 gradually turn off so that sufficient programming voltage reaches memory 1. After the programming voltage source 3 has been deactivated, the capacitor C is discharged by the transistor 6.

The illustrated current mirrors can be extended in known ways to suppress disturbances due to processing developments. for example,
Other transistors can be cascaded in series with transistor Q2 to suppress disturbance feedback from drain to gate. In the example shown in FIG. 2, an additional transistor Q, connected as a voltage follower, is connected between transistor Q2 and capacitor C, the gate of this transistor Q is connected to capacitor C, and The voltage follower electrode (source in the illustrated case) of transistor Q3 is connected to the gate of transistor Q1.

If the (gate-source) limiting voltage of transistor Q, at which the transistor begins to conduct, (as in the normal case) transistor Q! and Q3, transistor Q becomes transistor Q! And the current stops flowing earlier than Q3. The current flowing through transistor Q1 is transistor Q! In order for the current value to remain many times larger than the current flowing through the transistor Q, the width/length ratio of the channel of the transistor Q must be sufficiently larger than that of the transistor Q, for example at least 10 times. It needs to be larger than that.

Transistors Q and Q2 (and also Q3) could in principle also be constructed as N-channel field effect transistors instead of P-channel field effect transistors as shown.

Finally, FIG. 3 shows that the voltage rise per unit time can always be kept below the safe limit value, regardless of the stray capacitance value of the (E/IliPROM) memory connected to the progera idle voltage source 3. This figure shows the circuit that does this. For this reason, the transistor QI has a multiple structure.

That is, other transistors QI'+Ql #, etc. are connected in parallel to the original transistor Ql. These other transistors are (one or more) transistors 7.7', ? These transistors QI'+Q can be switched on as desired depending on the magnitude of the (stray) capacitance of the memory (stage) by interconnecting them to
The width/length ratio of channels such as I# is 150/3°30
0/3, etc., from transistor Q2 to transistor Q,' (and/or Ql).
', etc.) to be able to adjust the current amplification factor. If the width/length ratio of the channel of the transistor shown in FIG. 3 is set to the above value, then the virtual capacitor C
The fO value is as follows. That is, Cf, = (50-B + 1) where B is a binary lO-adic value, and when the associated transistor turns on or off, respectively, b3. bz,b
The values of + and bi (3≧i≧O) are 1 or 0.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first example of a one-way system according to the present invention, FIG. 2 is a circuit diagram showing an improved example of FIG. 1, and FIG. 3 is a circuit diagram showing a modification of FIG. 1. l...-Memory 1'...-Leakage resistance 2...-Stray capacitance 3-Programming voltage source 4--Charging resistance 5...-Zener diode 6
, 7-) Transistor Ql--first transistor Q,
-Second transistor Q, -Third transistor C-, capacitor

Claims (1)

Claims: 1. Erasable programmable read-only memory (1!PR()M In a circuit for generating a programming voltage for an EHPROM (EHPROM), a first transistor is connected in parallel to the charging circuit of the memory stage bridged by the (stray) capacitance;
The control electrode of the first transistor is controlled by the voltage of a capacitor connected in series with the conduction path of the second transistor and in parallel with the capacitance of the charging circuit, and the first and second transistors are connected as a current mirror. , the current mirror causes the current to flow from the second transistor to the first transistor.
A programming voltage generation circuit characterized by amplifying the current flowing to the transistor. 2. A third transistor connected as a voltage follower is provided between the second transistor and the capacitor, the gate of the third transistor is connected to the capacitor, and the voltage follower pole of the third transistor is connected to the capacitor. 2. The programming voltage generating circuit according to claim 1, wherein the programming voltage generating circuit is connected to the gate of the first transistor. 3. The circuit according to claim 1, wherein each of the transistors is a field effect transistor, wherein the first
the channel width/length ratio of the transistor is much larger than the channel width/length ratio of the second transistor;
A programming voltage generation circuit characterized in that the programming voltage is increased by at least one order of magnitude. 4. In the circuit according to claim 2 or 3, in which the third transistor is also a field effect transistor, the ratio of the radius/length of the channel of the third transistor is the width of the channel of the second transistor. A programming voltage generation circuit characterized in that the length is greater than or equal to the length ratio. 5. In the circuit according to claim 1, in which each of the transistors is a field effect transistor, one or more other transistors are connected in parallel to the first transistor, and these other transistors are connected as required. switch·
1. A programming voltage generating circuit characterized in that the programming voltage generating circuit is configured to be turned on and the channel width/length ratios of these other transistors are made relatively different.