JPS60156598U - Dynamic display control circuit - Google Patents
Dynamic display control circuitInfo
- Publication number
- JPS60156598U JPS60156598U JP1984044062U JP4406284U JPS60156598U JP S60156598 U JPS60156598 U JP S60156598U JP 1984044062 U JP1984044062 U JP 1984044062U JP 4406284 U JP4406284 U JP 4406284U JP S60156598 U JPS60156598 U JP S60156598U
- Authority
- JP
- Japan
- Prior art keywords
- dynamic display
- control circuit
- display control
- driver
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のダイナミック表示制御回路を示す図、第
2図は第1図の回路の動作を示す図、第3図は本考案に
よるダイナミック表示制御回路の一実施例を示す図、第
4図は第3図の回路の動作を示す図、第5図はタイマー
T1の動作、復帰状態を示す図である。
y□〜Xn・・・・・・表示データセット用ドライバ、
Y1′〜Yn・・・…コントロール用ドライバ、LED
工、〜LED1n、LED21〜LED2n、LEDn
1〜LEDon・・・・・・LED表示器、y□〜。、
yn+1・・・・・・AND素子、INV・・・・・・
インバータ素子、T□・・・・・・タイマー、TOUア
・・・・・・タイマー出力、INVoUT・・・・・・
インバータ出力、ALM・・・・・・タイマー検出異常
出力。FIG. 1 is a diagram showing a conventional dynamic display control circuit, FIG. 2 is a diagram showing the operation of the circuit in FIG. 1, FIG. 3 is a diagram showing an embodiment of the dynamic display control circuit according to the present invention, and FIG. This figure shows the operation of the circuit shown in FIG. 3, and FIG. 5 shows the operation and return state of the timer T1. y□~Xn・・・Display data set driver,
Y1'~Yn...Control driver, LED
Engineering, ~LED1n, LED21~LED2n, LEDn
1~LEDon...LED indicator, y□~. ,
yn+1...AND element, INV...
Inverter element, T□...Timer, TOUA...Timer output, INVoUT...
Inverter output, ALM...Timer detection abnormal output.
Claims (1)
器を、表示セット用ドライバとコント・ ロール用ドラ
イバとで順次点灯させるダイナミック表示制御回路にお
いて、各コントロールドライバの入力側に夫々もうけた
AND素子と、前記にの素子に対してタイマーとインバ
ータ素子とを介して制御コントロール信号が供給される
ことを特徴とするダイナミック表示制御回路。In a dynamic display control circuit that sequentially lights up a plurality of LED indicators connected to the intersections of a matrix circuit using a display set driver and a control driver, an AND element provided on the input side of each control driver is used. , a dynamic display control circuit characterized in that a control signal is supplied to the above elements via a timer and an inverter element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984044062U JPS60156598U (en) | 1984-03-29 | 1984-03-29 | Dynamic display control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984044062U JPS60156598U (en) | 1984-03-29 | 1984-03-29 | Dynamic display control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60156598U true JPS60156598U (en) | 1985-10-18 |
Family
ID=30556299
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984044062U Pending JPS60156598U (en) | 1984-03-29 | 1984-03-29 | Dynamic display control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60156598U (en) |
-
1984
- 1984-03-29 JP JP1984044062U patent/JPS60156598U/en active Pending
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