JPS60154734A - Fault detection system of inserting and branching device - Google Patents

Fault detection system of inserting and branching device

Info

Publication number
JPS60154734A
JPS60154734A JP1126284A JP1126284A JPS60154734A JP S60154734 A JPS60154734 A JP S60154734A JP 1126284 A JP1126284 A JP 1126284A JP 1126284 A JP1126284 A JP 1126284A JP S60154734 A JPS60154734 A JP S60154734A
Authority
JP
Japan
Prior art keywords
signal
add
circuit
counter station
station warning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1126284A
Other languages
Japanese (ja)
Inventor
Shunichi Nakayama
俊一 中山
Mikio Murozaki
室崎 三樹夫
Takeo Fukushima
福島 竹雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1126284A priority Critical patent/JPS60154734A/en
Publication of JPS60154734A publication Critical patent/JPS60154734A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/14Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To attain the detection of a fault by devices at both sides by supervising in polarity at the counter station warning signal of a digital multiplexer, passing through the signal when an inserting and branching device is failed, and eliminating the inversion of the counter station warning signal. CONSTITUTION:DMUX11, MUX12 are provided respectively with a counter station warning extracting circuit and a counter station warning inserting circuit being used for a digital multiplexer. Then the counter station warning signal having a level of ''0'' at normality and of inverted ''1'' at fault, extracted via the counter station warning extracting circuit is supervised by a counter station warning signal supervisory circuit 13, and the signal is inverted by an inversion circuit 14 and inserted via the counter station warning insertion circuit an the result is transmitted to the next stage from the MUX12.

Description

【発明の詳細な説明】 (a1発明の技術分野 本発明は対向のディジタル多重化装置間に対向の挿入分
岐装置を有するディジタル通信システムに係り、該挿入
分岐装置が障害の場合、少なくとも両側の装置で障害検
出を可能にした挿入分岐装置の障害検出方式に関する。
Detailed Description of the Invention (a1 Technical Field of the Invention) The present invention relates to a digital communication system having opposing add/drop devices between opposing digital multiplexers, and in the event of a failure in the add/drop devices, at least the devices on both sides The present invention relates to a fault detection method for an insertion/drop device that enables fault detection in the present invention.

山)技術の背景 挿入分岐装置とはディジタル多重化装置の空きチャンネ
ルを利用してデータを伝送J−るもので、該ディジクル
多重化装置と同一なフレーム構成であり、障害時にはス
ルーバスするようになっている。
Background of the technology An add/drop device is a device that transmits data using an empty channel of a digital multiplexer.It has the same frame structure as the digital multiplexer, and in the event of a failure, it can be used as a through bus. It has become.

対局警報信号とは、ディジタル多重化装置の障害を相手
側のディジタル多重化装置に知らせる信号で、フレーム
中の特定位置のビットを使用しており、障害時にはこの
ビットを反転することで相手側で障害が判るようになっ
ている。例えば、圧密時は“0”の信号を送信し、障害
時は反転された“1″の信号を送信するようになってお
り、このことにより相手側のディジタル多重化装置は障
害を検出出来るようになっている。
The game alarm signal is a signal that notifies the other party's digital multiplexer of a fault in the digital multiplexer. It uses a bit at a specific position in the frame. In the event of a fault, this bit is inverted and the other party's The problem is becoming obvious. For example, a "0" signal is sent when consolidation occurs, and an inverted "1" signal is sent when a failure occurs.This allows the digital multiplexing device on the other end to detect the failure. It has become.

(C)従来技術と問題点 第1図は従来例の挿入分岐装置を使用した通信システム
のブロック図であり、第2図は挿入分岐装置の障害時の
スルーパス動作説明図である。
(C) Prior Art and Problems FIG. 1 is a block diagram of a communication system using a conventional add/drop device, and FIG. 2 is an explanatory diagram of through-path operation when the add/drop device fails.

図中1,2はディジタル多重化装置、3,4は挿入分岐
装置、5.6は信号挿入分岐部、1oは挿入分岐部、S
WI〜SW4はスイッチ、7−1゜7−2.8−1.8
−2.9−1.9−2は伝送路を示す。
In the figure, 1 and 2 are digital multiplexers, 3 and 4 are add/drop devices, 5.6 is a signal add/drop unit, 1o is an add/drop unit, and S
WI~SW4 are switches, 7-1°7-2.8-1.8
-2.9-1.9-2 indicates a transmission path.

第1図において、代表して、一方向のデータ伝送を説明
すると、ディジクル多重化装置1にて多重化されたデー
タは伝送路7−1.挿入分岐装置3、伝送線路8−1.
挿入分岐装置4.伝送路9−1を通り、ディジタル多重
化装置2に送信される。又対局警報信号も同様のルート
でディジタル多重化装置1から2に送信される。一方挿
入分岐装置3,4間では、ディジタル多重化装置1,2
の空きチャンネルを使用し、同一フレーム構成で、信号
挿入分岐部5.6間でデータ通信を行っている。
In FIG. 1, one-way data transmission will be explained as a representative example. Data multiplexed by digital multiplexer 1 is transmitted through transmission path 7-1. Add/drop device 3, transmission line 8-1.
Insertion/branching device 4. The signal is transmitted to the digital multiplexer 2 through the transmission path 9-1. Further, a game warning signal is also transmitted from digital multiplexer 1 to 2 through the same route. On the other hand, between the add/drop devices 3 and 4, the digital multiplexers 1 and 2
Data communication is performed between the signal insertion/branching units 5 and 6 using empty channels with the same frame structure.

挿入分岐装置3,4は障害時には第2図に示す如くスイ
ッチSW1〜SW’4を実線側より点線側に切り替え挿
入分岐部10をスルーパスするようになっている。
In the case of a failure, the insertion/branching devices 3, 4 switch the switches SW1 to SW'4 from the solid line side to the dotted line side, as shown in FIG. 2, so that the insertion/branching section 10 is passed through.

ここで例えば挿入分岐装置3が障害となったとすると、
挿入分岐装置3はスルーバスされ、代表として一方向を
説明すると、多重化されたデータ(対局警報信号を含む
)はディンタル多重化装置1より伝送線路7−1.8−
1挿入分岐装置4を通りディジタル多重化装置2に送錫
されるも、挿入分岐装置3の障害は他のどの装置でも知
ることが出来ない欠点がある。
For example, if the insertion/dropping device 3 becomes a failure,
The insertion/dropping device 3 is a through bus, and to explain one direction as a representative, multiplexed data (including game alarm signals) is transferred from the digital multiplexer 1 to the transmission line 7-1.8-
1, and is sent to the digital multiplexer 2 through the add/drop device 4, but there is a drawback that no other device can detect a failure in the add/drop device 3.

fd1発明の目的 本発明の目的は上記の欠点に鑑み、挿入分岐装置が障害
になった場合、少な(とも両側の装置で障害検出を可能
とした挿入分岐部;lの障害検出方式の提供にある。
fd1 Purpose of the Invention The purpose of the present invention is to provide a failure detection system for an insertion/branch unit that makes it possible to detect failures with devices on both sides when the insertion/drop unit becomes a failure. be.

(e1発明の構成 本発明は上記の目的を達成するために、ディジタル多重
化装置の対局警報信号を、挿入う〕岐装置にて取り出し
、反転伝送するようにする手段、及び取り出した対局警
報信号の極性を監視する手段を各挿入分岐装置に設け、
挿入分岐装置が障害になるとスルーバスされ対局警報信
号が反転されなくなることにより少なくとも両側の装置
で障害検出を可能としたものである。
(e1 Structure of the Invention) In order to achieve the above object, the present invention provides a means for extracting the game alarm signal of a digital multiplexer using an insertion/branching device and inverting and transmitting the game alarm signal. means for monitoring the polarity of the
If the add/drop device becomes faulty, the system becomes a through bus and the game alarm signal is no longer inverted, making it possible to detect the fault in at least the devices on both sides.

(f1発明の実施例 以下本発明の一実施例につき図に従って説明する。(Example of f1 invention An embodiment of the present invention will be described below with reference to the drawings.

第3図は本発明の実施例の挿入分岐装置の要部のブロッ
ク図で一方向を示しており、1工は多重信号分離部(以
下DM(JXと称す)、12は多重化部(以下MUXと
称す)、13は対局警報信号監視回路、14は反転回路
、15は信号分岐端子、16は信号挿入端子を示す。
FIG. 3 is a block diagram of the main parts of the insertion/dropping device according to the embodiment of the present invention, showing one direction. 1 is a multiplex signal separation unit (hereinafter referred to as DM (JX)), and 12 is a multiplexer (hereinafter referred to as JX). 13 is a game alarm signal monitoring circuit, 14 is an inversion circuit, 15 is a signal branch terminal, and 16 is a signal insertion terminal.

第3図において、多重化されたディジクル信号はDMU
XIIにて分離され、挿入分岐装置で使用するチャンネ
ルの信号は信号分岐端子より取り出され、他のチャンネ
ルはMUXl2に送られ、信号挿入端子16より入力す
る挿入分岐装置で使用するチャンネルの信号と共に多゛
重化されて、多重化されたディジタル信号となり次段の
装置に送信される。コノ場合DMUX11.MUXl 
oには夫々ディジタル多重化装置に使用されている公知
の対局警報注出回路、対局警報挿入回路を持たせておき
、対局警報注出回路を介して取り出した例えば正常時は
“0”障害時は反転された′1”の対局警報信号を、対
局警報信号監視回路13にて監視し、又反転回路14に
て反転し、対局警報挿入回路を介して挿入しM U x
 tOより次段に送信するようになっている。勿論第2
図に示すスルーパス機能は持っている。
In FIG. 3, the multiplexed digital signal is transmitted to the DMU
XII, the signal of the channel used in the add/drop device is taken out from the signal branch terminal, and the other channels are sent to MUX12, and are multiplied together with the signal of the channel used in the add/drop device inputted from the signal insert terminal 16. The signal is multiplexed into a multiplexed digital signal and transmitted to the next stage device. In this case, DMUX11. MUXl
o is provided with a well-known game alarm output circuit and a game alarm insertion circuit used in digital multiplexing devices, respectively, and the output signal taken out through the game alarm output circuit is, for example, "0" in normal operation, but in case of failure. The inverted '1' match alarm signal is monitored by the match alarm signal monitoring circuit 13, inverted by the inverting circuit 14, and inserted via the match alarm insertion circuit M U x
It is designed to be transmitted to the next stage from tO. Of course the second
It has the through-pass function shown in the figure.

ここで第1図の挿入分岐装置3,4は上記の機能を持っ
たものとし又対局警報信号は正常時は“0”障害時は“
1”として、対局警報信号の流れに付き第1図を用いて
説明する。
Here, it is assumed that the insertion/dropping devices 3 and 4 in FIG.
1'', the flow of the game warning signal will be explained using FIG.

正常時上り方向では、ディジタル多重化装置1より送信
された“′0”の対局警報信号は挿入分岐装置3及び4
で反転され、10゛となった対局警報信号はディジタル
多重化装置2に入力する。一方下り方向では、ディジタ
ル多重化装置2より送信された“0″の対局警報信号は
挿入分岐装置4及び3で反転され“0″となった対局警
報信号はディジタル多重化装置1に入力する。この場合
、挿入分岐装置4の上り方向の対局警報を監視する対局
警報監視回路13及び挿入分岐装置3の下り方向の対局
警報を監視する対局警報監視回路13では“1”の信号
が来ている時を圧密と認識するようになっている。又挿
入分岐装置4の下り方向の対局警報を監視する対局警報
監視回路13及び挿入分岐装置3の上り方向の対局警報
を監視する対局警報監視回路13は“0”の信号が来て
いる時を正常と認識するようになている。
In the upstream direction during normal operation, the game alarm signal of “0” transmitted from the digital multiplexer 1 is sent to the add/drop devices 3 and 4.
The game alarm signal, which has been inverted at 10°, is input to the digital multiplexer 2. On the other hand, in the downstream direction, the game warning signal of "0" transmitted from the digital multiplexer 2 is inverted by the add/drop devices 4 and 3, and the game warning signal of "0" is input to the digital multiplexer 1. In this case, the game alarm monitoring circuit 13 that monitors the game alarm in the upstream direction of the add/drop device 4 and the game alarm monitor circuit 13 that monitors the game alarm in the downstream direction of the add/drop device 3 receive a signal of “1”. We have come to recognize time as compression. Also, the game alarm monitoring circuit 13 that monitors the game alarm in the downstream direction of the insertion/dropping device 4 and the game alarm monitoring circuit 13 that monitors the game warning in the upstream direction of the insertion/dropping device 3 detect when a signal of "0" is coming. It has come to be recognized as normal.

ここで例えは挿入分岐装置3が障害となり、スルーパス
されると、上り方向では挿入分岐装置4に入力する対局
警報信号は0”となり又下り方向ではディジタル多重化
装置1に入力する対局警報信号は“1”となり、両側の
、挿入分岐装置4の対局警報監視回路13及びディジタ
ル多重化装置1にて挿入分岐装置3の障害を知ることが
出来る。挿入分岐装置4が障害となりスルーバスされる
と」二記と同様の方法で、両側の、ディジタル多重化装
置2及び挿入分岐装置3の対局警報監視回路13で障害
を知ることが出来る。尚両側以外の装置でも対局警報信
号の反転により障害を知ることが出来る。
For example, if the add/drop device 3 becomes a failure and is passed through, the game alarm signal input to the add/drop device 4 in the upstream direction becomes 0'', and the game alarm signal input to the digital multiplexer 1 in the downstream direction becomes 0''. It becomes "1", and the game alarm monitoring circuit 13 of the add/drop device 4 and the digital multiplexer 1 on both sides can know the failure of the add/drop device 3.If the add/drop device 4 becomes a failure and a through bus is established. In the same manner as described in Section 2 above, the fault can be detected by the game alarm monitoring circuits 13 of the digital multiplexer 2 and the add/drop device 3 on both sides. Note that devices other than those on both sides can also detect a failure by inverting the game alarm signal.

(g1発明の効果 以上詳細に説明ゼる如(本発明によれば、挿入分岐装置
が障害になると、スルーバスされ対局警報信号が反転さ
れな(なるので、少なくとも両側の装置で障害を検出出
来る効果がある。
(According to the present invention, when the add/drop device becomes a failure, the game alarm signal is not inverted because it is passed through the bus, so at least the devices on both sides can detect the failure.) effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の挿入分岐装置を使用した通信システム
のブロック図、第2図は挿入分岐装置の障害時のスルー
パス動作説明図、第3図は本発明の実施例の挿入分岐装
置の要部のブロック図である。 図中1.2はディジタル多重化装置、3,4は挿入分岐
装置、5.6は信号挿入分岐部、7−1 。 7−2.8−1.8−2.9−1.9−2は伝送路、1
0は挿入分岐部、SWI〜SW4はスイッチ、11は多
重信号分離部、12は多重化部13は対局警報監視回路
、14は反転回路、15は信号分岐端子、16は信号挿
入端子を示す。 ’! ] I21= 条2酊 塔3酊
FIG. 1 is a block diagram of a communication system using a conventional add/drop device, FIG. 2 is an explanatory diagram of through-path operation in the event of a failure in the add/drop device, and FIG. 3 is a schematic diagram of an add/drop device according to an embodiment of the present invention. FIG. In the figure, 1.2 is a digital multiplexer, 3 and 4 are add/drop devices, 5.6 is a signal add/drop unit, and 7-1. 7-2.8-1.8-2.9-1.9-2 is the transmission line, 1
0 indicates an insertion/branching section, SWI to SW4 are switches, 11 is a multiplexed signal separation section, 12 is a multiplexing section 13 is a game alarm monitoring circuit, 14 is an inversion circuit, 15 is a signal branching terminal, and 16 is a signal insertion terminal. '! ] I21= article 2 drunkenness tower 3 drunkenness

Claims (1)

【特許請求の範囲】[Claims] 対向のディジタル多重化装置間に、対向の挿入分岐装置
を有するディジタル通信システムにおいて、該ディジタ
ル多重化装置の対局警報信号を、挿入分岐装置にて取り
出し、反転伝送するようにする手段及び取り出した対局
警報信号の極性を監視する手段を各挿入分岐装置に設け
たことを特徴とする挿入分岐装置の障害検出方式。
In a digital communication system having opposing add/drop devices between opposing digital multiplexers, a means for extracting a game alarm signal of the digital multiplexer by the add/drop device and inverting the transmission; 1. A failure detection method for an add/drop device, characterized in that each add/drop device is provided with means for monitoring the polarity of an alarm signal.
JP1126284A 1984-01-25 1984-01-25 Fault detection system of inserting and branching device Pending JPS60154734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1126284A JPS60154734A (en) 1984-01-25 1984-01-25 Fault detection system of inserting and branching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1126284A JPS60154734A (en) 1984-01-25 1984-01-25 Fault detection system of inserting and branching device

Publications (1)

Publication Number Publication Date
JPS60154734A true JPS60154734A (en) 1985-08-14

Family

ID=11773034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1126284A Pending JPS60154734A (en) 1984-01-25 1984-01-25 Fault detection system of inserting and branching device

Country Status (1)

Country Link
JP (1) JPS60154734A (en)

Similar Documents

Publication Publication Date Title
US5367395A (en) Apparatus for detection and location of faults in two-way communication through single optical path
JPS60154734A (en) Fault detection system of inserting and branching device
JPH09261132A (en) Redundancy switching system for data transmission system
JP2001136234A (en) Bulk transmitting device and auto fallback method
JP2656563B2 (en) Multiplexing / separating device
JP2827735B2 (en) Clock switching method
JPH0244933A (en) Fault detection system for multiplexer
JP2826383B2 (en) Alarm transfer method
JPS5868327A (en) Synchronism fault detection system
JPH0440022A (en) Duplexing/synchronizing method for extraction/insertion part for auxiliary signal of intermediate repeater station
JP2762579B2 (en) Transmission device loopback method
JP2690278B2 (en) Failure monitoring method
JP2973871B2 (en) Clock selection circuit
JP2821338B2 (en) Secondary alarm output control method
JPS60182832A (en) Supervisory system of multiplex separating device
WO2000019667A1 (en) Method and system for detecting failure of ring network
JPH09289492A (en) Branching type optical communication device
JPS59125152A (en) Subordinate connection control system of remote line concentrator
JPH03229533A (en) Method and system for informing high speed line fault
JPH0936827A (en) Transmission line fault section decision processing system
JPS6157141A (en) Multiplex converter provided with opposite station supervising function
JPH04304046A (en) Fault block deciding system for digital signal transmission system
JPH0461439A (en) Monitor for interconnecting state of unit
JPH02105647A (en) Line supervisory system
JPS6384224A (en) Master station equipment for time division multi-directional multiplex communication system