JPS60153591U

JPS60153591U - electronic equipment

Info

Publication number: JPS60153591U
Application number: JP4132684U
Authority: JP
Inventors: 弘吉元
Original assignee: 日本電気株式会社
Priority date: 1984-03-23
Filing date: 1984-03-23
Publication date: 1985-10-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は、従来の電子装置における電子回路ブロックの
一部切欠斜視図、第２図は、従来の電子装置の側面図、
第３図は、本考案の一実施例に係る電子装置の電子回路
ブロックを示す一部切欠斜視図、そして、第４図は、上
記実施例に係る電子装置の側面図である。９・・・マザーボード、１０・・・ゼロインサーション
フォースコネクタ、１２・・・電子回路ブロック、１３
・・・電子回路パッケージ、１４・・・ケーブル。第３図第４図FIG. 1 is a partially cutaway perspective view of an electronic circuit block in a conventional electronic device, and FIG. 2 is a side view of the conventional electronic device.
FIG. 3 is a partially cutaway perspective view showing an electronic circuit block of an electronic device according to an embodiment of the present invention, and FIG. 4 is a side view of the electronic device according to the above embodiment. 9... Motherboard, 10... Zero insertion force connector, 12... Electronic circuit block, 13
...Electronic circuit package, 14...cable. Figure 3 Figure 4

Claims

[Scope of utility model registration request]

In an electronic device in which electronic blocks accommodating a plurality of electronic circuit packages are stacked vertically, a motherboard is provided on both left and right sides of the electronic circuit block, and a plurality of electronic circuit packages arranged in parallel with the motherboard are provided for connection to the plurality of electronic circuit packages. An electronic device characterized in that an electronic circuit package is supported by a zero insertion force connector, and a cable is connected to a motherboard of stacked electronic circuit blocks.