JPS60152991U - Electronic clock with data memory - Google Patents
Electronic clock with data memoryInfo
- Publication number
- JPS60152991U JPS60152991U JP4039584U JP4039584U JPS60152991U JP S60152991 U JPS60152991 U JP S60152991U JP 4039584 U JP4039584 U JP 4039584U JP 4039584 U JP4039584 U JP 4039584U JP S60152991 U JPS60152991 U JP S60152991U
- Authority
- JP
- Japan
- Prior art keywords
- data
- data memory
- electronic clock
- memory
- erroneous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面はこの考案の一実施例を示したもので、第１図はデ
ータメモリを備えた電子時計の上面図、第２図は第１図
で不した表示装置１の構成図、第３図はこの電子時計の
ブロック回路図、第４図は第３図で示したスイッチ部２
２とスイッチ制御部１６の構成図、第５図は第３図で示
したデータメモリ回路部１５の構成図、第６図は第５図
で示したＲＡＭ４１の構成図、第７図Ａ、 Ｂ、 Ｃは
スイッチＳ１の操作に伴って変遷する表示状態図、第８
図Ａ、 Ｂはハイフォン表示状態図である。
１５・・・・・・データメモリ回路部、１６・・・・・
・スイッチ制御部、２２・・・・・・スイッチ部、５６
・・・・・・誤データ検出団結、５７・・・・・・アン
ドゲート。The drawings show one embodiment of this invention; FIG. 1 is a top view of an electronic watch equipped with a data memory, FIG. 2 is a block diagram of the display device 1 not shown in FIG. 1, and FIG. The block circuit diagram of this electronic watch, Figure 4, is the switch section 2 shown in Figure 3.
2 and the switch control unit 16, FIG. 5 is a configuration diagram of the data memory circuit unit 15 shown in FIG. 3, FIG. 6 is a configuration diagram of the RAM 41 shown in FIG. 5, and FIGS. 7A and B. , C is a display state diagram that changes as the switch S1 is operated, No. 8
Figures A and B are diagrams of the Haiphong display state. 15... Data memory circuit section, 16...
- Switch control section, 22...Switch section, 56
...False data detection unity, 57...And gate.
Claims (1)
段から入力されたデータを前記データメモリに書き込む
書き込み制御手段と、前記データ入力手段から入力され
たデータが予め設定された所定の形式で入力されたか否
かを検出する誤データ検出手段と、この検出手段で誤デ
ータであることが検出された際に前記データメモリへの
データ書き込みを禁止する手段とを具備したことを特徴
とするデータメモリを備えた電子時計。a data input means; a data memory; a write control means for writing data input from the data input means into the data memory; A data memory characterized by comprising: erroneous data detection means for detecting whether the data is incorrect; and means for prohibiting data writing to the data memory when the detection means detects that the data is erroneous. electronic clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4039584U JPS60152991U (en) | 1984-03-23 | 1984-03-23 | Electronic clock with data memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4039584U JPS60152991U (en) | 1984-03-23 | 1984-03-23 | Electronic clock with data memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60152991U true JPS60152991U (en) | 1985-10-11 |
Family
ID=30549242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4039584U Pending JPS60152991U (en) | 1984-03-23 | 1984-03-23 | Electronic clock with data memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60152991U (en) |
-
1984
- 1984-03-23 JP JP4039584U patent/JPS60152991U/en active Pending
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