JPS60150358A - Reception logical circuit - Google Patents

Abstract

PURPOSE:To reduce jitter in a decoding signal by providing a limiter to a prestage of a reception logical circuit converting a binary signal applied with differential logic into a ternary signal, identifying its absolute value and decoding it. CONSTITUTION:An input signal (a) is subjected to distortion on a transmission line and its waveform is dulled. This signal passes through a limiter 8, from which an output clipped in bipolar way is produced, and the signal is subject to amplitude limit and changes into a signal (b) with a sharp leading/trailing by selecting properly the limiter characteristic in this case. This signal is delayed by a time of 1-bit length by a delay circuit 2, the other is fed as it is to a differential amplifier 3, where both the signals are subtracted and a ternary signal (c) is produced and in this case, the signal changing from positive to negative of the ternary signal and the signal changing from positive to zero are almost coincident. Then the pulse width identifying the signal at a positive threshold value Vs is almost unchanged between the changes of the ternary signal from positive to negative and from positive to ''0''. Thus, the jitter of a decoding signal (d) being an output of the absolute value circuit 4 is decreased remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a reception logic circuit for receiving a digital signal, and in particular, it is difficult to extract a clock signal from a Nahorst wave when differential logic is applied. This relates to the reception logic circuit that signals the signal.

1 Optical Technology and Problems When transmitting data using digital signals, transmission lines generally cannot transmit DC components, so
If the signals of
” becomes difficult to distinguish.

Therefore, on the input side, a transmission differential logic circuit is used to
” is continuous, it is converted into a signal in which “1” and “o” change alternately, and when “0” is continuous, it is sent as is, and the receiving side uses a receiving differential logic circuit. Then, a method is used in which this signal is converted again and the original signal is decoded.

The receiving logic circuit when using such a method is as follows:
Generally, a circuit is used that performs logical operations using a clock synchronized with a received signal. However, in the case of communication systems that use burst signals, it is difficult to extract the clock.
Therefore, a receiving logic circuit that can perform decoding without using a clock is required. As a logic circuit on the reception side in such a case, a circuit such as shown in FIG. 1, which combines a waveform conversion circuit including a delay circuit and an absolute value circuit, is conventionally used. In the figure, 1 is a hybrid' (H), 2 is a delay circuit of time To (1 bit length), and 3 is a differential amplifier. 4 is an absolute value circuit, which includes comparators 5 and 6 and an OR circuit 7.

Furthermore, FIG. 2 shows the ideal waveform of each part signal in the circuit of FIG. 1, and is used to explain the operation of the reception logic circuit of FIG. , ()]) is the input signal b of the absolute value circuit 4,
(C1 is the output signal C of the absolute value circuit 4.

The input signal a is split into two by the hybrid 1, one of which is delayed by 1 bit length by the delay circuit 2, and the other is directly applied to the differential amplifier 3 where the difference is taken, as shown in Fig. 2 fbl. Generates a 3-value signal. This signal is inputted in parallel to comparators 5 and 6 connected with opposite polarities, and compared with reference voltages Vs and -Vs, respectively, and shaped. Positive polarity signals are left unchanged, and reverse polarity signals are inverted. Each generates an output, which is combined in an OR circuit 7 to produce a decoded output C shown in FIG. 2 fCl.

However, the actual input signal does not have the correct waveform as shown in Figure 2 (81), but is distorted and dulled in the transmission path. Therefore, the output of the receiving logic circuit shown in Figure 1 contains jitter. As a result, there is less timing margin in the received signal.

FIG. 3 shows an example of signal waveforms of various parts in the receiving logic circuit of FIG. 1, faL (b), (cl
are (al, (bl, (C1
The corresponding signal is shown.

When the input signal of pulse width To is dull as shown in FIG. 3 (al), the ternary code at the input of the absolute value circuit 4 becomes as shown in FIG. When identifying and binarizing, the pulse width of the decoded signal generated by binarization is different depending on whether the signal changes from positive to negative or from positive to 0 (center value). figure(
b), (C1 indicates the width of the valley of the pulse when the input of the absolute value circuit 4 changes from positive to O, and B indicates the width of the valley of the pulse when the input of the absolute value circuit 4 changes from positive to negative. The width of the valley of the pulse is shown.In FIG. 3, only the output signal from one comparator has been described, but the same situation applies to the other comparator.

In the reception logic circuit shown in FIG. 1, which converts a binary code applied with differential logic into a ternary code and decodes it,
Depending on the state of the ternary code, a jump jitter of (B-Δ/2) occurs in the decoded signal, so the width of the valley in the decoded signal is A-B.
There is a problem in that the RZ section signal changes, and the timing margin decreases.

OBJECT OF THE INVENTION The present invention attempts to solve the problems of the prior art, and its purpose is to provide a reception method that decodes a differential logic signal without using a clock synchronized with the input signal. An object of the present invention is to provide a logic circuit in which jitter is less likely to occur in a decoded signal.

Structure of the Invention The receiving logic circuit of the present invention converts a binary code applied with differential logic into a ternary code, and by providing a limiter at the front stage of the receiving logic circuit that converts a binary code applied with differential logic to a ternary code, identifies the absolute value, and decodes the code. This is intended to reduce jitter in the decoded signal.

Embodiment of the Invention FIG. 4 shows the configuration of an embodiment of the reception logic circuit of the invention. In this figure, the same parts as in FIG. 1 are designated by the same numbers, and 8 is a limiter.

Further, FIG. 5 shows the signals of each part in the reception logic circuit shown in FIG.
, fCl is the signal C1fdl at the input of the absolute value circuit 4
is the decoded signal d at the output of the absolute value circuit 4.

As shown in FIG. 5 (al), the input signal a is distorted in the transmission path and its waveform is blunted. This signal passes through the limiter 8 and produces an output that is clipped in both positive and negative directions.
In this case, by appropriately selecting the limiter characteristics, the amplitude is limited and the signal changes to a signal with steep rises and falls, as shown in FIG. The other one is applied to the differential amplifier 3 without any change and the difference is taken, resulting in the difference shown in FIG.
A ternary code C as shown in C) is generated, but in this case, the signal in which the ternary signal changes from positive to negative and the signal in which the ternary signal changes from positive to O are almost the same. Therefore, this signal is set to a positive threshold Vs
The pulse width when identified by , as shown in FIG. 4 Fdl, hardly changes when the ternary code changes from positive to negative and when it changes from positive to O. Therefore, jitter in the decoded signal d, which is the output of the absolute value circuit 4, is significantly reduced.

Although only the signal identification in one comparator 5 has been described above, it goes without saying that signal identification in the other comparator 6 is performed in the same manner.

As described in detail, according to the receiving logic circuit of the present invention, the difference between a binary input signal subjected to differential logic and a signal obtained by delaying this input signal by 1 bit is obtained. In a reception logic circuit that decodes an input signal by identifying the obtained ternary code by positive and negative dark values and calculating the absolute value of the obtained signal, Since a limiter is provided that limits the amplitude so that it has steep rises and falls, jitter in the output decoded signal can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional reception logic circuit, FIG. 2 is a diagram showing ideal waveforms of signals of each part in the reception logic circuit of FIG. 1, and FIG. 3 is a diagram of each part of the reception logic circuit of FIG. 1. FIG. 4 is a diagram showing the configuration of an embodiment of the receiving logic circuit of the present invention, and FIG. 5 is a diagram showing various signals in the receiving logic circuit of FIG. 4. 1-Hybrid (H), 2-Delay circuit, 3-Differential amplifier, 4-Absolute value circuit, 5.6-Comparator, 7-OR circuit,
8- Limiter 1st Figure S Vs 2nd Figure 4 Figure 5 (JLi (Il+) (S)

Claims (1)

[Claims] A binary input signal applied with differential logic and the input signal are
The input signal is converted into a 1M signal by distinguishing the ternary code obtained by calculating the difference between the signal and the delayed signal by the positive and negative dark values, and calculating the absolute value of the obtained signal. 1. A reception logic circuit comprising: a limiter for limiting the amplitude of an input signal so that the input signal has sufficiently steep rises and falls in a preceding stage of the reception logic circuit.