JPS60146348A - Hierarchy memory control system - Google Patents

Abstract

PURPOSE:To attain both a random access and a sequential access with the same hierarchy memory by using a buffering area of a comparatively small high-speed memory to attain the buffering of the high-speed data of large quantity. CONSTITUTION:In case a sequential access request indicates the writing to a low-speed memory 4, a buffering control part 1 feeds an address and a write signal to a directory 2. In this case, the write data is written directly to the memory 4 with no intervention of a high-speed memory 3. The directory 2 decides an address to receive an access within the memory 3 from the input address and read/write signal. The memory 3 or 4 received an access transmits and receives the data to outside via a high-speed memory cycle allocating part 6. Thus the buffering is attained to an sequential access.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides a method for buffering sequentially input data from a high-speed storage device (hereinafter simply referred to as high-speed storage) and a low-speed storage device (hereinafter simply referred to as low-speed storage). Hierarchical storage control method for efficiently buffering a large amount of data using a hierarchical storage device (hereinafter simply referred to as hierarchical storage) consisting of % formula % Conventional technology and problems Conventionally, when buffering sequentially input data , buffer storage did not have a hierarchical structure, and buffering of large amounts of high-speed data required a large amount of high-speed storage. In addition, when a storage system consisting of a cache and main memory used in a computer is used for buffering as described above, and data is processed by a processor as it arrives I1m, the cache's unnecessary block eviction algorithm has several unnecessary problems. LRU (L
East Racently' [Jsed] method is common, so by the time you want to process the necessary data in the cache, it may have already been transferred to the main memory, and the recent buffering method takes time before a processing request occurs. Only the data that has been updated will exist in the cache, which has the disadvantage of significantly reducing processing performance.

OBJECT OF THE INVENTION The present invention attempts to solve the problems of the prior art, and its purpose is to provide a buffering area for relatively small high-speed storage in a method for buffering sequentially input data. By preparing a system, it is possible to buffer a large amount of high-speed data, and it can also coexist with the cache and main memory system in a normal computer system.
Therefore, it is an object of the present invention to provide a system that can perform data buffering in random access and data buffering in sequential access using the same hierarchical storage.

Structure of the Invention The hierarchical storage control method of the present invention uses a hierarchical storage consisting of high-speed storage and low-speed storage, and also includes a group of management registers that manage the empty status and usage order of buffer areas in each storage within the hierarchical storage. ′, and is configured to execute data transfer from high-speed storage to low-speed storage and from low-speed storage to high-speed storage in the order in which data is buffered.

Embodiment of the Invention FIG. 1 is a basic configuration diagram of an embodiment of the invention, in which 1 is a buffering control section, 2 is a directory, 3 is a high-speed storage,
4 is a low speed register, 5 is a block transfer control section, 6 is a high speed storage cycle allocation section, and 7 is a processor.

This embodiment realizes the functions aimed at by the present invention by being embedded in the configuration of a storage system consisting of a cache and main memory in a normal computer system; however, when configured independently, Directory 2, high-speed storage cycle allocation section 6. It can be easily realized without the processor 7.

A high-speed storage cycle allocating unit 6 allocates a high-speed storage access cycle to a sequential access request from the outside according to a priority determination with respect to an access request from the processor 7. After that, the sequential access request is input to the buffering control unit l, which determines the buffer address, determines whether the address is in the buffer area in the high-speed memory or in the low-speed memory, and then accesses the read or write signal. Add directory 2 according to the request content
is input. Regarding the access request of the processor, after an access cycle is allocated by the high-speed storage cycle allocation unit 6, the access request is directly input to the directory 2.

In this embodiment, when the sequential access request is for writing to a buffer area in low-speed memory, the buffering control unit l inputs an address and a write signal to the directory 2, and also inputs an address and a write signal to the directory 2. In order to prohibit block transfer from the low-speed storage 4 to the high-speed storage 3, a block transfer prohibition signal is sent to the block transfer control unit 5-. Furthermore, in this case, the write data is written directly to a buffer (41 in FIG. 4, which will be described later) connected to the data bus, without passing through the high-speed memory 3, and later written to the low-speed memory 4. The functions of the block transfer control section 5 may be the same as those used in a normal computer system, except for the function of interpreting the above-mentioned prohibition signal.

In response to a sequential access request, the directory 2 determines the address to be accessed in the high speed memory from the input address and read/write signal, and accesses the address.

If the address does not exist in the high-speed memory, the low-speed memory is accessed. When the buffering control unit 1 detects that the buffer area in the high-speed memory becomes empty, the operation is started independently of external sequential access requests and access requests from the processor. ). The accessed high-speed or low-speed memory transmits and receives data to and from the outside via the high-speed memory cycle allocation unit 6, and buffering for sequential access is realized. Note that accesses from the processor 7 are input to the directory 2 via the high-speed storage cycle allocation section 6 and processed using known procedures implemented in general computer systems. The high-speed storage cycle allocation unit 6 includes a priority determination circuit, a switching selection circuit,
It can be easily configured using general hardware technology using register circuits and register circuits.

Fig. 2 shows a schematic diagram of the buffering control unit 1, where 11 is a high-speed memory address management module (AM-1) that manages the buffering area in the high-speed memory.
, 12 is a low-speed memory address management module (AM-2) that manages the buffering area in low-speed memory, and 13 is a low-speed memory address management module (AM-2) that manages the buffering area in low-speed memory; 13 indicates whether the input sequential access request requests buffering of external input data; 14 is a buffer address generation and request decoding unit (1-INT) that determines whether the request is to be sent to the AM-1, AM-1, and determines the buffer address to be used in the case of buffering human data; A management control unit (MNG) which knows the status of AM-1 and AM-2 and determines the operation mode of the entire buffering control unit 1;
M-2, I-INT, an address selection and R/W command generation section (0- INT)
It is.

FIG. 3 is a diagram showing a method of address management in AM-1 and AM-2. 111 is a register array consisting of N entries that accommodates buffer addresses of high-speed memory 3; 1lla is a register array 111 that accommodates addresses of high-speed memory 3 to be read at the next read access;
The entry 1llb is an entry in the register array 111 that accommodates the address of the high-speed memory 3 to be written at the next write access, 112 is a pointer (TP-1) that holds the entry number of the entry 111a, and 113 is the entry 1llb. A pointer holding the entry number of (
BP-1), 114 is a counter (BP-1) that stores the number of entries holding valid data in the register array 111.
CNT-1), 121 is a register array consisting of M entries accommodating buffer addresses of low-speed memory 4;
121a is an entry in the register array 121 that accommodates the address of the low-speed memory 4 to be read during the next read access, and 121b is an entry in the register array 12 that accommodates the address of the low-speed memory 4 to be written during the next write access.
1, 122 is a pointer (TR-2) that holds the entry number of entry 121a, and 123 is a pointer (BP-2) that holds the entry number of entry 121'b.
-2), 124 is a counter (CNT
-2). Register arrays 111 and 12 in FIG.
The diagonally shaded entries in 1 are entries containing valid address data, and data is added and deleted in ascending order of entry numbers. However, as shown in the register array 121, the accessed entry strange rock is
When the final entry in the register array is reached, the next access is in a cyclic manner, returning to the first entry. CNT-1 is the number of hatched entries in the register array 111, and CNT"2 is the number of entries in the register array 12
TP-1, BP-1, 1''P by accessing the high-speed storage 3 or the low-speed storage 4, respectively.
-2, the contents change according to changes in BP-2.

FIG. 4 shows an embodiment of the buffering control unit 1, in which sb and 131 are buffer address registers that provide the buffer address to be used when an input buffer request is made. , has the ability to add a certain value to sequentially input data so that consecutive buffer addresses can be given one after another, and the initial value setting and value change are performed by instructions from the processor 7.

Reference numeral 132 denotes a request decoder that determines whether read access or write access should be performed according to the access request. 141 is the counter indicated by 114 (GNT-1)
The comparator 142 compares the data of 124 with the total number N of entries in the register array 111, the sequential access request signal from the high-speed storage cycle allocation unit 6, and 124.
The buffering data transfer control unit (BTCTL) determines the overall operation mode of the buffering transfer control unit 1 based on the data of the counter (CNT-2) indicated by .
142 is the contents of the counter 114 (CNT-1) and the numerical value N
143 is a counter (C
A comparator that compares the contents of NT-2) with the numerical value M, 151 is a selection circuit for an access address to be sent to the directory 2, and 152 is an access command generator that sends a read or write command to the directory 2 based on a signal from the BTCTL 141. I'm at the club.

In addition, TP-1, BP-1, CNT-1, TP-2, B
Resetting and initial value setting of P-2 and CNT-2 are performed according to instructions from the processor 7. A buffer 41 temporarily buffers data to be written to the low-speed memory 4.

FIG. 5 schematically shows the operation in this embodiment. In FIG. 5, a high-speed memory cycle allocation unit 6 determines whether or not a high-speed memory access address can be allocated to a sequential access request from the outside, according to a priority judgment with respect to an access request from a processor 7. If 10% of high-speed memory access cycles are allocated to sequential access requests,
The operation in this embodiment is roughly divided into the following four modes.

Note that when a high-speed memory access cycle is assigned to an access request from the processor 7, the operation in this embodiment is similar to that of the cache and main memory in a normal computer system.

■) Input data buffering operation (MODEI) ■) Data sending operation (MODEI[) ■) Input data buffering operation using low-speed storage when a high-speed storage buffer overflow occurs (MODEnl) IV) High-speed storage buffer after the MODE river occurs Transfer of buffering data from low-speed storage to high-speed storage at the time of area creation (MODE IV) The BTCTL 141 determines which mode of the above (1) to (4) to be activated based on the following conditions.

i) S*INRQ*((N-(CNT-1))>0)
If MODE1 ii) S*0UTRQ then MODEnl iii) S*INRQ*((N-(CNT-1))
=0 ) * ((M-(ONT-2))>0 ) then M
ODEl[iv) V*((N-(CNT-1))>O
)*((CNT-2)>O) then MODEIV. Furthermore, S*INRQ*((N-(CNT-1))=0
)*((M-(CNT-2))=0), then the busy signal is sent to the processor 7 and the high-speed storage cycle allocation unit 6.
Send to.

However, S: The current storage access cycle is assigned to a sequential access request.

■: The current memory access cycle is idle (no access is assigned).

INRQ: Data reception request.

0UTRQ: Data transmission request.

(CNT-1): The contents of the counter CNT-1 at 114 (CNT-2): The contents S, V, INRQ, 0UTRQ of the counter CNT-2 at 124 are input from the high-speed storage cycle interrupting unit 6 to the BTCTL 141. It's a signal.

Further, in FIG. 5, (TP-1): The contents of the pointer 112 indicate the entry number of register array=111.

(BP-1): The content of the pointer 113 indicates the entry number of the register array 111.

(TP-2): The contents of the pointer 122 indicate the entry number of the register array 121.

(BP-2): The content of the pointer 123 indicates the entry number of the register array 121.

((TP-1)): TP-1 of register array 111
This is the content of the entry with the number indicated by and indicates the address of the high-speed memory 3.

((BP-1)): This is the content of the entry numbered BP-1 in the register array 111 and indicates the address of the high-speed memory 3.

((TP-2)): This is the content of the entry numbered TP-2 in the register array 121 and indicates the address of the low-speed storage 4.

((BP-2)): This is the content of the entry numbered BP-2 in the register array 121 and indicates the address of the low-speed memory 4.

Details of each mode will be explained below.

1) MODEL 1) The request decoder 132 outputs a write access signal and registers p7V-11 indicated by the contents of BP-1.
At the same time as writing the contents of the buffer address register 131 to the entry No. 1, the same contents are input to the selection circuit 151. The circuit selects and outputs the content 59 by turning on the BTCTL 141 cD instruction (* mark) signal.

ii) The access command generation unit 152 generates a write command based on the BTCTL 141.

1ii) Using the contents obtained in i)' as an address, access directory 2 with the command in 11).

Thereafter, the directory 2 determines that the access is an access to the low-speed storage 3, and accesses the storage.

1v) The contents of the buffer address register 131 and Bp-x are automatically updated by the nodeware in preparation for the next access.

It) MODEn i) The request decoder 132 outputs a Read access signal, reads the contents from the entry of the register array 111 specified by the contents of TP-1, and sends the contents to the selection circuit 15.
Enter 1. The circuit follows the instructions of BTCTL 141 (*
(Turn on the signal marked *) to select and output the content.

ii) Based on the BTCTL 141, the access instruction generation unit 152 generates a read instruction.

1ii) Using the content obtained in i) as an address, access directory 2 with the command in 11).

Thereafter, the directory 2 determines that the access is an access to the high-speed storage 3 and accesses the storage.

1v) The contents of TP-1 are automatically updated by the nodeware in preparation for the next access.

1) MODEil 1) The request decoder 132 receives a seven-inclusive access signal.
Output the number. On the other hand, since the comparator 142 notifies the BTCTL 141 that the content of CNT-1 and the number of work/tries N match, the signal marked with *** is turned ON.

, -1i) Since the signal marked *** turned ON, the contents of the 15 sofa address register 131 are written to the entry of the register array 121 specified by the contents of BP-2, and at the same time the same contents are selected. It is input to circuit 151. In this circuit, the signal marked with *** is ON, so the content is t-
Select and output.

1ii) The access command generation unit 152 generates an access command to the BTCTL 141.

iv) Using the Mk address obtained in ii), access directory 2 with the command ①).

Thereafter, the directory 2 determines that the access is an access to the low-speed storage 4 due to the occurrence of a miss, and accesses the storage.

(2) After accessing the low-speed storage 4 in step iv), the directory 2 issues an instruction to the block transfer control unit 5 to transfer the contents to the high-speed storage 3 (this is a general control in a normal computer system).

vi) Signal power O marked with *** for BTCTL 141
N,! : However, in the block transfer control unit 5,
This signal is interpreted as a signal to ignore the instruction from directory 2 shown in V), and the transfer operation is not started. (This function temporarily stops functions that are inconvenient to the present invention in order to allow the present invention to coexist with a general control mechanism in a normal computer system.) vii) Buffer address register 131 and BP
The contents of -2 are automatically updated by hardware in preparation for the next access.

IV) MODEN i) The BTCTL 141 determines that the current memory access cycle is idle, (N-(CNT-1))>o, and that there is an empty entry in the register array 111.
CNT-2) > 0, and it is detected that there is an entry containing valid data in the register array 121.
Turn on the signal marked with the mark.

ii) When the signal marked *** is turned ON, the contents are read from the entry of the register array 121 specified by the contents of TP-2 and input to the selection circuit 151, and the contents are transferred to the BP-2. Write to the entry in register array 111 indicated by the content of 1. Selection circuit 15
1, the signal marked *** is ON, so the content is selected and output.

ii) BCTL 141 access command generation unit 1
52 generates a read command.

1. Using the contents obtained in 11) as an address, access directory 2 with the command 1ii).

The rear directory 2 determines that the access is an access to the low-speed storage 4 and accesses the storage.

(2) After accessing the low-speed storage in step iv), the directory 2 issues an instruction to the block transfer control unit 5 to transfer the contents to the high-speed storage 3. (This is general control in a normal computer system.) Vi) BP-1, CNT-1, TP-2, CNT-2
The contents are automatically updated by hardware in preparation for the next access.

In order to realize the data buffering mechanism described above by incorporating it into the configuration of a storage system consisting of a cache and main memory in a normal computer system, the directory 2 is configured to coexist with, for example, a general LRU eviction algorithm. It is necessary to do so.

FIG. 6 shows an example of the structure of the directory 2 in this embodiment. This figure shows only the parts related to the implementation of the eviction algorithm, but the parts not shown in this figure may be configured in the same way as in a normal computer system. In this embodiment, the mapping method between high-speed storage and low-speed storage is based on the set-anonymous method, but even if other methods are used, the functions of the present invention can be easily realized from this embodiment. You can get the configuration. 21 is L that holds information for realizing the LRU algorithm.
RU table (LRUT), 22 is a sequential buffer display flag array (SQBFA) that accommodates flags for displaying blocks used as sequential buffers during high-speed storage, 23 is LRUT 21
LRU conversion/determination circuit (LRUCD) that determines unnecessary blocks based on the information of 5QBFA 22 and 5QBFA 22, and 24 are address arrays (AA) '1 241 and 31 that hold addresses of blocks stored in the high-speed storage section. are input block selection circuits 242 and 3 that select blocks containing data based on information from the LRUCD 23;
Reference numeral 2 denotes an output block selection circuit that selects a block containing data to be output based on information from the LRUCD 23.

5QBFA22 and AA24 are the same 4 rows n as high-speed memory 3
The LRUT 21 has a structure of 6 rows and n columns. 5QBFA22, AA24 X row Y
The block located in the column is a sequential buffer display flag for the block in the X row and Y column of the high-speed storage 3.

6, 5, and 6, which respectively contain address information.
A block of the QBFA 22 stores "1" when the corresponding block of the high-speed memory 3 is used as a sequential buffer, and "0" otherwise.

LRUT 21 is a certain column of high-speed memory A and B.

6 pits in the corresponding column for 4 blocks C and D)
(AB, AC, AD, BC, BD, CD) holds information that can determine the eviction block.

Figure 7 shows AB, AC, AD, BC, B of LRUT 21.
FIG. 4 is a conceptual diagram of a method of determining an expelled block using 6 bits of D and CD, and a method of not selecting a block used as a sequential buffer as an expelled block. FIG. 7(a) is a graph in which four blocks A, B, C, and D are combined with lines that are directly connected to each other. Lines with each direction are AB and AC
, AD, BC, BD, and CD. For AB lines, when the arrow is pointing from block A to B, it is 1#, and when it is not, it is 0". For other lines, from the left character block to the right. t1 when the arrow is pointing to the block of characters.
u, otherwise set @0#. Therefore, AB, AC,
A, B, C by 6 bits of AD, BC, BD, and CD.
, D, and a graph in which the direction of the line connecting them changes can be displayed. In such a graph, when a certain block is accessed, if the arrow of the line connected to that block is changed to point from that block to another block, LRU
According to the algorithm, the block selected as the evicted block is one in which all the arrows of the connected lines are pointing towards the block itself. In FIG. 7(a), block D is selected as the evicted block.

Figure 7(b), ((ri), (d) shows a method to prevent blocks A and C from being selected as evicted blocks when blocks A and C are used as sequential buffer blocks. Figure 7(b)
In step (C), block A' is selected as the evicted block, but block A' is accessed for modification at step (C), and block C is selected as the evicted block at this stage. Block C is accessed for modification and block D is eventually selected as the evicted block.

FIG. 8 shows the LR for realizing the method shown in FIG.
This is an example of the configuration of the UCD 23. 231-236 are LRUT
Flip-flops latching 6 bits of data in a certain column of 21; 2310-2360 flip-flops latching modified contents of 231-236; 2371-2360;
2374 is a flip-flop that latches 4 bits of data in the corresponding column of 5QBFA 22, 2375 to 2378
The clock from the 1d timing generation circuit is 2371~2
AN to block/non-block according to the contents of 374
These signals are input to the S and R terminals of the flips 231 to 236 using the D gates, giving the effect of executing a modified access of the corresponding block.

2391 to 2394 are AND gates for selecting blocks to be evicted by LRU according to FIG. 7(a). 238
is φ0°φ1. φ2. φ3. φ4. This is a timing generation circuit that sequentially generates φ5, and φ1 to φ4 are pulses used for modifying access.

Referring to FIG. 8, the operation when the data in the first column of FIG. 6 is input will be described. The operations proceed in order from (1) to (vii) below.

(1) By clock φ0 (AB, AC, AD, BC,
BD, CD)=(o, o, o, t, i, o) are latched in registers 231-236. At the same time (A,
B, C, D) = (1° o, i, o) is the register 2371
~2374 is latched.

(ji) Since the clock φl is output from the timing generation circuit 238 and the output of the register 2371 is 1, the gate 2375 is not turned on, and the registers 231 and 232
.

233 is set to 1 (AB, AC, AD, BC,
BD, CD) = (i, t, i, t, i, o).

(m) Clock φ2 is output from the timing generation circuit 238, but since the output of the register 2372 is 0,
Game) 2376 remains OFF.

(1v) Since the clock φ8 is output from the timing generation circuit 238 and the output of the register 2373 is 1, the game
) 2377 turns on, registers 232 and 234
is reset and register 236 is set (AB, AC
.

AD, BC, BD, CD) = (1,0,1,0,1
,1).

(V) Clock φ4 is output from the timing generation circuit 238, but since the output of the register 2374 is 0,
Gate 2378 remains OFF.

(vl) Clock φ5 is output from timing generation circuit 238, and the final results of registers 231-236 are stored in registers 231O-2360.

(Vii) (AB, AC, AD, BC, BD, CD)
= (1,0,1,0,1゜l), so it is game)
Among gates 2391 to 2394, only gate 2392 is turned on, and block D is selected as the evicted block.

The operations (i) to (vii) above are shown in FIG. 7(b).
+ (c) −+ (d) Same as tv operation.

In performing the operations shown in FIG. 7(b), ((ri) and (d), it is assumed that all four blocks are not used as sequential buffers, and to realize this assumption, The buffer area to be managed by the register array 111 in the AM-1 is one or less of the capacity of the high-speed memory (the structure of the high-speed memory is 4 blocks per row, so at least one block must be left unused for the sequential buffer). For this reason, the capacity must be less than m-v'm for one row and n blocks, and it is better to make it even smaller to prevent performance degradation due to program mishits.On the other hand, AM-2 Since the size of the register array 121 can be made sufficiently large, the sequential buffer of the entire system can also be made sufficiently large.

In this embodiment, the module AM-1゜n indicated by 11
The module AM-2 indicated by 111, 121, pointers 112, 113, 122, 12
3. Although the counters 114, 124, etc. are provided to achieve the intended functions, they may be replaced by an associative memory having a function of detecting emptiness and occupancy of all entries.

In the embodiment described above, sequentially input data is buffered using the buffer area in the high-speed memory 3, and after the buffer area is full, the buffer area in the low-speed memory 4 is used to buffer the sequentially input data. After execution, when the high-speed memory buffer area becomes empty, the data in the low-speed memory buffer area is transferred to the high-speed memory buffer area, as shown in Figure 9 (A).
The situation is shown in (a). Here, 31 is a high-speed memory buffer area, and 42 is a low-speed memory buffer area.

In Figure 9, the buffer address of input data is initially managed and recorded in AM-1 (()), and after the register array 111 in the AMI (see Figures 3 and 4) is full, the buffer address of the input data is managed and recorded in AM-1. -2 is managed and recorded (Q). After that, when register array 111 becomes empty, the address stored in AM-2 is transferred to notification-1 (6)). After that, it is output from AM-1 (0'). Figure 9(a) is the 9th
In the operation shown in Figure (6), AM-1 is moved to the buffer area 31.
, AM-2't- (replaces the buffer area 42 and performs exactly the same operation on input data), and shows the basic operation of the embodiments described so far.

Here, after the buffer area 31 of the high-speed memory 3 becomes full, buffering is immediately performed in the buffer area 42 in the low-speed memory (buffering is continued in a new buffer area 32 provided in the high-speed memory 3). (Q in Figure 9 (13) (b)).

()), transfers data from the same buffer area to the low-speed memory buffer area 42, and r4J3. Q), When the buffer area 31 is empty, transfer the data in the buffer area 31 from the buffer controller and rear 42 ((3p',
()) can also be considered. The basic operation of this embodiment is shown in FIG. 9 φb). Figure 9 CB) In (b), 32 is a newly created buffer area in the high-speed memory;
110 is the address management module 1'(AM-1') that manages and records addresses in the same area.
IJ number L). FIG. 10 shows the basic operation shown in FIG. 9 CB) (b) in more detail as a flowchart. A buffering control unit l that realizes this flowchart,
Directory 2. The configuration of the block transfer control unit 5 can be easily derived from the configuration shown in this specification using ordinary techniques.

As described in detail, the present invention uses a hierarchical storage structure consisting of high-speed storage and low-speed storage for buffering sequentially input data, and eliminates vacancies in the buffer area in the valley storage within the hierarchical storage. A management register group and a control unit are provided to manage the status and order of use, and transfer between high-speed storage and low-speed storage is performed in the order in which data is buffered, and has the following advantages and effects.

(1) Even when buffering a large amount of high-speed data, it is possible to prepare a relatively small buffering area for high-speed storage.

(2) It is possible to coexist with the cache and main memory systems in a normal computer system, and program processing and sequential data buffering can be performed in the same hierarchical memory.

(3) By (1) and (2), it is possible to provide a means to provide the cache of a normal computer system with an ink face of the inverting circuit, and to execute data processing from the line and program execution on the same hardware. .

(4) In (3), there is a degree of freedom in setting the buffering area, and it can also be changed dynamically depending on the usage situation, making it possible to effectively use the storage area and processing capacity. It can be drawn.

[Brief explanation of drawings]

FIG. 1 shows the basic configuration of an embodiment of the present invention, FIG. 2 shows a schematic configuration of a buffering control section, FIG. 3 shows an address management method, FIG. 4 shows an embodiment of the buffering control section, and FIG. Figure 4 shows the schematic operation of the embodiment, Figure 6 shows an example of the configuration of IJ, Figure 7 shows the method of determining the expelled block, and Figure 8 shows the L
An example of the configuration of the RU switching/determination circuit, FIG. FIG. 10 is a diagram showing the basic operation of the second length embodiment, and FIG. 10 is a diagram showing a schematic operation of the second embodiment. DESCRIPTION OF SYMBOLS 1... Buffering control part, 2... Directory, 3... High-speed storage, 4... Low-speed storage, 5... Block transfer control part, 6... High-speed storage cycle allocation part, 7
. . . Processor, 11 is a high-speed storage address management module (AM-1), 12 is a low-speed storage address management module (AM-2), 13 is a buffer “r address generation and request decoding unit (I INT)” ,1
4...Management control unit (MNG), 15...Address remote selection and R/W command instruction unit (INT). Patent Applicant Nippon Telegraph and Telephone Public Corporation Patent Attorney Hisashi Gobe Tamamushi (2 others) Figure 7 (α) (b) (c) AB: OAB: I AC: OAC: + AD: OAD: I BC: + BC・ 1 13D:I 13D:I CD:Q CD:'0 AB: 1 AC:I AD:1 13C:I BD: 1 QD:1 (d) AB;+ AC:O AD++ BC0 8D・I CD :1

Claims (2)

[Claims] (1) A hierarchical storage device consisting of a high-speed storage device and a low-speed storage device, and the above-described storage device that manages data commitment status in each buffer area of each storage device in the hierarchical storage device and holds information on buffering order. Buffering control means that includes a register group provided corresponding to each storage device, and a buffer transfer control means that detects whether or not each of the register groups is empty and performs transfer of buffered information within the hierarchical storage device. When the buffer allocated to sequentially input data in the high-speed storage device becomes full, the input data is buffered in the low-speed storage device in the hierarchical storage device, and the data is transferred to the buffer area of the high-speed storage device. An Is'J layer storage control method, characterized in that, when a free space occurs, the data buffered in the low-speed storage device is transferred to the free buffer area of the high-speed storage device in the order in which it was buffered to the low-speed storage device. (2) A hierarchical storage device consisting of a high-speed storage device and a low-speed storage device, and the valley that manages the writing status of data in each buffer area of each storage device in the hierarchical storage device and holds information on the buffering order. A buffering control means including a register group provided corresponding to a storage device, a buffer data transfer control means for detecting emptiness of each register group, and executing transfer of backed-up information within the hierarchical storage device; When securing a free area for random access, the eviction block determining means uses the LR1J algorithm to determine the data block to be evicted from the buffer area in the high-speed storage device, and when there is no free area for sequential access, the data block is transferred to the low-speed storage device. It is equipped with a data transfer means that performs buffering and transfers the oldest data to the high-speed storage device in the order in which it was buffered in the low-speed storage device when a free area later becomes available in the high-speed storage device. When the buffer becomes full, the data determined by the expulsion block determining means is ejected and the data is transferred to the high speed storage device, and at the time of sequential access, the data transfer means is used to transfer the data to the high speed storage device. A hierarchical storage control method featuring: