JPS60145A - Driving circuit of modulator - Google Patents

Abstract

PURPOSE:To keep an even spectrum of a PSK modulated wave and to ensure the stable operation of the PCM communication by inserting the normal signal of another line to the line which transmits the pulse signal when one of plural systems of pulse signals is cut off. CONSTITUTION:Terminals 4 and 5 are connected to input terminals D of waveform reproducing circuits F1 and F2 of a modulator driving circuit, and the 1st output terminal Q is connected to the 1st input terminal of a transmission logical circuit T LOG via gate circuits G3 and G4 respectively. At the same time, the 2nd output terminals Q' are connected to the 2nd input terminals of gate circuits G1 and G2 via monitor circuits DET-1 and DET-2 and then to the 2nd terminals of the circuits G3 and G4 via n-bit shifters S1 and S2. Furthermore the output terminals of the circuits G1 and G2 are connected to the 2nd input terminals of the circuits G3 and G4 respectively. Then the circuits F1 and F2, shifters S1 and S2 and the T LOG are connected to a terminal 6. When a series is cut off, the normal of another line is inserted. Thus the stable operation is possible for the PCM communication.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a modulator drive circuit, and particularly to a modulator drive circuit in which a carrier wave t=PsK (PhaseShiftKe) is used in a plurality of series of pulse signals.
'ing) This relates to a modulator drive circuit used for a modulator to modulate P8.

(b) Prior art and problems In recent years, digital wireless systems have been widely used that convert information such as voice, data, and images into pulses and send these pulse signals to the other station using wireless communication lines. 4
A digital modulation method such as a phase PSK modulation method is used.

FIG. 1 is a block diagram of a conventional modulator driver. In the same diagram, separate pulse trains applied to terminals 1 and 2 are generated by a free-lag flop circuit F1 using a clock signal applied from terminal 3. and F, the foreshadow is reproduced. Then, the regenerated two series of pulse and pulse signals are sent to the transmission logic circuit T@L
Each pulse is subjected to logic processing in the OG so as to show a relative phase, and then amplified to a predetermined level in a pulse amplification circuit PLS-DRV and applied to a modulator MOD to perform four-phase PSK modulation on the carrier wave.

On the other hand, monitoring circuits DET-1 and DET-2 constantly monitor whether each pulse sequence is normally received or reproduced. For example, when the pulse train applied to terminal 1 is disconnected, the output signal from this monitoring circuit DET-1 causes the light emitting diode DI to emit light, so you can visually see which series of pulse trains has been disconnected. be able to.

In order to extract this pulse train from such a 4-phase PSK modulated wave, first extract the carrier wave from the 4-phase PSK modulated wave using, for example, a baseband demodulator, and then combine this wave and the output wave of the voltage controlled oscillator with a PLL (Ph ~ase Lock L
It is necessary to phase-synchronize the voltage controlled oscillator with a (oop) circuit and extract a part of the output of the voltage controlled oscillator.

In this case, when random pulse trains are applied to both terminals 1 and 20, it is possible to receive a PSK modulated wave with a uniform spectrum distribution on both sides of the center frequency fo as shown in Fig. 2(a). can. The frequency fo of the carrier wave extracted from this received wave using the baseband demodulator is approximately at the center of the operating frequency range of the PLL circuit fm. Therefore, the PLL circuit can synchronize the oscillation frequency of the voltage controlled oscillator in phase with the frequency fo of the carrier wave approximately at the center of this operating range, and even if this frequency fo changes to some extent, the PLL circuit W1 can sufficiently follow it. It is.

However, in order to widen the cache charge range in the demodulator of the receiving section, PLL and automatic frequency fk control (A
FC) are used. Here, AFe
ij is a circuit that detects all frequency error components and makes the frequency of the reproduced carrier wave follow the input frequency. Therefore, the frequency of the reproduced carrier wave is controlled by outputting a frequency error component so that the energy distribution of the spectrum of the input modulated wave becomes symmetrical.

However, if the spectrum is asymmetrical as shown in FIG. 2(b), the frequency control voltage of the synchronization circuit will transmit erroneous information due to the uniformity of the spectrum, making it impossible to synchronize. Therefore, there was a problem that it became impossible to reproduce this pulse train.

(c) Purpose of the Invention The present invention was devised in view of the problems of the prior art described above, and the present invention is such that even if any pulse train is cut off, the P S K changes.
It is an object of the present invention to provide a modulator drive circuit that can maintain the uniformity of the A-wave spectrum.

(d) Structure of the Invention The object of the invention is to provide a waveform reproducing circuit for reproducing the waveform of inputted pulse signals of a plurality of series, a transmission logic circuit for logically processing the waveform-regenerated pulse signals, and a system for each of the plurality of series. In a modulator drive unit comprising a monitoring circuit that monitors the presence or absence of a pulse signal, an output from the υNoculus oscillator is provided between the waveform regeneration circuit and the transmission logic circuit to indicate the absence of the pulse signal from the monitoring circuit. This is achieved by providing a modulator drive circuit characterized in that a means for inserting the output of the pulse signal into the line where the pulse signal is disconnected is added to the modulator drive section.

(e) Examples of the invention FIG. 3 is a block diagram of one embodiment of the present invention.

In the figure, F and F2 are waveform reproducing circuits, DET-1, respectively.
and DET-2 are respectively monitoring circuits, S and S are n-bit shifters, Gl to G4 are gate circuits, T.LOG is a transmission logic circuit, MOD is a modulator, 4.
The terminals ri and 6Fi are shown respectively.

The various parts of JI and others are connected in a linear manner.

The input terminals of waveform reproducing circuits F and F2 are terminal 4, respectively.
and 5, the first output terminal is sent to the first and second input terminals of the gate circuit G and G4' (il-), respectively, and the second output terminal is sent to the first and second input terminals of the logic circuit respectively to the second input terminals of the gate circuits G and G2 via the monitoring circuits DET-1 and DET-:In, and to the first input terminals of the gate circuits G and G1 via the n-bit shifters S and Sl, respectively. Furthermore, the output terminals of the gate circuits G and G2 are connected to the second terminals of the gate circuits Gs and G4, respectively.
The person who is connected to the blade terminal. Also, terminal 6 is the waveform reproducing circuit F.
, and Fhn pit circuits SL and S2, respectively, and the output terminal of the transmission logic circuit T.LOG is connected to the modulated wave MOD via the Norms amplification circuit P@DRVi=.

In FIG. 3, the portion of the present invention is surrounded by a dotted line.

The operation of the modulator drive circuit connected in this way is as follows.

When a pulse train is applied to terminals 4 and 5, the terminal 4 pulse train is disconnected.When a pulse train is applied to terminal 5, even if one pulse train is disconnected, the gate circuits G3 and G4
The pulse train applied to the terminal 4 or the terminal 5 and the pulse train delayed by n pits in the opposite phase are taken out from the terminal (2) and applied to the modulator M0.1).

The reason why the n piton lids S1 and sxv were inserted in one embodiment of the present invention is as follows. That is, when the same pulse train is divided into two and sent to the modulator MOD via the transmission logic circuit T-LOG, there are only two combinations of the two pulse trains that can be applied to the modulator MOD: 00 or ull. Therefore, the phase state of the carrier wave for this is, for example, only O or π.

Generally, the phase state of a 4-phase PSK modulated wave is 0. π/2゜2π
Since the four phase states of /2 and 3π/2 appear randomly, the spectrum of the PSK modulated wave with is uniform, but as mentioned above, if the phase state is only O or π, it becomes an asymmetric spectrum with a strong correlation. (υ, the state is the same as when one pulse train is cut off as described above.

However, the combination of two pulse trains I'ioo, oi is applied to the modulator by passing through an n-bit shifter.

10. Since it can take the four states of 11, PSK
The spectrum of the f harmonic becomes a symmetrical spectrum.

Note that when a series of pulse signals is interrupted, instead of detecting it and using the pulse train sent through another line as described above, the pulse train from the pulse oscillator is
The same effect as above can be obtained by adding fil to the input terminal of a bit shifter.

(f) Detailed Description of the Invention [7] According to the present invention, when at least one series of pulse signals among the series of pulse signals is cut off, the line that was transmitting this pulse signal is By inserting a normal pulse signal 'f' on another line, the uniformity of the spectrum of the JPSK modulated wave is maintained and stable operation of PCM communication is achieved.

[Brief Description of the Drawings] Figure 1 is a block diagram of a conventional modulator drive section, and Figure 2 (a
＞ and (b) Spectrum distribution diagram of Fi4-phase PSK modulated wave. FIG. 3 is a diagram for explaining an embodiment of the present invention. In the figure, Fl and F2 are waveform reproducing circuits, DET-1, respectively.
and DET-2 are each a monitoring circuit, Sl and S2 are each an n-bit shifter, G and ~G4 are gate circuits, and T
11LOG is a transmission logic circuit, P/DRV is a pulse amplification circuit, MOD#-j modulator, 4. 5. 6 each indicate a terminal.

Claims (2)

[Claims] (1) A waveform reproducing circuit that regenerates the waveform of input multiple series of pulse signals, a transmission logic circuit that logically processes the waveform-regenerated pulse signal, and a monitoring circuit that monitors the presence or absence of a pulse signal of each of the multiple series. In a modulator drive unit consisting of, between the waveform reproducing circuit and the transmission logic circuit, an output from the monitoring circuit indicating that the pulse signal has been disconnected causes the output from the pulse oscillator to be output from the pulse oscillator when the pulse signal is disconnected. A modulator drive circuit characterized in that a means for inserting into a line is added to the modulator drive section VC. (2) The pulse generator comprises a circuit that branches a pulse signal from a series in which the pulse signal is not interrupted, and a circuit that shifts bits of the branched pulse signal by the branch circuit. The modulator drive circuit according to item 1.