JPS60142670A - Reduction system for half-tone picture - Google Patents

Abstract

PURPOSE:To obtain a reduced picture without spoiling the property of half-tones by outputting reduced picture element blocks after making a black/white decision by using a dither matrix generated by generating random numbers for every two- dimensional block. CONSTITUTION:A reduced block area dividing part 102 divides binary black/ white digitized picture information in a reduction objective rectangle in video memory 101 into reduction processing unit blocks. A reduction picture element point determining circuit part 103 calculates change point position information in a processing unit block after reduction simultaneously with the block division. Then, the picture element level at a change point is calculated by a calculating circuit part 104 for reduction picture element point picture element level and the two-dimensional picture element level matrix in this processing unit block is outputted. This output is supplied to a reduction picture element point dither processing circuit part 105, which makes a black/white decision by using the dither matrix as a threshold value to output the result as output picture information to reduced dither picture memory 106.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a halftone image reduction method, and more particularly to an image reduction method that can reduce the image while faithfully preserving black and white binary halftone characteristics.

[Background of the Invention] For example, when communicating between an A4 size facsimile and an 84 size facsimile, it is necessary to reduce the halftone image.

Conventionally, image reduction methods include a selection method (thinning method) that does not rely on calculations, and methods that use interpolation calculations include the OR method, which allows high-speed calculations, and the projection method, which causes less image deterioration. There is.

The selection method is to overlay the grid points of the converted image on the original image, select the pixel of the original image closest to the grid point, and adopt that pixel level as the pixel level of the converted pixel.
As a result, pixels are thinned out. in this way,
Since the density distribution of white and black pixels in the image is not taken into consideration, there is a drawback that transformation distortion is large.

Similar to the selection method, the logical sum method first overlaps the grid points of the converted image in the original image coordinate system, and then selects a black level if even one pixel level of the four pixels of the original image surrounding the grid point is black. This method sets the pixel level of the lattice points of the converted image to the black level, and because the calculation formula is simple, high-speed calculation can be expected, but it has the disadvantage of deterioration of image quality such as blurring. This was particularly noticeable when there were many points of change between black and white, such as in a halftone image.

Similar to the above two methods, the projection method is determined by first superimposing the reduced converted pixel points on the coordinate system of the original image. The pixel level of this converted pixel point can be determined by performing an interpolation calculation on the pixel levels of the surrounding pixel group of the original image, weighted by the distance to the converted pixel point. The converted pixel values determined in this way take continuous values,
This image is judged to be black and white at two density levels, black and white, and finally output as a binary image. This method of determining black and white is performed by simply comparing the levels of successive pixel level values of converted pixels obtained by interpolation calculations with a certain fixed threshold value.

For this reason, depending on the reduction ratio, in an input image with a large number of black-and-white transition points, the continuous pixel level values of converted pixels become unbalanced values, so that white dots in a group of black dots that produce halftones, Another problem is that black dots in a group of white dots are overemphasized or disappear, and the average density of the input image and the reduced output image changes. The disadvantage was that the tonality was lost.

[Purpose of the invention]

It is an object of the present invention to provide a halftone image reduction method that can improve such conventional drawbacks and reduce a black and white binary digital halftone image without losing its halftone properties. It is in.

[Summary of the invention]

In order to achieve the above object, the halftone image reduction method of the present invention uses reduced pixels having continuous density levels that are reduced and output in an image processing apparatus that performs reduction processing of a black and white binary digital halftone image. The focused pixel block of the point information group is compared using a dither matrix generated by generating random numbers or pseudo-random numbers in units of two-dimensional blocks, and the information of the focused pixel block is determined to be black or white and output. There is a characteristic in doing.

(Example of the invention) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram illustrating the present invention in detail.

In FIG. 1, 31 is a converted pixel group R(
k, ri is the converted pixel point after reduction, S (1° ,t)
It is.

The image reduction method of the present invention is a process of determining whether converted pixel information obtained by reducing image information of an input image is black or white.

Each value of the pixel point R (k,
The continuous pixel level values 32 are weighted by the distance to the reduced pixel point R(c) and subjected to interpolation calculations.

Next, the converted pixel (pixel of interest) R(k,
In order to determine whether the image is black or white, it is sliced using a certain threshold value and converted into an output pixel 0 (k, z) having either white or black density and output, as in the conventional method. In that case, in the present invention, the threshold for slicing is set to a two-dimensional threshold value (bump) generated by a random number or pseudo-random number generation circuit.
dither matrix), the pixel point of interest R(k,l)
By slicing in correspondence with the two-dimensional block of
) and output. That is, in FIG. 1, the converted pixel group R(k) of the reduced image 31 is converted from the pixel group S1, ,+) of the original image using the same method as the conventional method.

Here, a pixel level 32 of a halftone image of 4 cows is generated. In this halftone image 32, there are 4 cows
The pseudo-random numbers of the dither matrix (threshold button) 33 are compared as thresholds, and when pixel level≦threshold, it is judged as black, and when pixel level>threshold, it is judged as white, and a dithered image 34 of 4 pixels of the chair is generated. Output pixel 0 (k, ).

FIG. 2 is a schematic block diagram of the image reduction method of the present invention.

Of the black and white binary image information in the image memory 101, the area within the rectangle to be reduced is divided into blocks for each reduction processing unit (referred to as processing unit blocks) by the reduction block area division circuit section 102. Further, at the same time as the block formation, the reduced pixel point determination circuit section l○3 calculates the converted point position information after reduction within the processing unit block. Next, the pixel level of the conversion point within the processing unit block is calculated by the reduced pixel point pixel level calculation circuit section 104, a two-dimensional pixel level matrix within the processing unit block is output, and the reduced pixel point dither The processing circuit unit 105 uses the dither matrix as a threshold to determine black and white, and outputs a reduced dither image memo as output image information. It is output to J106.

Reduced block area division circuit section 102. Reduced pixel point determination circuit section 103. and reduced pixel point pixel level calculation circuit section 1
04 can utilize the conventional technology that executes the process of calculating the pixel level of the reduction conversion point.

FIG. 3 shows a more detailed block diagram of FIG. 2. In the dither section decision logic circuit 3, a high speed clock generator 50
Counter 5 counts up with the clock signal output from
1.52, the reduction output pixel points are calculated according to the reduction ratio given by the reduction ratio setter 1 and the processing target rectangle information of the original image given by the reduction target rectangle setter 2. MXN dots of pixel points on the original image corresponding to a 4×4 dot block are divided into blocks, and a dither section which is a processing unit block is calculated. The address of the segment in the image memory 4 and the size of the segment are given to the image memory. moreover,
The size of the dither section and the reduction rate are output to the reduced pixel point calculation circuit 6 and the weighting coefficient calculation circuit 5.

The clock signal of the counter 52, which provides the timing for determining the dither section, is further input to the dither matrix generation circuit 13, and a two-dimensional threshold value button corresponding to the dither section is created.

The reduced pixel point calculation circuit 6 calculates reduced pixel points R(1,l) to R(4,4) in the dither section 40 shown in FIG.
, and outputs it to the reduced pixel point coordinate memory 8 and the weighting coefficient calculation circuit 5.

The weighting coefficient calculation circuit 5 calculates pixel points S (i, j) to S (i++n) on the original image for each of the reduced pixel points R (1, 1) to R (4, 4) shown in FIG.

j+n) weighting coefficients are calculated and output to the weighting coefficient memory 7.

From the image memory, pixel information on the original image within the dither section 40 is stored in the horizontal line shift register 9 within each dither section 40 for each horizontal line (every j''-j+n lines). The pixel information on the image is synchronized with the clock signal of the counter 51 in the column S(1+j"j+n)
1. s, (t, +, 1t j-j+n), ..., S
In units of (i 10 m +, j,, x j + n),
From the horizontal line shift register 9 within each dither section 40,
The signal is input to the vertical dot reduction pixel level calculation logic circuit 10. The reduced pixel level calculation logic circuit 10 calculates the reduced pixel point coordinates necessary for calculating the pixel level of the reduced pixel points stored in the reduced pixel point coordinate memory 8 and the weighting coefficient memory 7 from the sequentially input pixel information on the original image. By referring to the weighting coefficient information, each column of reduced pixel points (R (1, 1-4)
, R(2,1~ri, I((3,1~4), R(4
, 1 to 4)) are calculated and created,
In synchronization with the clock signal from the clock generator 53, the pixel level of each column is sequentially added to the matrix adder (comparator) 1.
1.

Further, the clock signal from the clock generator 53 is also input to the dither matrix generation circuit 13, and the threshold string of the two-dimensional threshold pattern created at the time of generating the dither section 40 described above is synchronized with the ripple mark signal. Output.

The matrix adder (comparator) 11 compares the successive pixel levels of the reduced pixel points of each column that are input synchronously with each threshold of the threshold value column, and outputs a comparison result signal of each column. The black and white determination circuit 12 performs black and white determination and binarization, and the black and white level of each column is referred to the reduced pixel point coordinate memory 8 to determine the reduced pixel point address and output to the reduced dither image memory 14.

Thereafter, in the same manner, all blocks of the dither section 40 within the rectangle to be reduced are processed, and reduced pixels are output to the reduced dither image memory 14.

FIG. 5 is a schematic diagram of an image reduction processing method showing another embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation of FIG. 5.

FIG. 5 shows that depending on the black density within a reduced single block,
An example of switching and applying dither patterns is shown.

That is, in FIG. 5, the reduction rate given from the reduction rate register 16 and the reduction processing target area register 1
From the processing target area of the original image given from 7, the reduced block area division determination logic circuit 18 determines the reduced processing target area 31 and the reduced block area 35 in the original image 36 shown in FIG. , the dither section determination logic circuit 19 determines the dither section 40 shown in FIG. 6(b) from the reduced block area 35. ), the pixel level of the reduced pixel point 38 within one segment 37 of the original image 36 is calculated and output to the matrix adder (comparator) 21.

On the other hand, the reduced single block black pixel number counter 23 and the reduced single block pixel number counter 2 count the black pixel number A and the total pixel number B within the reduced pull pull area 35, respectively, and calculate them by A/B. Calculate the percentage of black pixels. The threshold pattern selector 25 selects a plurality of threshold patterns 26, 27, 2
8. From among 29, when A/B-0 to 1/16 - is pattern 26, and when A/B-1/16 to 2/16 -
selects pattern 27, pattern 28 for A/B-2/16 to 3/16, and pattern 29 for A/B-15/16 to 1 to correspond to the density in the book. It is output to the adder 21 as a threshold pattern 33.

In the adder 21, pixel level≦threshold or pixel level>
After determining one of the threshold values, the binarization circuit 22 determines that the former is black and the latter is white, and then output as a reduced dithered image 34.

〔Effect of the invention〕

As explained above, according to the present invention, when determining black and white after reducing a halftone image, a pseudo-analog sequence α1) of reduced pixel points of interest is calculated, and dithering processing is performed on the subsequent pixel levels. Since the image is binarized by applying , it has the effect of being able to reduce the image while faithfully retaining the properties of the intermediate tone.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a block diagram of an image reduction processing device showing an embodiment of the invention, Fig. 3 is a detailed block diagram of the processing device shown in Fig. 2, and Fig. 4 is an explanatory diagram of the dither section in FIG. 3, FIG. 5 is a block diagram of an image reduction processing device showing another embodiment of the present invention, and FIG.
It is an explanatory diagram of the operation of the figure. 4.101: Image memory, 1: Reduction ratio setting device, 2: Reduction target rectangle setting device, 3.19: Dither section determination logic circuit, 5: Weighting coefficient calculation circuit, 6: Reduction pixel point calculation circuit, 7
: Weight coefficient memory, 8: Reduced pixel point coordinate memory, 9: Horizontal line shift register within dither section, 10: Vertical dot reduced pixel level calculation logic circuit, 11: Matrix adder (comparator), 12: Black and white determination circuit, 13; Dither matrix generation circuit, 14. 106: Reduced dither image α2 memory, 50: High-speed clock generator, 51, 52: Counter, 53: Four-wheel generator, 18: Reduced block area division decision logic circuit, 23 : Black pixel number counter in a reduced single block, 24: Pixel number counter in a reduced single block, 2
5: # value pattern selector, 26 to 29: threshold slam.

Claims (1)

[Claims] 11) In an image processing device that performs reduction processing of a black-and-white binary digital halftone image, two-dimensional A halftone image reduction method characterized in that a dither matrix generated by generating random numbers or pseudo-random numbers is compared for each block, and information on the pixel block of interest is determined to be black or white and output.