JPS60142429A - Method and apparatus for executing input/output of virtual computer system - Google Patents

Abstract

PURPOSE:To reduce an I/O simulation overhead and to make a VMS highly efficient by constituting an I/O instruction executing circuit and an I/O interruption executing circuit by hardware and executing I/O under control by the hardware. CONSTITUTION:If an I/O channel of a virtual computer in running is occuplied and an I/O instruction is generated from the running virtual computer to the I/O channel in the virtual computer system for running one or plural operating systems by one computer, an AND circuit 2600 outputs ''1'' to a line 4200 to allow a selecting circuit 1900 to select a real channel number. In a high-speed VM mode, the channel number of the occupied I/O channel is converted from the virtual number to a real number by the hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a virtual computer system, and particularly to an I10 execution method and apparatus for a virtual computer system in which input/output is directly executed by hardware.

[Background of the Invention] In recent years, with the expansion of the field of application of Digital i-Based Computers, addressing methods (
(virtual memory method) is used, and furthermore, using the Kono method, 1
A method (virtual computer system) is used in which one real computer can be used by multiple operating systems (hereinafter referred to as O8) at the same time.

FIG. 1 is a conceptual diagram of a normal virtual computer system.

Central processing unit (hereinafter referred to as CPU) of a real computer system
100 real main storage device 200, real input/output channel device group 3
00, a real input/output device group 400 is shown. The real main storage device 2001.7 is a virtual machine system (hereinafter referred to as VMS).
There is a management program VMCP (also simply called CP) that controls the entire system, and this management program ■MC
Virtual computer VMI (
500-1), VM2 (500-2), VM3 (5
00-3) is realized (hereinafter, the virtual machine will be referred to as VM, and the control program will be referred to as VMCP and Net).

The number of VMs that can be implemented is limited by the amount of computer resources. As shown in Figure 1, each VM has virtual CPUs (500'-10, 500-20', 5
00-30), virtual main storage (500-11,500
-21,500-31), virtual input/output channel device group,
Virtual I/O devices exist. These virtual resources are realized by the simulation function of VMCP.

Since the O8 on the VM uses these resources as real resources, hereinafter these will be referred to as the VM's CPU.

VM main storage device, VM input/output channel device group, V
This is called the input/output device group of M.

FIG. 2 is a diagram showing a method of allocating the main memory of the VM shown in FIG. 1, that is, the virtual main memory in the real main memory 200.

Figure 2 shows the resident area (V=R, resident area 1. resident area 2)
, shows the dynamic paging area of VMCP. This paging area is used as a non-resident area (V=V).

The VM of VR is a V=FL area starting from address O, a resident area starting from main storage address α□ for main storage 500=11 of the first resident VM, and a permanent area starting from the main storage address α□ of the second resident VM. For the main storage device 500-21 of the VM, the resident areas starting from the main storage device address α are not occupied. Similarly, if the number of resident VMs increases, the resident area 3. The resident area 500-31 is the main memory of resident VM3, and the main memory of resident VM4 is f#t500-4.
It is defined as 1.

In the case of a general V=V (non-resident) VM, VMCP
will share the dynamic basing area of the V-V with other V-V VMs. Furthermore, as shown in FIG. 2, a VMCP prefix area (PSA) is secured at an appropriate location on the real main storage device 200 (hereinafter, the flex area will be referred to as PSA). Word rmm
The PSA stores the hardware status of the computer, and an example of the stored status is shown in FIG. 4(A).

The PSA 201 in FIG. 4(A) contains a command word CCW (Cb, annej Comma
Channel address word (CAW) 202 including the start address of the nd word, ) group, access key, etc.
, I10 old P S W (Program 5tatu
s Word ) 20:! ,,■10 New PSW204
It is included.

FIG. 4(B) is a diagram showing the contents of the PSW of FIG. 4 (Al).

Bit I in PSW 204 is an I10 mask, bit E is an external interrupt mask, bit W is a wait bit, and N and IA represent the next instruction to be executed. This P
Only one SW 204 exists in the CPU, and represents the state of the CPU.

Furthermore, a psw (virtual PSW) exists for each VM, which represents the state of each VM. Also,
The PSA of each VM is included in each M area shown in FIG. 2, and represents the hardware (generally virtual hardware) state of each VM. The PSA (virtual PSA) of each VM includes the same contents as shown in FIG. 4(A). The CAW within the virtual PSA is
Contains the start address and access key of the CCW group in the virtual main memory. Further, the PSW in the virtual PSA is a gold powder PSW that contains information specific to the VM.

The PSA of the VMCP shown in FIG. 2 displays the status of the computer system used in the VMCP, that is, the status of the computer system of the entire VMS.

Next, we will discuss the I10 request and the 11 request in the actual computer system.
The method for executing the 0 interrupt will be explained.

First, when there is a request for ■10, the main memory W20
0, f = I10 channel operation (Read/Wr
ite, etc.). That CCW
The data address contained within is a main memory address. Next, the start address of the CCW group is set to CAW, and a 5tart I10 instruction is issued. As a result, the I10 activation signal is issued to the target device. This device is addressed by the ■10 address CU, where C is the channel device number and U is the device address. The following Ilo request procedure is performed by a program called I10 supervisor, which is the core of O8 that controls the computer system.

Execution of the 110 interrupt is first started by issuing a 110 interrupt request from the I10 channel device to the CPU. The CPU side determines whether or not the current state allows an interrupt for this interrupt request, and if the interrupt is possible, initiates an interrupt operation. It is psw on the CPU side
is stored in the I10 old psw in the PSA, and the I10 new PS
This is done by loading W into the PSW. At this time, the I10 address CU of the interrupt request source is simultaneously stored in a specific part of the PSA. The above interrupt operations are directly implemented by hardware without intervention from O8.

Figure 3 (A) CB) shows I10 request and I10#, respectively.
It is a figure which shows the simulation operation in VMS including I.

The I10 request and I10'#lJ in vM are:
First, as shown in Figure 3 (A), O8 on VM600 is simulated as follows by VMCP.
creates a CCW group (referred to as a virtual CCW group) on its main memory, and sets its start address to the temporary #CA in the virtual PSA.
Set to W and issue the I10 instruction. The CCW group is
It is created from the address of the VM's main memory. If the resident area shown in FIG. 2 is provided as the VMO main memory, this address is a relative address within the resident area with O as the starting address. In addition, if the I10 channel device shown in FIG. 1 is given only the address of the virtual PSA that includes the start address of the CCW group (created in the resident area using the relative address within the CCW group F), It shall have the function to execute the solar system. In this case, the execution is
This means that the CCW of O8 in the resident area F is executed as is on the I10 channel without any change in the program.

In FIG. 3A, the I10 instruction issued by the OS on the VM 600 is trapped (branched) by the hardware 700, and control is further passed to the VMCP 800. V
The M CP 800 determines the start address of the virtual CCW group from the virtual CAW in the PSA of the VM (the address in the main storage device), and uses this as the CAW in the PSA of the VMCP.
, and issues an I10 instruction on behalf of the VM. By kneading, the I10 channel is the CAW in the PSA of the VMCP.
The virtual CCW of the VM is accessed and executed directly.

The I10 channel can also execute cc'w (real CCW) created with the address of the real main storage device 200.

Next, as shown in Figure 3(B), 110
When an interrupt occurs, it is trapped by the hardware 700 and the VMCP 800 is given control.

The VMCP 800 determines in which VM this 110 interrupt should be reflected, determines the possibility of an I/O interrupt for this V'M, and if the interrupt is possible, reflects the entire interrupt to that virtual PSA.

This is done by storing the VM's PSW (virtual PSW) in the I10 old psw of its virtual PSA and setting the I10 new PSW in the virtual f) SW. These pSW replacement processes are all performed by the VMCP 800 on the PSA of the VM.

In this way, in conventional VMS, ■10 instructions are always
Since the simulation is performed using the CP, there is a drawback that the CPU overhead is large and high performance cannot be expected.

[Object of the Invention] The object of the present invention is to improve the conventional drawbacks and to improve the VM
I10 of a virtual computer system that can reduce simulation overhead and improve performance
10 implementation methods and devices.

[Summary of the invention]

In order to achieve the above object, the virtual computer system of the present invention is a virtual computer system in which one or a number of operating systems are run under one actual machine, in which a virtual machine currently running is When the I10 channel is not occupied and an I10 instruction is issued from the currently running virtual machine to the I10 channel, the I10 instruction execution circuit executes the above ■10 instruction, and the I10 channel other than the above is
The feature is that when the I10 instruction is issued, the processing of the I10 instruction is entrusted to the virtual machine management program (VMCP).

[J side of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a diagram of an I10 instruction execution circuit showing an example of the present invention, and FIG. 9(], ) 12) is an operation flowchart of FIG.

As shown in FIG. 5, the f10 instruction execution circuit is configured by hardware.

A conventionally provided I10 instruction register 1000,
, I10\ row circuit 2300, 2400. PSW register 5200. In addition to the judgment circuit 5300 and the circuit including program v111 5400, there is a virtual channel mask register 1.
100, (/i, 1f41r exchange register 1200,
Breakfix registers 140Q, 1500 and selection circuit 1900 are newly provided.

When the I10 instruction is decoded, I
10 code, channel number C, and device address U are set to 000 (step of FIG. 91 (1)).

Figures 7(a), (b), (c), and (d) are, respectively,
Virtual channel mask register 1100. Virtual conversion 1/
Sister 120o, real channel mask register 610
0. 6 is a diagram showing the configuration of an actual conversion register 6200. FIG.

The numbers below each register in Figure 7 are o...n...
...31 is the virtual channel number (a) (b) or the real channel number (C) (d).

The virtual channel mask register 1100 is composed of 32 bits and indicates the state of the channel of the currently running VM in Table 71.
It's on. B) When the value in of n is O, it means that the current running VM occupies the real channel corresponding to virtual channel n. In addition, the virtual conversion register 1200
is dreaming of a real channel number C corresponding to the virtual channel n of the currently running VM, the l entry is 1 byte, and the total number is 3.
It has a length of 2 bytes. The virtual channel mask register 1100 and virtual conversion register 1200 are initialized when the currently running VM is activated by the VMCP.

Now, in FIG. 5, the virtual channel mask bit corresponding to the channel number C (referred to as virtual channel number) set in register 1000 is the virtual channel mask bit.
It is taken out from register 1100 and set in latch 1600 (step 2). Note that when the value 1 of the latch 1600 is °°0'', it indicates that the virtual channel Cv is not occupied by the currently running VM.Furthermore, the virtual channel mask register 1100 is set by the VMCP. .

Next, in the same manner, the real channel number Cr corresponding to the virtual channel number cv is taken out from the virtual conversion register 1200 and set in the register 1700' (step 3). Here, the virtual translation register 1200 is V
Set by MCP. Virtual channel number Cv1
When the real channel number Cr is sent to the selection circuit 1900,
The selection circuit 1900 selects either Cv or Cr and sends it to the register 21OO 710AND circuit 2600
Latch (H) 1300 is °′l” and latch 160
When 0 is uOT+, that is, in high-speed VM mode (latch t() 1300 is °'1"), the current running VM
Only when the channel is occupied (latch 1,600 pieces o''), °l'' is output to the line 42oo, and the selection circuit 1
900 to select real channel number C (step 4,
5.6). Note that in step 5, II II II is output only in the high-speed VM mode and when the channel is an occupied channel. Also, in step 6, Ilo, V of the shared channel
When Ilo of MCP, the output of game) 2600 is '0
''. In this case, C and r are used without conversion.

Hereinafter, operation H means that in the high-speed ■M mode, each time Ilo for an occupied channel is converted from virtual to actual channel number by hardware.

The selected channel number C and the device address U in the register 1000 are set in the register 2100 (step 7). The I10 address is input to the I10 normal processing circuit 2300 or the I10 exception processing circuit 2400 (step 8).

Based on the output of the determination circuit 5300, ■10 normal circuit 230
0 or I10 exception handling 2400. Alternatively, one of the program interrupt circuits 5400 is selected and activated (step 9).

FIG. 6 is a logic circuit diagram of the determination circuit of FIG. 5.

The CPU PSW is set in the register (PSW) 5200, and when the P bit is P-o, the CPU
is in a privileged state, and when P-1, the CPU is in an unprivileged state. Privileged instructions such as I10 instructions are executed when the CPU is in a privileged state.
In other words, it is controlled to be executable only at P-00. Therefore, when P=1, the line 5300-3 ni
t"l" is output, and the program interrupt circuit 5400 is activated (step 11). Note that p-1 is Prob/
It means am Mode, and in this case, the I10 instruction is treated as a privileged instruction exception.

Next, at P-00, when the value I of the latch 1300 is "0", that is, when it is not the high-speed VM mode, the signal "I II" is output to the signal line 2300-1 in order to start the I10 normal processing 2300. (Step 12).

The value H-Q of the latch 1300 is in the case of a general VM spanning the real computer mode, and in this case, "0" is output to the line 5100 and the prefix/register height 1500 is selected.

Next, in the high-speed VM mode, the value C of the PSA change request flag 2200 causes the signal line 5300-1
A signal II I 11 is issued to (step 13). At this time, ``]-pa is output on line 5100, the breffix register 1400 (for example, the prefix register of the current VM) is selected, and the effective breffix register 1400 is selected.
It is set in register 1800.

Next, when Co=1, there is a PSA change, so I1
0 exception handling 2400, the signal &-if
A signal "1'" is output to 5300-2 (step 14).

At this time, 0'' is output to @5100, and the prefix register 1500 (for example, the prefix register of VMCP) is selected.

Now, the contents of the effective prefix register 1800 are sent from the line 4300 to the I10 normal processing 2300 and the I10 example 1 processing 2400.
The corresponding processing is performed as the SA address. The contents of the effective prefix register 1800 are AND game) 20
Output of 00 5 Selected by the value of 00. That is,
High, 7VM mode 1300 value H is “1’” and P
Only when the value C6 of the SA change request flag 2200 is II OII, 1"' is output to the line 5100, and at that time,
The contents of prefix 1400 of the currently running VM are selected,
Set in effective brefix register 1800. At this time, as described above, when the CPU is in the right state, the determination circuit 5300 outputs an activation signal to the 10 normal circuit 2300 via the line 5300-1. I1
The 0 normal circuit 2300 sends the contents of the effective brake register 1800 sent from the line 4300 along with the activation signal to the I10 channel 2500 via the line δOo. In this case, the I10 channel 2500 stores the address of the specified PSA in the full register 2501. In the above case, the PSA of the current running VM is shown, so the virtual CCW is extracted from the CAW in the current running VM 17) PSA and executed sequentially. At this time, the content of the CAW and the data address of the virtual CCW are expressed as relative addresses within the resident area in FIG. 2. It is assumed that this (1) 10 channels 2500 are used for storage. In addition, the transfer of the leading address α and the transmission of α by the I10 channel
is stored using the same technology as before, so I10
It is shown as a register 2502 in the channel 2500, but the connections are omitted.

In the case of the real computer mode, the high-speed VM mode flag 1300 is 0'', and in this case, the contents of the prefix register 1500 are not selected, the I10 normal circuit 2300 is activated, and the conventional Processing in practical computer mode is guaranteed.

Below 1-. Second, for the processing of the I10 instruction, \l = r
It is possible to directly execute the 10 commands from the O8 of the VM and the VM of t. Also, the Ilo from the OS on the non-resident v Ni of V-V is high [\1M mode off, '1, i.e., latch], and the value I-1 of 300.
0"' and in privileged mode (i.e. PSW5200
Since the value of the I] bit is ]-), the VMCP
To 1.1! J1 is output and simulated by VMCP as before.

Next, in FIGS. 5 and 9 α), the virtual channel mask register 1600 is +111, that is, the current running V
In the case of Ilo for a channel that is not an occupied channel of M, activation signal 7 from determination circuit 5300; , 5300-
2, the I10 exception handling 2400 (section 1) is performed (step 21). At this time, in the 10 example 1 process 2400, the I10 address Cv U s is input from the register 2100.
The contents of the VN-CP brake register: +-800 are input from line 4300 (step 22). Set the above two values in the work register and break into the microprogram processing of I10 exception handling 24-00 (step 23). The microprogram in the I10 exception handler 2400 can also use the set inputs to interrupt the VMCP, and also not to lose control to a specific location in the VMCP. T@ru (step 24). V+\4 CP
ty) i (, 'a to'/rii, % To pass control to the place, ■MCI) 1.) i〉 with the microprogram
・It is necessary to keep track of tough 1-space information.

The above is the operation of (1) 10 instruction processing.

FIG. 6 is a diagram of an I10 interrupt execution circuit showing an embodiment of the present invention, and FIG. 10 is an operation flowchart of FIG. 6.

As shown in FIG. 6, the f/0 #II interrupt execution circuit of the present invention is similar to the conventional I10 interrupt circuit e.
3900. In the I10 interrupt register 6000, there is a new real channel mask register 6]OO1 real conversion register 6200. VM prefix register 1400
．． Effective prefix register 1δOO5 selection circuit 67
00, latch 1300, etc. are provided.

An interrupt request signal is sent from I10 channel 2500 to line 9oo.
o to the I10 interrupt circuit 6900 (first
Step 31) in Figure 0 α). This is the same as conventional operation. Next, the I10 address CO that is issuing the I10 interrupt request is sent to the register aooo via the line 8°00.
(step 32). Here, Cr is a real channel number and U is a real device number. This tl is also the same as the conventional operation.

FIG. 7 (
c) Explained by (d).

These registers 6100 and 6200 are not set by the VMCP when the current VM is started. The real channel mask register 6100 consists of 32 bits, and the number below the name bit indicates the real channel number. When the value of bit n is O, the real channel n
indicates that the current running V is occupied by 1. In addition, the real conversion register 6200 has an entry of 1 byte and 32 bytes, and the value C of the n-th byte indicates that the real channel n corresponds to the virtual channel C of the currently running VM.

Now, mask 1 corresponding to the real channel number Cr is taken out from the real channel mask register 6100 and set in the latch 6300 (step 33).

Here, when the mask is 1-0, it indicates that the real channel Cr is not occupied by the VM currently running. Next, in the same way as before, from the actual conversion register 6200,
Take out the virtual channel check @Cv corresponding to the real channel number Cr and set it in the register 6400 (step 3
4). In addition, as mentioned above, register 6'lO0, 62
The contents of 00 are set by VMCP.

The real channel number Cr and the virtual channel number Cv are sent to the selection circuit 6700, and the value of the input from the line 8300 becomes °゛1.
”, select Cv, and when “O”, select C (step 35). Output 830 of AND gate 7700
0 is the high-speed VM mode (value H-1 of latch 1300) and is an occupied channel of the currently running VM (latch 630
The channel number C5 selected by the selection circuit 6700 and the device address U of the register 6000 are stored in the register 680.
is set to 0 (step 36). The above operation means that in the high-speed VM mode, in the case of a Kakko-hide channel, the channel number is automatically converted from real to virtual by hardware.

The value of the register 6800 is input to the 10 interrupt circuit 6900. ■10 interrupt circuit 6900 has line 69007
The value of the prefix register that is more suitable than 1 is PSA
It has been input as an address (step 37).

The value of effective prefix register 1800 input to I10 interrupt circuit 6900 via line 6900-1 will be described below with reference to FIG. 10(4).

The value C0 of the PSA change request flag 6500 is O''' (1)
Only when the high-speed VM mode flag 1300 is ``1'' (meaning that the current running VM is in the high-speed VM mode), the output of the AND game 6600 is ``1°''. Next (step 73), the current running VM
The print/fix register 1400 of is selected (step 74) and its contents are stored in the effective fix register 800 (step 75).

In cases other than the above, the output of the AAND game) 6600 becomes '0' (steps 7], 72), the prefix register 1500 of the CP is selected, and its contents are stored in the effective prefix register 1800. be done.

The address of the selected effective prefix is sent to I10 interrupt circuit 6900 (step 76). In addition, VM
The value of the prefix register 1400 is set by VMCP when ①M starts up. Further, the value of the CP's brefix register 1500 is set during initialization of the VMCP and is normally not changed.

Now, returning to FIG. 10 (1), the I10 interrupt circuit 6900
performs interrupt processing using the ■10 address CU input from register 6δOO and the effective prefix address input from line 6900-1, but the processing is exactly the same as the conventional one (step 38). . M8900-
If the input from 1 is 1'', the interrupt will be reflected in the current running VM's brake fix, but if the current running VM cannot be interrupted, the interrupt processing microprogram of the I10 interrupt circuit 6900 will be reflected. No break-in occurs in I1
The interrupt request signal from channel 2500 is routed to line 9000.
This is a continuation of what was issued above, and the CPU side continues processing without generating any interrupt operations.

As before, the interrupt possibility of the currently running VM is determined by the current PSW.
is determined by the I10 mask of and the corresponding channel mask of control register CR2.

When in gate speed VM mode (value H-1 of latch 1300),
The current PSW is set to the PSW of the currently running VM.
In addition, the exclusive channel mask of the currently running VM is set in the corresponding part of the real control register CR2. The corresponding mask of the real control register CFL2 corresponding to the shared channel is always °゛1'' (interruptible), and the corresponding mask of the real control register CR2 for the exclusive channels of other VMs are all 60'' or exclusive It is possible to set the AND of the value of CR2 and the I10 mask of the PSW of the VM.The value of the current PSW and the actual control register CR2
The value of is set by the VM and CP when the VM is started.

In this way, the r10 interrupt circuit 690C)
Determine the mask, and if interrupts are possible, interrupt processing 9i jT4
Break into the microprogram (step 3)
9). The microprogram in the I, 10 interrupt circuit 6900 then reflects the given prefix hesi p1 in the conventional manner (step 40).

When the input from line 8900-1 is °゛O°', MM
When the input from the line 8900-1 is "]", the interrupt is reflected to the CP lexicus (step 4).

When reflecting the interrupt to MMCP, the current PSW52oO
%PSW to low) - after, Ii 9200, J: t
)C□ of latch 65oO, H of latch 1300
It is reset to + and the process is completed (step 42).

Now, if you want to reflect interrupts to VM, use the current PSW520.
0 is loaded with the new I10 PSW of the currently running VM, but after that, m9'200 resets the latch 6500 to °゛O''' (step 43).The high-speed VM mode latch 1300 remains at 1''. be. Current PSW 52
00 km After the new psw fails to set, if the high speed V tJ mode is l', then VMCP-ahll 7
600 interrupts may be triggered (step 4
4.4-5).

Current running ■After reflecting the interrupt to M's PSA, high-speed VM mode/
When the latch 1300 is "1", the following processing is further performed.

When bit W - of PSW 5200 is 1 (Wait), the output of OR circuit 7400 becomes "111" and "°l" is output to line 9700 (step 52).

In this case, P3'W52. Inside OO, there are VM ■10
A new PSW is set (step 51).

The latch 7000 has the I10 pending bit of the currently running VM set, and the latch 7100 has the external interrupt pending bit of the currently running VM set (step 5).
3.54). These two numbers +7000.7100 are set by VMCP when starting the vM. Lunch 70
00 is "l" means that the current running VM's I10 interrupt is pending, and the channel mask register CR of the current running VM is pending.
2 means that there is something that can be interrupted. Further, the fact that the launch 7100 is 1'' means that the 9I section interrupt of the current running VM is pending and that there is an interrupt possible with respect to the corresponding bit of the external interrupt submask CFtO of the current running VM.

Next, PSW 5200 external interrupt mask (E)
and the value of latch 7100 are both °1'', AN
The output of D gate 7300 is ]”, therefore OR
The output of the circuit 7400 becomes “°1” (step 55)
.

When the output of the OR circuit 7400 is ``1'' and the high-speed M mode latch 1300 is ``111'', the AND game)
The output of 7500 is I:+-I+, and VMCP-
chll interrupt circuit 7600 is activated (step 5
6.57). VMCP-cait? The circuit including JJ is
The contents of the VMCP's prefix register 1500 are selected and used as the prefix address (step 56). That is, the interrupt is reflected in the PSA of VMCP, and then the latch 6500 C□ and latch 13001 (
’” (step knobs 59 and 60).

Thereafter, control is transferred to VMCP, and VMC'P performs 1-restriction hold release processing (step 61).

As a result of the above processing, the I10 interrupt processing of O8 on the VM can be executed directly from the node 1-dware without intervention of the VMCP.

Note that in the embodiments shown in FIGS. 5 and 6, the mutual conversion function between the virtual channel number and the real channel number is shown implicitly, but in the operation of VM and S, it is assumed that the two are equal. If usage restrictions are placed, the conversion function becomes unnecessary.

Therefore, the virtual conversion register 1200% and the real conversion register 6200 are unnecessary, and the circuit is simplified.

[Effects of the Invention] As explained above, according to the present invention, the I10 instruction path and the I10 interrupt execution circuit are configured by hardware,
Since it is executed directly under the control of the software without the control of the VMCP, the 110 simulation overhead can be reduced, and MSIy) high performance can be achieved.

[Brief explanation of drawings]

Figure 1 shows an outline of a general virtual computer system (Si 1, 2
Figure 1 shows the method of allocating VMs in the main storage device, Figure 3 shows the I10 simulation in VMS, Figure 4 shows the configuration of the prefix (PSA), Figure 5
The figure is a block diagram of the I10 instruction path showing an embodiment of the present invention, FIG. 6 is a block diagram of the l10111-inclusive execution circuit, not showing the embodiment of the present invention, and FIG. 7 is the same as that of FIGS. A configuration diagram of the registers used, Figure 8 is a logical connection diagram of the judgment circuit in Figure 5,
FIG. 9 is a flowchart of the operation of FIG. 5, and FIG. 10 is a flowchart of the operation of FIG. 100: CPU, 200: Real main storage, 300
: Channel device, 4oo two-person output device, 500-1.5
00-2,500-3: Virtual machine (VM'), 100
0: I10 Instruction L/Sister, 1100: Virtual Channel Mask Register, 1200: Virtual Translation Register, 1300: High, JVM Mode Register, 1400:
Current running ■M brake fix register, 1500: V
MCP prefix register, 6100: real channel mask register, 6200: real conversion register,
5300: Judgment circuit, 6900: I10 interrupt circuit, 2
300: 110 normal execution processing circuit, 2400: I
10 execution exception handling circuit, 506-10, 500-20.
5oo-3o: Virtual CPU, i.e. VM CPU, 50
0-1.1,500-21.500-31: VM main storage (generally virtual main storage). Patent applicant: Hitachi 11i9 Manufacturing Co., Ltd.
Patent Attorney Masa Isomura＼・ ゝ、l-- Figure 7 1100 200 0 1 、、、、、、、n 、、、、、、、 312
00 012...n application...31 Fig. 8 1) SW5200 Fig. 9 (1) Fig. 9 (2) Fig. 10 Operation diagram including 1/II (1) ] O Fig. C) Small ]0 Figure (3) Figure 10 (4)

Claims (1)

[Claims] σ) In a virtual computer system in which one or more operating systems are run under one real computer, the I10 channel is not occupied by the currently running virtual computer, and When a 17'0 instruction is issued from the currently running virtual machine to the I10 channel, the I10 instruction execution circuit executes the above I10 instruction, and when an I10 instruction is issued to an I10 channel other than the above, the I10 instruction is processed. 1. A method for executing I10 in a virtual machine system, characterized in that the I10 execution method is entrusted to a virtual machine management program (VMCP). 12) In a virtual computer system that runs one or more operating systems on one real computer, the I10 channel is occupied by the currently running virtual computer, and a 110 interrupt occurs in the I10 channel. When the above I10 interrupt is possible for the virtual machine described in 2, the above I1 is stored in the interrupt information storage area of the virtual machine.
110 interrupts that occur in channels other than the occupied I10 channel are added to the VMCP prefix IIJ.
I10 of a virtual computer system characterized by including
Execution method. (3) A means for identifying whether the virtual machine is currently running, a means for indicating whether or not the I10 channel is occupied, A means for storing a prefix address, a means for storing a VMCP brefix address, a means for selecting one of the above two storage means, and an I10 instruction issued while the virtual machine is running. An I10 execution device for a virtual computer system, comprising: means for determining whether or not an issue has been issued to an I10 channel. (I4) The determining means determines whether the currently running virtual computer is r1.
It is determined whether or not the I10 channel to which the 0'M interrupt request was issued is occupied, and if the I10 channel is occupied, it is determined whether or not the virtual machine can perform the F I10 interrupt. I1 of the virtual computer system according to claim 5, characterized in that
0 execution device. (5) The means for determining the I10 instruction or ■101ii511 inclusion request stores an I10 channel address among the I10 addresses indicated by the virtual machine, or an I10 channel address in the real computer corresponding to the address, and stores both of the above. An I10 execution device for a virtual computer system according to claim 3 or 4'yi, characterized in that addresses are mutually converted. (6) When determining whether or not the 110 interrupt is possible,
Equipped with a means to indicate the existence of a 110 interrupt pending in the currently running virtual machine and the existence of an external interrupt pending, and after reflecting the 10 interrupt in the currently running virtual computer/- soul prefix, When an I/O interrupt is pending in a virtual machine inside and the computer becomes capable of 110 interrupts, or when an external 8 interrupt is pending and becomes capable of external interrupts, or when the computer is in a wait state. An I10 execution device for a virtual calculation-like system as set forth in claim FfJ4 (3), (4) or (5), which generates VMc p y-, va inclusion when .