JPS60139089A - Synchronous detection circuit - Google Patents

Abstract

PURPOSE:To prevent the variation of a killer level and to stabilize the working of a synchronous detection circuit in case the width of a burst gate pulse has variation, by adding a transistor to discriminates the level of the burst amplitude. CONSTITUTION:A signal Vi to be detected, i.e., a color burst signal Vi is multiplied by a carrier signal Vc synchronizing with the signal Vi by a multiplying circuit consisting of transistors TRQ31-Q36, a constant current source I01, etc. of to obtain the 1st and 2nd outputs of different polarities. Each of these outputs undergoes a level shift by a shift circuit consisting of TRQ37 and Q38 and constant current sources I32 and I33 and is applied to the 1st and 2nd differential circuits consisting of TRQ39-Q42 and constant current sources I34 and I35. A load circuit consisting of TRQ43 and Q44 as well as TRQ45 and Q46, etc. is connected to each differential circuit. Then a capacitor C31 is charged and discharged by a current flowing to the load circuit. The amplitude level of a burst signal is discriminated by the ON/OFF of TRQ39-Q42. Thus the variation of a killer level is prevented and the circuit working is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention is applicable to, for example, a color television receiver or a video Teso recorder.

[Technical background of the invention]

Figure 1 shows a synchronous detection circuit conventionally used as a color killer detection circuit in color television receivers and video Teso recorders. In the figure, transistor Qlt - Qlg + emitter resistance R11 + R1!
+ constant current source Ill constitutes a multiplication circuit composed of two balanced differential amplifier circuits 4#. The load circuit connected to the common connection point of the collectors of transistor Qt3+QCs is a current mirror circuit consisting of transistor Q17 +Q+8 +resistor R13*R14, and transistor Q1s'
+ One multiplication output flowing to the common connection point of the collectors of Qts flows into the hold capacitor C1l. The load circuit connected to the common connection point of the collector of transistor Q14 + Qts is transistor Ql* + Q10.
+ Current mirror circuit consisting of resistor RIll + RHB, transistor Qg+ + Q2z r resistor R17
* Consisting of two current mirror circuits, including a current mirror circuit consisting of R11+, transistor Q14 r
The other multiplication output flowing to the common connection point of the collectors of Qts is extracted from the capacitor C1l.

A color burst signal which is one of the signals to be multiplied (below μ, this is shown as a voltage signal vi: see Fig. 2 (a))
is supplied to the pace of the transistor Q++, and the pace 1ift of the transistor Qst is supplied to the pace of the transistor Q12 forming a differential pair therewith.

DC potential is supplied (or color burst signal v
1 and a signal 7I of opposite polarity is supplied).

A carrier signal synchronized with the color burst signal v1, which is the other signal to be multiplied (hereinafter referred to as a voltage signal vc), is supplied to the common connection point of the transistors Q1s + Qlg, and the transistors QI4 * Qt
At the common tangent 7 light point of the pace of s, there is a transistor Q + s +
The same DC potential as the common connection point of the pace of Qta is supplied (or a signal 7 having a polarity opposite to the carrier signal VC) is supplied.
c is supplied).

A second terminal for extracting the color burst signal vI from the terminal 11.
High-level perspective shown in Figure (b))
When G is applied, the constant current source 1111 switch SW of the multiplication circuit is turned on. Now, assuming that there is no color burst signal v1, the capacitor C from the transistor QCs
Since the current flowing into I+ and the current drawn from capacitor C1l by transistor Q2m are the same, no current flows through capacitor C11, and the hold voltage of capacitor C11 becomes equal to the bias voltage vl applied from power supply Vll through resistor R1l+. .

On the other hand, when the color burst signal Vi is present, the operation is as follows. First, the color? - strike signal v1
When is positive, the carrier signal v(, is also positive, so the transistor Q13tQxs is turned on, and when the amplitude of the color burst signal Wi is tossed to vB(0-peak lii), the capacitor -1 has; o % current. is poured in, and in the case of this capacitor C11, the carrier signal VC is also negative, so trans. Similarly, as the current flows into the capacitor C11, the current flowing into the capacitor Ctt also increases, and reaches a constant value at the maximum Ion (current value of constant current source III) as shown in FIG. 2(c) (Rls =
RI41RI! =R+s). However, in reality, the burst period T1 is smaller than the e-tooth width T2,
If the ratio is k (0 x k x 1), then capacitor C1l
The maximum average current flowing through is kI ot. Therefore, the hold voltage of capacitor C1l is also at maximum kIOl.
ai9 tonal. The hold voltage of the capacitor C11 is compared with the reference voltage v2 in the comparator circuit 12, and the presence or absence of a color signal is determined. Note that in the figure, vcc is a power supply.

[Problems with ambiguous technology]

However, in the case of the configuration in which the hold voltage is proportional to the burst amplitude VB as described above, when the burst f-pulse width T2 changes, the killer level for determining the presence or absence of a color signal changes. To explain this using Fig. 3, in the figure, the solid line indicates the case when = 1, and the dashed line indicates the case where the pulse width T2 becomes larger. This shows the case where As shown in the figure, as the burst pulse width T2 increases, the hold voltage around 1 (corresponding to k) becomes smaller and the killer level increases.

(Ll→L2). In this way, in the conventional circuit, the killer level varies depending on the burst gate pulse width T2 and f@, so it is not possible to always determine the presence or absence of a color signal using the same standard, and even though K is a color broadcast, it is reproduced in black and white. This resulted in problems such as being damaged.

[Purpose of the invention]

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide a synchronous detection circuit that can prevent fluctuations in the killer level even if the burst dart pulse width fluctuates. shall be.

[Summary of the invention]

This invention multiplies a limb detection signal and a carrier signal synchronized therewith, and generates a first signal with a different polarity. A multiplication circuit that obtains a one-trigram output, a first level shift circuit that level-shifts the first multiplication output, and a second level shift circuit that level-shifts the second multiplication output. , a first transistor that uses the first multiplication output as a pace input; and a second transistor that forms a differential pair with the first transistor and uses the output of the second level shift circuit as a pace input.
a tenth differential circuit having a transistor, and a third differential circuit having the second multiplication output as a pace input and whose collector is commonly connected to the collector of the second transistor.
and a fourth transistor forming a differential pair with the transistor and the third transistor, the collector of which is connected across the collector of the first transistor, and whose pace input is the output of the first level shift circuit. a second differential circuit comprising: a first constant current source connected to a common connection point of the emitters of the eleventh and second transistors and determining the operating current of these transistors; a second constant current source connected to a common connection point of the emitters of the fourth transistors and determining the operating current of these transistors;
The current flowing through the common connection point of the collectors of the transistors and the second transistor. The third transistor is configured to include a capacitor that is charged and discharged by a current flowing through a common connection point of the collector of the third transistor.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a circuit diagram showing the configuration of one embodiment.

In the figure, transistor Q3s = Qss *emitter resistor R31r R2H + constant current source ZS+ forms a multiplier circuit having a double-balanced differential amplifier circuit configuration. The differential inputs of the transistors Qss + Qas forming a differential pair are the color burst signal vl (see FIG. 5(a)), and the differential inputs of the transistors Qss + QssO are the carrier signal vc.

A load resistor R33 is connected to the common connection point of the collectors of the transistors Qss + Qas, and the transistor Qsa
e A load resistor R1 is installed at the common connection point of the collector of Qss.
4 is connected.

The common connection point of the collectors of the transistors Qss*Qas is connected to the base of the transistor Qst, the collector of this transistor Qst is connected to the power supply VCC, and the emitter is grounded through a resistor Rag and a constant current source I32 in this order. These resistor R3S and constant current source ist form a level shift circuit that level-shifts one multiplication output mI derived to the common connection point of the collector of transistor Q33 r Qss. A transistor Qsa from which the other multiplication output m2 having a different polarity from the multiplication output m1 is obtained.
Similarly, a level shift circuit consisting of a resistor R36 and a constant current source rss is connected to the common connection point of the collector of +Qss via a transistor Qss.

The other multiplication output m2 is applied to the pace of the transistor Q39, and a signal obtained by level-shifting one multiplication output ml is applied to the pace of the transistor Q40 from a common connection point between the resistor nss and the constant current source 1ast. Transistors Qa1r and Qaz also form a differential pair, and transistor Q41
One multiplication output m violet is applied to the pace of the transistor Q411, and a signal obtained by level-shifting the other multiplication output m2 is applied to the pace of the transistor Q411 from a common connection point between the resistor R3B and the constant current source 32. Transistor Qse + Q4
A constant current source I34 is connected to the common connection point between the emitters and the transistors Q41*Q4t(til
A constant current source It8 is also connected to I.

The collectors of the transistors Qss r Qat are commonly connected, and the transistors Q43゜Q44 are connected to this common connection point.
．． The input end of a current mirror circuit consisting of a resistor R37+13g is connected, and its output end is connected to a Hall capacitor C11.

The collectors of the transistors Q40 r and Q41 are commonly connected, and the transistor Qa11*Q4 is connected to this common connection point.
6. The input end of a current mirror circuit consisting of resistors R39+R46 is connected. The output end of this current mirror circuit is transistor Q4? *Q4ml resistance R
The input end of a current mirror circuit consisting of 41*R4* is connected, and the output end thereof is connected to a capacitor Cjl.

The capacitor C31 has a power supply v3. Yoshi switch SW...
.

Since a bias voltage v1 is applied through a resistor R(s), the hold voltage of this capacitor Cat is compared with a reference voltage V in a comparator circuit 31.

The constant current source "R4r I35 '+ switch 5w31 is a high level burst f-)no4 applied to the terminal 32.
It is turned on by the pulse Pa (see FIG. 5(b)).

The operation in the above configuration will be explained.

Consider the case where the constant current source I34 + I3B + switch 5W31 is on. Now, assuming that there is no color signal, the transistor Q37゜Qs
The emitter potentials of a are approximately equal to each other, and these become the pace potentials of transistors Q3**Q41, respectively. The pace potentials of transistors Q4G*Qat are each lower than the pace potential of transistors Qse + Q41 by LsRss l loIRIII. Therefore, transistor Qxe+Q4+ is turned on and transistor Q4or Qat is turned off.

This results in constant current ■. The number is passed through the transistor Qss and the collector of the transistor Q44 is connected to the capacitor Cf1.
It is poured into l. On the other hand, constant current I. 5//i The transistor Q41 is passed through and the collector of the transistor Q48 is drawn out from the capacitor Cat.

By the way, if to4'' IO8 and the current ratio of the three current mirror circuits mentioned above are all set to 1:1, no current will flow through the capacitor CSX and resistor R43, and the hold voltage will be equal to the bias voltage Vl. It has become.

When there is a color signal, if the color burst signal M1 is positive, the transistor Qss*Qss is turned on, and if the emitter burst signal VB of the transistors Qsa and Qat is negative, the transistor Qs4+Qis is turned on, and the transistor Qss and Q117ru. in this way,
Regardless of whether the color burst signal v1 is positive or negative,
If the transistor Qss is constructed, the emitter potential of the transistor Qss is higher than the potential obtained by rectifying the color burst signal v1 into a positive # signal. However, resistance R33 + R34
is set so that R33=R34. □Now, the amplitude VB of the color burst signal vI (0 - B (=■o
3R311) If it is smaller, the transistor Qs*
+Q41 is turned on and operates in the same way as when there is no color signal, and the comparison circuit 31 determines that there is no color signal.

■. Assuming it is larger than 2R36 (see Figure 5 cc))
, transistor Q39 with transistors Qss and Qao
The fact that Q turns on is the same as in the previous case, but the transistor Q
41 and Q42, transistor Q42 is now turned on. This results in constant current ■. 4+I. , is the transistor Q
se * led to the collector of transistor Q4s through Qaz, and from the collector of transistor Q44 as shown in FIG. 5(d). A current of 4+Io8 flows into capacitor C31.

Here, if the value of the resistor R4m is increased, the hold voltage with the burst amplitude VB of 102R16 will rise instantaneously, regardless of the magnitude of the burst pulse width T2, as shown in FIG. A determination is made as to whether the color signal is present or not.

In Fig. 6, the solid line shows the characteristics when 2 = 1, and the broken line shows the characteristics when 0〈k〈1, Tsumashi, Burst Dart No. and Luss: [T2 becomes large. show.

In such a configuration, the killer level vk (O-peak value) is given by the following equation and is not affected by the magnitude of the //str pulse width T2 (the magnitude of k). Then, by appropriately setting the resistance ``aa * I.t + Rst l Rsz + constant current I02, the killer level v
k can be set appropriately.

Note that if the color burst signal Vl and the carrier signal vc are always synchronized, the transistors Q39 and Q10 are unnecessary. However, in reality, for example in a weak electric field,
The color burst signal v1 contains a signal (such as noise) that is not synchronized with the carrier signal vc. In case B, the synchronized component charges the capacitor C31. Therefore, due to the inverted synchronous component, capacitor C3゛! In order to dissipate the charge and prevent it from flowing to the capacitor C3t on average, the transistor Qts
*Q411 is required.

Also, if a sufficient dynamic range can be obtained, the common collector of transistors Q40 + Q41 can be connected to a capacitor c.
, nt, and the two current mirror circuits consisting of the transistor Q*s=Q*a can be omitted.

As detailed above, in this embodiment, the resistor 1'tssR3
6. Constant current source■3! *The burst amplitude VB is identified at a binary level using the level shifter IIoz/R36 as a reference by the level shift circuit consisting of I33 and the transistors Q39 to Q41 forming a differential pair, and the current from the constant current source I34 r II8 is determined according to the identification result. Different charging and discharging modes are created when the burst amplitude V is large and small compared to the above level shift, and the capacitor C
11 is constant current■. , · I'O1 is used for charging and discharging.

In this way, the size of the burst width VB is determined by the transistor Q.
In a configuration in which 1 is identified by turning se to Q42 on and off, and the capacitor C31 is charged and discharged with a constant current 04' + I6g according to the identification result, regardless of the burst amplitude VB, the current is proportional to the burst amplitude VB as in the past. Compared to a configuration in which the capacitor is constantly charged and discharged with the current, the current is less affected by fluctuations in the dart pulse width T2, and the presence or absence of the color IH can be determined based on the killer level vk, which is always approximately constant.

Furthermore, it goes without saying that the present invention can also be applied to a color killer detection circuit.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a synchronous detection circuit that can prevent the killer level from changing even if the burst gate changes.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional synchronous detection circuit used as a color killer detection circuit, Figure 2 is a signal waveform diagram to explain the operation of Figure 1, and Figure 3 explains the shortcomings of Figure 1. FIG. 4 is a circuit diagram for explaining an embodiment of the synchronous detection circuit according to the present invention, FIG. 5 is a signal waveform diagram for explaining the operation of FIG. 4, and FIG. 6 is a characteristic diagram for explaining the operation of FIG. 4 is a characteristic diagram for explaining the operation of FIG. 4. FIG. Q! +-Q4g...Transistor, R3□~R4B・
・・ku resistance＼cst"'hold capacitor, yst~r
ss...constant current source, v31...voltage source, 31...
Comparison circuit.

Claims (1)

[Claims] Multiplying the test wave signal and a carrier signal synchronized with each other,
1st with different polarity. a multiplication circuit that obtains a second multiplication output; a first level shift circuit that rail-shifts the first multiplication output; a second level shift circuit that level-shifts the second multiplication output; a first transistor that uses the multiplication output of the second level shift circuit as a pace input; and a second transistor that forms a differential pair with the first transistor and uses the output of the second level shift circuit as a pace input.
a first differential circuit having a transistor, a third transistor having the second multiplication output as a pace input, a collector of which is commonly connected to a collector of the second transistor; a second differential circuit having a fourth transistor that is commonly connected to the collector of the transistor of the first transistor and uses the output of the first level shift circuit as a pace input; a first constant current source connected to a common connection point of the emitters of the second transistors and determining the operating current of these transistors; a second constant current source connected to a common connection point of the emitters of the fourth transistor and determining the operating current of these transistors; Fourth
The current flowing through the common connection point of the collectors of the transistors and the second transistor. A synchronous detection circuit equipped with a capacitor that is charged and discharged by a current flowing through a common connection point of the collectors of the third transistor.