JPS60136876A - Vector processor - Google Patents

Abstract

PURPOSE:To allow optional vector operation processing in which random number columns are used by using plural random number generators, and generating the optional random number columns in parallel. CONSTITUTION:A control circuit 2 reads the vector instruction from a main storage device 1 by using a bus 10, and decodes the instruction. When a vector register 4 specifiers random number generation and the person who has written the generated random number, the control circuit 2 starts a random number generator 6 through a bus 15. In addition, the control circuit 2 makes a switching circuit 18 operate by using a bus 12, and gives the instruction to write the results in the vector register 4 by using a bus 18. When the bector instruction is the operation instruction, the control circuit 2 connects input buses between the vector register 4 and vector operator 5.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a vector processing device equipped with a random number generator.
In particular, the present invention relates to a vector processing device suitable for Monte Carlo simulations in which it is necessary to generate a random number sequence in Takagi.

[Background of the invention]

When performing vector arithmetic processing using a random number sequence (for example, Monte Carlo simulation) using a conventional vector processing device, the random number sequence that is the basis of the vector arithmetic processing is stored in the main memory, and is transferred to the memory requester. or load it into a vector register by
A method has been adopted in which a random number sequence is generated on a vector register by a congruence method according to the teration command ◆.

However, the former method loads a random number sequence from the main memory, so it suffers from drawbacks such as a reduction in data transfer speed due to contention between multiple memory requesters, and an insufficient number of random numbers due to main memory constraints. had. On the other hand, in the latter method, the first-order 1teration order ◆ that is,
x;, +1=x;, + a;, -1-4g, '*
Due to the slowdown in vector calculation speed due to the sequential nature of type calculations (recent vector calculations have a processing speed of approximately AOa degrees, which is the limit for the above-mentioned sequential type calculations compared to other general vector calculations), it is difficult to generate random number sequences. had the disadvantage of consuming a lot of computer time.

[Purpose of the invention]

An object of the present invention is to provide a vector processing device with a plurality of random number generators, use the generators to generate arbitrary random number sequences in parallel, and store the random number sequences in a plurality of vector registers using vector instructions. The object of the present invention is to provide a vector processing device that can perform arbitrary vector processing using a random number sequence on the vector register.

[Summary of the invention]

When generating a random number sequence in a vector processing device, the conditions that the random number sequence must satisfy are: 1) it is reproducible, 2) the random number generation speed is high, close to the machine cycle pitch, and the random number sequence is a scalar ( (sequential) similar to a computer, and can obtain a random number sequence from multiple random number generators in parallel, and (3) satisfies the above three conditions: it must be possible to easily specify any random number sequence. As one of the algorithms to
There is a random number generation method using the congruence method.

However, this method performs the following sequential calculations, so xj, +, = mod (x↓pregnancy α, θ)... Song ■
It is not compatible with the vector arithmetic unit of the vector processing device. Here, θ is any positive number (usually taken as 231), α is a positive odd number, and mod means the remainder. For the values of α and θ, 'Seminumerical Algorithm
s, Random Numbers.

the art of Computer Progr.
aming Volume II (2nded,
)', D, E, Knuth, 19EN,
Addison-Wesley.

■If we transform the formula as follows, we get x, +2 mtrcL (mod (x4 supper a, θ
) α, θ) = mod (mad (αζθ) + xB
, θ )...The recurrence formula of the old congruence method does not represent the relationship between X+2 and xL, and is a formula that is two indexes apart.

This is X. , "Starting from two initial values of 1 (x, is found by sequential processing from X), "O→x2→X
By proceeding with the calculation as →...,X, →X, →xs→..., we show that it is possible to generate two random number sequences in parallel.

In the same way, the formula that is separated by the index is x4+, Z= mocL (mod (an, θ)*
JA, θ) -=...■ and "ON"j,...
...A random number sequence can be generated in parallel based on the initial value xn.

Utilizing this property, by continuously inputting ("Ol"j,...xn) columns to a pipeline multiplier with n-1 stages, the In addition, it is possible to insert a random number sequence into the machine cycle pitch. This method means that the random number generation method using the sequential congruence method has been converted into an independent calculation method using the number of stages of the vector arithmetic unit +1. Therefore, if this method is further expanded and applied to the random number generation rate consisting of a group of m multiple vector multipliers, if the number of stages of the vector multiplier is n-1, it is sufficient to create m+n independent calculation formulas. Become. This m
For the independent equation, the 61st term of the above-mentioned equation 0 can be set to αm''.In other words, a plurality of vector multipliers with a logical configuration that realizes the processing shown in FIG. 1 are installed in parallel, and the multiplier mad (α le,
By simply replacing θ) with mod(α7L+m, θ), a random number sequence by the congruence method can be obtained on the vector register at a pitch of 4 machine cycles. A vector processing device equipped with this parallel random number generator can perform vector arithmetic processing using a random number sequence at an extremely high speed that was not possible with conventional processing devices.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described using FIG. 2.3.

FIG. 2 shows an example of a vector processing device to which the present invention is applied. In FIG. 2, 1 is the main memory, 12 is the control circuit, 3 is the memory requester, 4 is the vector register, 5 is the vector arithmetic unit, 6 is the random number generator, and 7 and 8 are the output of the vector register and the vector arithmetic unit. , a switching circuit that dynamically generates a data bus between memory requesters (hereinafter both will be collectively referred to as resources).

The x displayed at the lower right of the memory requester 3, vector register 4, vector arithmetic unit 5, and random number generator 6 indicates that a plurality of such circuits exist, and n has no meaning.

When the vector processing device shown in FIG. 2 is activated, control circuit 2 uses bus 10 to read vector instructions from main memory 1 and then decode them. When a load or store from main memory is specified in the vector instruction sequence and there is a memory requester 6 that is not performing processing, the control circuit 2 uses the bus 11 to instruct the memory requester 3 to start up. do. At the same time, in the case of a load instruction, it acts on the switching circuit 8 via the ζ bus 12, connects the vector register t specified by the vector instruction with the output bus 16 of the memory requester targeted for activation, and Read data from the address specified by the vector instruction and store it in the specified vector register 4. In the case of a store instruction, the control circuit 2 acts on the switching circuit 7 via the bus 16 to generate a data bus between the vector register 4, the bus 17, and the memory requester 60.

When the vector instruction is an arithmetic instruction and the arithmetic unit is in a usable state, the control circuit 2 connects the input path of the vector register 4 specified as the operand of the vector instruction to the vector arithmetic unit 50 via the bus 13. conduct. At the same time, the vector calculator 5 is activated via the bus 14, and the bus 1
2, a data bus is connected to the vector register 4 into which the operation results are written.

When random number generation and the write destination vector register 4 of the generated random numbers are specified by a vector instruction, the control circuit 2 activates the random number generator 6 via the bus 15 and operates the switching circuit 8 using the bus 12. , gives an instruction to write the result into the vector register 4 using the bus 18.

By combining the above-mentioned basic processes, the vector processing device can perform vector calculation processing using a random number sequence, such as simulation, etc., as desired by the user.

FIG. 5 schematically shows the random number generator 6 on the second side. Before the control circuit 2 instructs the generator to start, appropriate values are stored in the vector length holding register 20 and the register 21 holding the multipliers, mod (alpha, θ), which are present in the random number generator. The two types of order information signal lines 15a and 15 of the control circuit 2 and the bus 15 are activated by a set-up instruction different from the random number generation instruction vector instruction.

and 15b. Since the values set in the registers 20 and 21 determine the properties of the random number sequence, the user can change these values by a program to generate a random number sequence with arbitrary properties.

After the setup via the bus 15 is completed, the random number generator is activated and the selector 22.2 is activated.
3.25.26 and switching circuit 24 are initialized to provide coupling of specific inputs (described in detail below) and output buses.

Next, the memory requester 28 in the random number generator stores the random number initial value (, ro, "1," in the main memory 1 via the bus 50).
2, .

seek In response to the read request, after the memory cycle time, the main memory device 1 sends read valid and data signals to the bus 5, which are signals to indicate that the read data is valid.
Send on 1. The memory requester 28 separates the data into valid data and data, and sends them to buses 52 and 53, respectively.
Anko is sent out. At this time, the selector 22 connects the valid counter 29 and the bus 52 through the setup process.

There are two valid random number initial value reads from the main storage device 1. This valid value is accumulated by the counter 29,
The count up value is sent on bus 54. On the other hand, the data signal separated by the requester 28 is transmitted to the latch 30.
The data is held in the RAM 31 via the selector 26 after being subjected to a timing delay until the necessary calculation of the valid counter 29 is completed. Here, the processing of the valid counter 29 is set to one clock. When the processing is a double clock, two stages of the latch circuit 30 are required. The output value on path 54 of valid counter 29 indicates the write address of RAM 31. With the above steps, the random number initial value ("01" 1, . . . , Jcn) is set on the RAM 31.

The value of the valid counter 29 is compared by a comparison circuit 32 every clock. When the random number generator 6 is activated, the selector 23 connects the data bus so that the output of the ROM 55 holding a constant equal to the number of multiplier stages + 1 is sent to the comparator circuit 62. When the number of valid signals sent from the path 55 becomes 1, the output of the comparison circuit 32 on the path 55 becomes '1'. switching circuit 24
is reset to connect paths 55 and 56 when the random number generator 6 is activated, so the main memory 1
When the number of valid accumulated values from 1 to 1 reaches 1, the detection information is passed through the path 56 to stop the operation of the memory requester 28, act on the selector 22, and input the clock pulse of the timing generator 64 to the valid counter 290. , resets the valid counter 29 (clears it to 0), acts on the count/return 35, and increases the count value by 1. Here, the counter 35 is a cycle counter whose value changes from 0→1→2→0→.... It also acts on the selector 37 and passes the valid signal and address of the counter 29 to the path 18a.
The paths 54 and 18a are connected so that they can be sent upward. −
Thereafter, in the vector processing device of the present invention, random numbers can be loaded onto the vector register 4 through the paths 18a and 18b.

Next, in synchronization with the output of the timing generator 34, the counter 29 is counted up in the order of 0→1→2, and so on. This value is passed through the path 54, and the read address and read data of the RAM 31 are passed through the paths 18a and 18, respectively.
b and is written into the vector register 4 in FIG. The vector multiplier 36 performs multiplication with the multiplier held in the register 21, ignores carry due to overflow during operation (in other words, takes the remainder of the data width of the multiplier), and sends the result onto the path 57. Send to. The result at this time is a random number sequence of cn+1, "fL+2 -1-.The multiplier on register 21 is motl
If (α+1.θ), the output random number sequence is xrL or a. 1%L+m+2,...

On the other hand, the output of the counter 29 is the number of stages of the multiplier +1
Then, the output of the comparison circuit 32 becomes '1' again. At this time, the switching circuit 24 connects the paths 55 and 58, so the selector 26 connects the RAM 5 via the path 58.
1 and the multiplier output path 57. Also pass 58
The above signals cause selector 25 to couple path 57 to the multiplier input bus, and selector 23 to couple vector length register 20 to comparison circuit 32. Pass 5 at the same time
The cycle counter 35 is counted up by the signal on the signal 8. The operation of the random number generator up to this point and the element numbers of the generated random numbers are shown in Figure 4 (time -2
). In Figure tll'5, when the counter 29 indicates number +1, the data on the path 57 on the selector 26 is a random number sequence f, n+4 (or xn+□,) as shown in Figure 4.
It is. Therefore, a random number sequence "yl+1Xu+2, . . . is written into RAMgl at one clock pitch.

When the value of the counter 29 becomes equal to the vector length, the output of the comparison circuit 32 becomes 11', and the operation of the multiplier 36 is stopped via the path 15c. At the same time, the completion of the random number generation process is reported to the control circuit 2 via path 15 (this path is bidirectional). Using the path 18, it is possible to read data at machine cycle pitch from time-1 in FIG. 4 onwards. If the RAM 31 in the random number generator has a plurality of banks, is equipped with a control circuit to control them, and has a function that allows reading and writing to the RAM in one machine cycle, The random number sequence can be read into the vector register 4 at any timing after time-1 in FIG. 4 and used for vector calculation processing using the random number sequence. Furthermore, even after random number generation is finished, the generated random number sequence is retained in the RAM 31 in the random number generator shown in FIG.
The sequence of numbers can be moved to the vector register 4 at any timing when the sequence is needed, and vector calculation processing can be performed.0 Generate the desired random number sequence once for the length of the vector, and then use the previous result again to generate the desired random number sequence. That is, when generating a continuous random number sequence, the previous result is written to the main memory 1, and when the next random number is generated, the latter part of the result is written to the RAM shown in FIG.
Just initialize it to 31. By specifying that this processing is to be performed continuously using a vector program, a random number sequence of any length can be generated within the vector processing device without data transfer between the main memory and the vector register. I can do it.

〔Effect of the invention〕

According to the present invention, arbitrary random number sequences can be generated in parallel using a plurality of random number generators, and this can be stored in a vector register, so that it can be supplied to various vector arithmetic units using the chaining function of the vector register. However, arbitrary vector calculation processing using a random number sequence can be performed at high speed.

FIG. 5 shows a conceptual diagram of a two-parallel Monte Carlo simulation using the method of the present invention.

In FIG. 5, 101 is a random number generator of the present invention, 102
is a vector register, and 106 is a vector arithmetic unit.

During simulation, the random number generator 101 writes a random number sequence (-A) into the register elements assigned respective numbers in the vector register 102 at machine cycle pitches. At the same time, by using the chaining operation of the vector register 102, the random number sequence being written to the register is used to read out the random number sequence at the same time as writing, and the vector arithmetic unit 103 performs simulation calculations in parallel, and converts the result into a vector. Write to register 102.

As described above, two-parallel Monte Carlo simulation can be realized by the vector processing device. By expanding 2-parallel processing to m-parallel processing), the processing speed seen from the user program becomes m times that expected from the machine cycle pitch, and an improvement in the performance of the vector processing device can be expected.

The random number generation shown in Fig. 5 separates even and odd numbers, but depending on the phenomenon to be simulated, (:to.

......-) and (:r:yuya1.....-T2
rL) column is separated and an independent random number sequence (3:o, ,T
, , ... 翫) and (ya , 2+ , ...
There are cases where it is better to generate two types of h) in succession to better solve the problem. In such a case, by using the random number generator built into the vector processing device of the present invention, the set-up conditions, that is, the initial random number sequence and the remainder of the multiplier can be matched to the desired random number sequence. By supplying it to a random number generator, it has the advantage that a target random number sequence can be generated at high speed without making any hardware changes.

[Brief explanation of the drawing]

FIG. 1 is a diagram conceptually showing input data, arithmetic processing, and output of a multiplier in a random number generator, FIG. 2 is a schematic block diagram of a vector processing device based on the present invention, and FIG. Figure 2 is a schematic block diagram of the random number generator in the vector processing device, Figure 4 is a diagram showing the time relationship of the random number generator in Figure 3, and Figure 5 is a diagram showing the time relationship of the random number generator in the vector processing device. FIG. 2 is a conceptual diagram of a parallel calculation method. DESCRIPTION OF SYMBOLS 1... Main memory device, 2... Control circuit, 3... Memory requester, 4... Vector register, 5...
Vector arithmetic unit, 6... Random number generator, 7.8... Switching circuit, 28... Built-in memory requester, 29... Valid counter, 31... RAM 16
2... Comparison circuit, 33... ROM. 34..., timing generator, 65... cycle counter, 36... pipeline multiplier, 50, 20, 21... register, first
Change the figure Figure 2 Figure 3 + What 11+e-1ttma-Z

Claims (1)

[Claims] A vector processing device that is equipped with a plurality of vector registers, arithmetic units, and a memory requester and that executes vector instructions includes a plurality of time-sharing pipeline random number generators, and an initial value of the random number generated by the random number generator. A storage means for holding a multiplier value that modifies the initial value, the initial value and the multiplier value being set by a program, is provided, and based on the initial value and the multiplier value held in the storage means. A vector processing device characterized in that an arithmetic random number sequence is generated in parallel using a vector instruction and transferred to a plurality of vector registers, and arbitrary vector processing is performed using the random number sequence on the vector register.