JPS60135943U - memory reading device - Google Patents

memory reading device

Info

Publication number
JPS60135943U
JPS60135943U JP1984022927U JP2292784U JPS60135943U JP S60135943 U JPS60135943 U JP S60135943U JP 1984022927 U JP1984022927 U JP 1984022927U JP 2292784 U JP2292784 U JP 2292784U JP S60135943 U JPS60135943 U JP S60135943U
Authority
JP
Japan
Prior art keywords
reading device
counting
memory reading
keys
address information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984022927U
Other languages
Japanese (ja)
Inventor
晋 鈴木
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1984022927U priority Critical patent/JPS60135943U/en
Publication of JPS60135943U publication Critical patent/JPS60135943U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案が適用される操作パネルの一例を示す図
、第２図は本考案の原理を示す図、第３図は本考案の一
実施例を示す図である。１，１′は操作キー、２゛は数
字表示器、３はメモリ選択回路、４はメモリ、１１〜１
４はカウンタをそれぞれ示す。FIG. 1 is a diagram showing an example of an operation panel to which the present invention is applied, FIG. 2 is a diagram showing the principle of the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. 1, 1' are operation keys, 2' is a numeric display, 3 is a memory selection circuit, 4 is a memory, 11-1
4 respectively indicate counters.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のキーと、該複数のキーにそれぞれ対応して設けら
れ各キーの押下入力回数を計数する計数手段と、各計数
手段の計数値を各桁の係数値とするアドレス情報を生成
する生成手段と、生成手段によって与えられるアドレス
情報に対応するメモリからデータを出力する出力手段と
を備えたメモリ読出装置。A plurality of keys, a counting means provided corresponding to each of the plurality of keys and counting the number of press inputs of each key, and a generating means for generating address information using the count value of each counting means as a coefficient value of each digit. and output means for outputting data from the memory corresponding to address information given by the generation means.
JP1984022927U 1984-02-20 1984-02-20 memory reading device Pending JPS60135943U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984022927U JPS60135943U (en) 1984-02-20 1984-02-20 memory reading device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984022927U JPS60135943U (en) 1984-02-20 1984-02-20 memory reading device

Publications (1)

Publication Number Publication Date
JPS60135943U true JPS60135943U (en) 1985-09-10

Family

ID=30515684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984022927U Pending JPS60135943U (en) 1984-02-20 1984-02-20 memory reading device

Country Status (1)

Country Link
JP (1) JPS60135943U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5672757A (en) * 1979-11-19 1981-06-17 Fujitsu Ltd Micro computer system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5672757A (en) * 1979-11-19 1981-06-17 Fujitsu Ltd Micro computer system

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