JPS6013488U - world clock - Google Patents
world clockInfo
- Publication number
- JPS6013488U JPS6013488U JP6666384U JP6666384U JPS6013488U JP S6013488 U JPS6013488 U JP S6013488U JP 6666384 U JP6666384 U JP 6666384U JP 6666384 U JP6666384 U JP 6666384U JP S6013488 U JPS6013488 U JP S6013488U
- Authority
- JP
- Japan
- Prior art keywords
- panels
- world clock
- display section
- clock
- world
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Instructional Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示し、第１図は正面図、第２
図は第１図■−■線断面図、第３図はブロック図、第４
〜５図はそれぞれ世界地図板の配列を変えた状態の正面
図である。
１・・・・・・世界時計、２・・・・・・世界地図板、
２”ａ〜２ｇ・・・・・・パネル、３・・・・・・連結
部材、５ａ〜５ｇ・・・・・・時計表示部、９・・・・
・・子時計駆動装置。The drawings show one embodiment of the present invention, with Figure 1 being a front view and Figure 2 being a front view.
Figure 1 is a cross-sectional view along the line ■-■, Figure 3 is a block diagram, and Figure 4 is a block diagram.
Figures 5 to 5 are front views of different world map board arrangements. 1... World clock, 2... World map board,
2"a to 2g...Panel, 3...Connection member, 5a to 5g...Clock display section, 9...
...Sub clock drive device.
Claims (1)
図板と、上記複数のパネルに配設した時計表示部と、こ
の特許表示部を駆動する計時装置と、上記複数のパネル
を連結する連結部材とから構成され、 上記複数のパネルは上記連結部により上記順序をすらし
て連結可能であることを特徴とする世界時計。[Claims for Utility Model Registration] A world map board constructed by arranging a plurality of panels in a predetermined order, a clock display section disposed on the plurality of panels, and a timekeeping device that drives this patent display section. and a connecting member that connects the plurality of panels, wherein the plurality of panels can be connected in the above order by the connecting portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6666384U JPS6013488U (en) | 1984-05-08 | 1984-05-08 | world clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6666384U JPS6013488U (en) | 1984-05-08 | 1984-05-08 | world clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6013488U true JPS6013488U (en) | 1985-01-29 |
| JPS6324463Y2 JPS6324463Y2 (en) | 1988-07-05 |
Family
ID=30196869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6666384U Granted JPS6013488U (en) | 1984-05-08 | 1984-05-08 | world clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6013488U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59980U (en) * | 1982-06-24 | 1984-01-06 | 株式会社精工舎 | world clock |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59980B2 (en) * | 1978-02-01 | 1984-01-10 | 三菱電機株式会社 | Electrostatic induction type semiconductor logic circuit device |
-
1984
- 1984-05-08 JP JP6666384U patent/JPS6013488U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59980U (en) * | 1982-06-24 | 1984-01-06 | 株式会社精工舎 | world clock |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6324463Y2 (en) | 1988-07-05 |
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