JPS60132432A - Disturbing wave eliminating device - Google Patents

Abstract

PURPOSE:To improve suppression characteristics of disturbing waves by combining a phase wave detector and a variable phase shifter at the reception part of a TV broadcasting device to constitute a feedback circuit. CONSTITUTION:The phase of the output of a subtraction circuit 22 is varied by wave detection voltages EI and EQ so as to obtain phases reverse to each other between the sum and the difference between vectors A and B applied to terminals 3 and 4. Then a phase wave detector using a balance mixer 36 is combined with a variable phase shifter 29 to obtain a feedback circuit. A fine adjustment is given to the phase of the output of an in-phase distributor 28 by the output of an LPF38 so as to obtain the accurate phases reverse to each other between the sum and the difference of vectors A and B. In such a way, an error caused by the variation of phases between balance mixers 26 and 27 can be eliminated.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is capable of removing unnecessary interference waves other than broadcast waves from a desired master station in a receiving section of a relay broadcasting machine such as a televisual relay broadcasting station. The present invention relates to an interference wave removal device.

[Technical background of the invention]

In general, at relay broadcasting stations, in addition to the desired radio waves transmitted from the master station, unnecessary interference waves are input into the receiving band, appearing as beat screens and -1 sounds, deteriorating the quality of broadcasting. .

In order to prevent this, a method is used in which two to three transmitting antennas are used and the phase difference between the interference waves is used to cancel them out.

However, when the direction of the interference waves changes, the preset antenna spacing does not result in a well-inverted phase, resulting in residual cancellation. At the same time, the subtraction circuit performs subtraction, the subtraction result is phase-shifted by 90 degrees, the amplitude is adjusted, and the second addition circuit adds the addition result of @1 addition circuit, and the addition result is 90 degrees from the addition result. There is a system in which the phase-shifted subtraction result is synchronously detected and fed to a second addition circuit.

FIG. 1 is a diagram showing the principle by which the phase difference between the interfering wave and the desired wave of the two receiving antennas is generated in this 1 "jamming wave removal method". In FIG. 1, 1 is a desired wave, and 3 and 4 are receiving antennas. Receiving antennas 3 and 4 are each connected to a second receiver (not shown) 4i.These two receiving antennas 3.4 transmit the desired wave 1 at an interval d approximately equal to λ (wavelength). They are arranged side by side in a direction orthogonal to the receiving antenna 3.4, and the desired wave J is in phase with each receiving antenna 3.4, and the interference wave 2 has a phase difference of ψ=2Kf-d-picture0.

FIG. 2 shows the vector of the desired wave I at the receiving antennas 3, 4-, and FIG. 3 shows the vector of the interference wave 2 with respect to the receiving antenna 3.4.

Figure 4 focuses on the interference wave 2 and connects these two receiving antennas 3.
, 4, the vector Ia is obtained. On the other hand, the difference between the vectors becomes vector 15. In this FIG. 4, 11 indicates the interference wave input vector of the receiving antenna 3, 12v; 0. The interference wave input vector of the receiving antenna 4 is shown, 13 is the signal (-B) whose phase is inverted from the antenna 4, and the vector 4 is the sum of the interference wave input vector 1 and @J2, that is, the vector X+
It is a vector tube (with sum signal).

In addition, vector 15 is the difference between the interference wave input vector 11.12, that is, vector A - vector 100 (differential signal), and 16 is the difference between the interference wave input vector 11.12, which is 1sf90f delayed and multiplied by m. signal, (i.e. at -).

Here, the interference wave level of the output of the receiving antenna 3 and the interference wave level of the output of the receiving antenna 14 are equal to vector 14 because the distance d between both antennas 3 and 4 is at most about λ (wavelength), Vector 15 is always orthogonal.

From this, it is assumed that the interference waves can be canceled by shifting the phase of the vector I5f by 90 degrees and changing the level to an appropriate level.

Also, Figure 5 is a diagram showing the configuration of the above-mentioned "interference wave elimination reception system" which is equipped with two receiving antennas based on the principle of canceling interference waves shown in Figure 4. In this Figure 5, The same parts as in FIGS. 1 to 4 are given the same reference numerals.

The interference waves received by the reception antennas 3 and 4 are added to the adder circuit 23 via the distributors 21 and 24, where addition is performed. The sum output of the adder circuit 23 is sent to the adder circuit 29
sent to.

At the same time, the interference waves received by the reception antennas 3 and 4 are applied to the subtraction circuit 22 via the distributor 21p24, where subtraction is performed and the difference output is sent to the 90 degree phase shifter 22.
Sent to 5.

After the differential output is phase-shifted by 90 degrees by the 90-degree phase shifter 25, it is divided into two parts by the divider 26, one of which is sent to the variable gain amplifier 27 and the other to the amplifier 2H. This distributor 26
The other fully passed differential output is amplified by the amplifier 28, and only a predetermined band component is extracted by the band tR filter 32 and added to the synchronous detector 31 as a reference signal source.

On the other hand, in the sum signal output, the difference output is phase-shifted by a 90-degree phase shifter 25 to have an opposite phase, and is added to a signal whose amplitude is adjusted by a variable gain amplifier 27 by an adder circuit 29, where the residual component is When generated, the signal passes through the distributor 30 and is input to the synchronous detector 3, where it is synchronously detected with the previously input reference signal.

Here, since the reference signal and the residual interference component have the same frequency and constant phase, the output of the synchronous detector 31 is a DC component signal according to the amplitude of the residual interference component. This signal passes through the low noise filter 33 to the variable gain amplifier 27.
control.

This control always works to reduce the interference waves, so eventually the interference waves can be eliminated.

[Problems with background technology]

[7] However, in the above-mentioned interference wave removal reception method, the bad pass filter 32 is inserted only in one place between the amplifier 28 and the synchronous detector 3, but the In order to further increase the efficiency, (1) it is sufficient to insert filters into all the high-frequency input terminals of those detectors, and (2) the selectivity of the filters can be increased so that only the interfering waves are passed. The effect can be increased by using a filter.

However, simply configuring the filter as described above causes other problems as listed below.

(1) Since filters are expensive, the equipment becomes expensive.

(2) It is difficult to match filter characteristics, especially group delay time characteristics, within the band.

(3) It is difficult to match the stability of filters against environmental changes such as temperature characteristics.

ttifI/C1 If the device is constructed by ignoring the characteristics of items (2) and (32), it will not be possible to exhibit good suppression characteristics against frequency changes and environmental changes.

[Purpose of the invention]

This invention was made in view of the above points, and it is possible to further demonstrate the effect of the filter while avoiding the above-mentioned problems.
It is an object of the present invention to provide an interference wave removal device that has good interference wave suppression characteristics.

[Summary of the invention]

The present invention includes two receiving antennas arranged at a predetermined interval, an addition circuit and a subtraction circuit that add and subtract signals received by the reception antennas, and a first and subtraction circuit to which the outputs of the addition and subtraction circuits are supplied. a second switch circuit;
A fee word circuit detects the phase of the output of these switch circuits and variably controls the phase of the reduced IL signal using the detected output so that the sum and difference of the received signals have opposite phases. , a circuit that variably attenuates the output of the feedforward circuit, a circuit that combines the variably attenuated signal with the output of the adder circuit, and third and fourth circuits to which the combined output and the output of the feedforward circuit are supplied. a switch circuit, and a feedpack circuit that performs phase detection and synchronous detection of the outputs of these Swiss-Sochi circuits, adjusts the phase of the feedforward circuit output using the phase detection output, and adjusts the variable attenuation circuit using the synchronous detection output; Above 1st and 2nd. means for operating the third and fourth switch circuits in a predetermined order; and a bandpass filter connected to each of the switch circuits operated by the means, supplied with the switch circuit input, and deriving the switch circuit output. , all are configured as a single bandpass filter.

[Embodiments of the invention]

Embodiments of the interference wave removal device of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram showing the configuration of one embodiment. In FIG. 6, some parts that are the same as those in FIGS. 1 to 5 will be described with the same reference numerals.

In this FIG. 6, the receiving antenna 3 is connected to the in-phase distributor 21.
f: Subtraction circuit 22. It is connected to the adder circuit 23. In addition, the receiving antenna 4 is connected to the in-phase distributor 24 through
Similarly, it is connected to a subtraction circuit 22 and an addition circuit 23.

The output of the subtraction circuit 22 is outputted to balance mixers 26 and 27 through a 90 degree divider 25. 90
The frequency divider 25 transfers the output of the amplification circuit 22 to the balance mixer 2.
6 is sent in the same phase, and balanced mixer 27
O balance mixer 26, . The outputs of 27 are respectively passed through the in-phase synthesizer 28 and output to the variable phase shifter 29. The output of the variable phase shifter 29 is outputted to the synthesizer 31 through the variable attenuator 30, and is also sent to the phase locked oscillator 33 (hereinafter referred to as PLO) via the high frequency switch 32. It is designed to be output.

The output of this PLOJ 3 is sent through the entire in-phase distributor 34 to the parallel waveforms 35 and 36 for synchronous detection and phase detection. The output of the balance mixer 35 is applied to the variable attenuator 30 through a low-frequency p-wave generator 37 and a sample hold aft 52f.

Further, the output of the balance mixer 36 is applied to the variable phase shifter 29 through the S/F filter amplifier f51 and the low-frequency P wave generator 38.

The output of the subtraction circuit 22 is input to the PLOJ 9 through a high frequency switch 32b. The output of this PLO 39 passes through an in-phase distributor 40f and is output to balanced mixers 41 and 42.

Furthermore, the output of the adder circuit 23 is a high frequency switch, Sochi 32a.
and 90 degree divider 4 (JA'i) to output to balance mixers 41 and 42. The signal is sent to the balance mixer 42 with a phase shift of 90 degrees.

The balanced mixers 41 and 42 phase-detect the output of the in-phase divider 40 and the output of the 90-degree divider 4σA, respectively, to generate detected voltages, and filters 5J, 54, A/G 4
The signal is outputted to the balance mixers 26 and 27 via 3 and 44.

The output of the adder circuit 23 is also sent to a combiner 31, which combines the output of the variable attenuator 30 and the output of the adder circuit 23, and the output is sent to the high frequency switch 32c and It passes through the entire 90-degree distributor 45 and sends it to the balance mixer 35.degree. 36.

This balance mixer 35? 6 performs contrast detection between the output of the 90 degree distributor 45 and the output of the PLOE 3.

The above-mentioned high frequency switches and notches 32h to 32d are each at timing 12. V to perform opening/closing operation at tJ, tJ, tJ.
As shown in Fig. 8, the timing t1
It is arranged to turn on and off in sequence from t4 to t4.

One terminal a, d of each high frequency switch 9 32h to 32d
y e + h is connected to a bad pass filter 46 as shown in FIG. Therefore, the output of the addition circuit 23, the output of the subtraction circuit 22, the output of the synthesizer 31, and the output of the variable phase shifter 29 are respectively input to the bandpass filter 46.

The output of the bad bus filter 46 is applied through an amplitude limiter 47 to the other terminals of the high frequency switches 32a to 32d, i.e., c+f+g.

Next, the operation of the interference wave removing apparatus of the present invention having the VC configured as described above will be explained. Receiving antenna 3, 4
The interfering waves received at the respective in-phase distributors 21 and 24 are added to the adder circuit 23, where they are combined, and the combined output is sent to the combiner 31J, - and the high frequency switch 32.
ILV is added.

Similarly, the interference waves received by the receiving antennas 3 and 4 are respectively applied to the subtraction circuit 22, where they are combined (subtracted), and the combined output is sent to the high frequency switch 32b1.
90If is added to the distributor 25. The output of the t21F-circuit 22 applied to the 90 degree divider 25 is sent to the balance mixer 26 in the same phase as this output, and to the balance mixer 27, it is sent out in phase with the output of the subtraction circuit 22. , are added with a 90 degree phase shift.

On the other hand, the high frequency switches 32 a to 32 dIrJ are sequentially turned on and off at the timing shown in FIG.
Added to PLO39 through 2b. The PLO 39 is fixed to the phase of the output of the subtraction circuit 22 and is connected to the in-phase distributor 40.
Output to.

The output of this in-phase distributor 4o fi PLOs 9 is similarly applied to balanced mixers 41 and 42. At the same time, the output of the adder circuit 23 is applied to the 90 degree distributor 41JA through the high frequency switch Sochi 32af.

The 90 degree divider 40 sends the output of the adder circuit 23 to the balance mixer 41 in the same phase, and outputs the output to the para/mixer 421C with a phase shift of 9 () degrees.

Balanced mixers 41 and 42 perform phase detection of the output of the in-phase synthesizer 40 and the output of the 90-degree phase shifter 40, respectively.

That is, the balanced mixers 41 and 42 operate as phase detectors, and detect the detected voltage El due to the vector sum and difference of the interference waves of the receiving antennas 3 and 4, and the phase difference of A+1 and 1, >7.
Outputs EQ.

This detected voltage El is applied to the filter 53. It is applied to the balance mixer 26 through the up 43, and the detection voltage EQ
is filter 54. Balance mixer 2 through up 44
7 and this detection voltage 11. EQICJ: The p-controlled noise/mixer 26.2 functions as a variable phase shifter, and varies the phase of the output of the subtraction circuit 22 by the detection voltages EI and EQ, and converts it into R vector A + vector 1. On the other hand, the phase of the spectral arvector 100 is made to be in reverse phase. Thus, balance mixers 41, 42, 2
The section 6.27 acts as a feedforward phase control circuit.

In this way, vector A+vector B and vector A-vector B'z are made to have almost opposite phases, but with only these nine feedforward circuits, the balanced mixers 26, 2
The error caused by changing the phase in step 7 becomes a hole in the left state, and the above-mentioned opposite phase is not necessarily maintained.

In order to solve this problem, in the present invention, a phase detector using a balanced mixer 36 and a variable phase shifter 29 are further combined to form a feed pass circuit, and vector A+vector B and vector W-vector 1 are combined. It is resolved so that the phase is reversed.

In the present invention, as shown in FIG. 7, only one set of Nokundo/Yasu filter 46 is prepared, and this band "pass filter 46 only needs to be manufactured with emphasis on selectivity. Sfilter 46f!: Allocate to necessary locations at the timing shown in FIG.
4 are operated in synchronization, and at timing t4, the high frequency switch notch 32c and the ups 51 and 52 are operated in synchronization.

In this FIG. 8, at timing t (l), the cascade circuit of the bandpass filter 46 and the amplitude limiter 4/J 47 is connected to one terminal C and the other terminal 6 of the high frequency switch i2b in FIG. Next, at timing t2 in FIG. 8, the bandpass filter in FIG. Connect the cascade circuit with Mizuta 47,
1.42 to operate as a phase detector.

That is, a signal with a predetermined bandwidth is extracted from the output of the adder circuit 23 through a 1 ft.
1'f! : In addition to balanced mixers 41 and 42, phase detection is performed there with the output of the in-phase distributor 40 to increase the detected voltage.
Add to 7. In other words, amplifiers F43 and F44 are amplifiers that are used as a S/F hold circuit that holds at timing t2.

Next, timing t3 in FIG. At t4, the 6th
The system on the right side of the figure performs a similar operation, and the cascade circuit of the bus filter 46 and amplitude limiter 47 shown in FIG. 7 is connected to the high frequency switches 32d and 32c, respectively.

Now, as described above, at timing t2 in FIG.
The detected voltage EI obtained from the rose/mixer 41 and 42,
Balance mixer 26, 27f: After controlling with EQ and varying the phase of the output of the 90 degree distributor 25, the output of this balance mixer 26 + 27 is passed through the in-phase synthesizer 28,
added to the variable phase shifter 29 where it is further phase shifted;
Variable attenuator 30. It is added to the high frequency switch 32d.

Next, at timing t3 in FIG. 8, the cascade circuit of the bad IP filter 46, amplitude limiter, and vine 47 in FIG. 7 is connected between one terminal g and the other terminal of the high frequency switch 32d, and the PLO 33 is Mouth is exposed.

Next, at timing t4, this cascade circuit is connected between one terminal e and the other terminal f of the high frequency switch 32c.

At this time, a signal in which the output of the variable attenuator 3° and the output of the adder circuit 23 are combined by the combiner 31 passes through the high frequency switch 32c, the band pass filter 46, and the amplitude limiter 47, and is added to the 90 degree divider 45. Furthermore, the output of the 90-degree distributor 45 is applied to the balance mixer 36.

As a result, the 1-balance mixer 36 performs phase detection between the output of the 90-degree divider 45 and the signal output from the PLO 33 and passed through the in-phase combiner 34.

The synchronous detection voltage obtained by the balanced mixer 35 is output to the low-frequency p-wave generator 37, where only the low frequency component is extracted and is applied to the variable attenuator 30 by the amplifier 52 at timing t4.

The variable attenuator 30 controls the amount of attenuation of the output of the variable phase shifter 29 using the output of the low-frequency wave transducer 37 and adds it to the synthesizer 3JIlC. Also, the phase detection voltage 1 obtained by the balance mixer 36 is output at timing t4. Then, the signal is sampled and held by the amplifier 51 and applied to the low-frequency P-wave generator 38 , where only the low frequency component is extracted and applied to the variable phase shifter 29 . This results in 1
The variable phase shifter 29 uses the output of the low-pass p-wave shifter 38 to finely adjust the phase of the output of the in-phase distributor 2H.

In addition, in the embodiment shown in FIG. 6, PLO39°332
Although the case where a phase is used is illustrated, this is to facilitate understanding of the present invention, and it is also possible to use one PLO at two locations.

! f, *, An example of a band filter 46 with good performance is a crystal filter.
As shown in FIG. 9, a 9-lance mixer 50 is inserted in the front stage V of the Pantonoyas filter 46 shown in the figure, and the balance mixer 50 receives the sum (fv + fu) of the carrier signal fv and the interference wave fu. 1 carrier signal fv may be added, subjected to frequency conversion, and then applied to the Pantonoyas filter 46 in the baseband region.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to use a single 4-nd Yas filter, so this filter can be made highly accurate, stable, and the effects of frequency changes can be removed, and the interference wave suppression characteristics are good. It has the following advantages.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the principle of generating a phase difference between the interference wave and the desired wave of the two receiving antennas applied to the interference wave removal device of the present invention. Figure 3 is a diagram showing the desired wave vector of the receiving antenna. Figure 3 is a diagram showing the interference wave vector of the two receiving antennas in Figure 1.
The figure is a diagram for explaining one vector of the sum and difference of the interference waves of the two receiving antennas as above, FIG. 5 is a block diagram of the interference wave removal reception method of the invention of the earlier application, and FIG. FIG. 7 is a block diagram showing the configuration of an embodiment of the interference wave removal device, and FIG. 7 shows a cascade circuit of a band filter, an amplitude limiter, and an ivy connected to the high frequency switch and notch circuit in the interference wave removal device. A block diagram, FIG. 8 is a timing chart showing the operation timing of the high frequency switch in the above interference wave removal device, and FIG. 9 is a program showing another embodiment of the high frequency switch in the above interference wave removal device and the circuit connected to the Sochi circuit. , V diagram. 3.4...Receiving antenna, 21*24.28°34.
40...In-phase distributor, 22...Subtraction circuit, 23...
-Addition circuit, 31...Synthesizer, 25.401L. 45...90 degree distributor, 26.27.35.36+4
1.42.50...Balance mixer, 30...Variable attenuator, 32a-32d...High frequency switch, switch, 33
．． 39...PLO137,, i 8...Low frequency υ waveform generator, 43.44, 51.52...Amplifier, 46...Bad pass filter, 47...Amplitude limiter, retarder.

Claims (1)

[Claims] two receiving antennas arranged at a predetermined interval;
An addition circuit and a subtraction circuit that add and subtract signals received by the reception antenna, first and second switch circuits to which the outputs of the addition and subtraction circuits are supplied, and phase detection of the outputs of these switch circuits. a feedforward circuit that variably controls the phase of the subtracted signal according to the output so that the sum and difference of the received signals have opposite phases; a circuit that variably attenuates the output of the feedforward circuit; and a circuit that variably attenuates the output of the feedforward circuit; a circuit for synthesizing the signal and the output of the adder circuit, third and fourth switch circuits to which the synthesized output and the output of the feedforward circuit are supplied, and performing phase detection and synchronous detection of the outputs of these switch circuits. , a feed pavcu circuit that adjusts the phase pot of the feed forward circuit output using the phase detection output and the variable attenuation circuit using the synchronous detection output; Second.
FR according to the predetermined order of the third and fourth switch circuits
and a bandpass filter connected to each of the above-mentioned switch circuits operated by the means, supplied with switch circuit power, and deriving the switch circuit output.