JPS60129693U - timer device - Google Patents
timer deviceInfo
- Publication number
- JPS60129693U JPS60129693U JP1769384U JP1769384U JPS60129693U JP S60129693 U JPS60129693 U JP S60129693U JP 1769384 U JP1769384 U JP 1769384U JP 1769384 U JP1769384 U JP 1769384U JP S60129693 U JPS60129693 U JP S60129693U
- Authority
- JP
- Japan
- Prior art keywords
- schedule
- time
- keyboard
- clock
- timer device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来のタイマー装置の一実施例の構成図、第
２図はこの考案によるタイマー装置の一実施例の構成図
、第３図はその動作を示すフローチャートである。
図中、１はクロック、２はＣＰＵ、 ３はメモリ、４は
キーボード、５はスピーカ、６は音声合成器、７はディ
スプレイである。なお、図中同一符号は同一、又は相当
部分を示す。FIG. 1 is a block diagram of an embodiment of a conventional timer device, FIG. 2 is a block diagram of an embodiment of the timer device according to this invention, and FIG. 3 is a flowchart showing its operation. In the figure, 1 is a clock, 2 is a CPU, 3 is a memory, 4 is a keyboard, 5 is a speaker, 6 is a voice synthesizer, and 7 is a display. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
、前記キーボードより入力されたスケジュールを記憶す
るメモリと、時間を計測するクロックと、このクロック
より読み取られた時間を入力とし、予定事項の該当時刻
に内容を表示するディスプレイと、前記ディスプレイに
表示される内容を音声信号に変換する音声合成器と、前
記音声合成器より出力される音声信号を流すスピーカ゛
と、装置全体を制御するＣＰＵとを備えたタイマー
装置。A keyboard for inputting the date, time, contents, etc. of the schedule, a memory for storing the schedule input from the keyboard, a clock for measuring time, and a time read from the clock for inputting the corresponding schedule for the schedule. A display that displays content at the time of day, a speech synthesizer that converts the content displayed on the display into an audio signal, a speaker that transmits the audio signal output from the speech synthesizer, and a CPU that controls the entire device. Equipped with a timer device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1769384U JPS60129693U (en) | 1984-02-10 | 1984-02-10 | timer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1769384U JPS60129693U (en) | 1984-02-10 | 1984-02-10 | timer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60129693U true JPS60129693U (en) | 1985-08-30 |
Family
ID=30505633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1769384U Pending JPS60129693U (en) | 1984-02-10 | 1984-02-10 | timer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60129693U (en) |
-
1984
- 1984-02-10 JP JP1769384U patent/JPS60129693U/en active Pending
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