JPS60128734A - Converting circuit of digital signal - Google Patents

Abstract

PURPOSE:To stabilize operations to resolve problems of difficulty of mounting, large power consumption due to high-speed element, etc. by performing signal processings with digital circuits to convert component color video signals to time division multiple color video signals. CONSTITUTION:Digital component color video signals Y, R-Y, and B-Y having a sampling frequency fs are supplied to memory circuits 60, 61, and 62 through registers 52, 53, and 54 and selectors 56, 56, and 58. Each of memory circuits 60, 61, and 62 consists of a pair of memories, and each memory of this pair of memories is switched from/to the write state to/from the read state in every one horizontal section, and one memory is set to the read state while the other is set to the write state. Outputs read out from memory circuits 60, 61, and 62 are supplied to a selector 71 through selectors 63, 64, and 65 and registers 67, 68, and 69. A latch pulse having a frequency 3fs is supplied to a register 73 from a terminal 74, and time division multiple color video signals are taken out from a terminal 75.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal conversion circuit used for time division multiplexing a plurality of digital signals such as digital component color video signals.

"Background technology and its problems" Traditionally, video signals were transmitted between the camera head and CCU (camera control unit) using multi-core cables, but multi-core cables were not suitable for long-distance transmission. Transmission using a single double-shielded coaxial cable is being considered.

For example, when transmitting a video signal between a camera head and a CCU using a double-shielded coaxial cable, the color difference signal B
It has been proposed to perform orthogonal two-phase modulation on a video signal consisting of -Y and 'RY, and to transmit the resultant signal by superimposing it on a luminance signal Y. However, the S/N ratio deteriorates due to crosstalk, and phase compensation between channels is required.

This method has drawbacks such as a complicated branching filter, making it difficult to perform transmission while maintaining high image quality.

Therefore, it is desirable to directly transmit AM or FM modulation of a component color video signal consisting of three primary color signals RGB, color difference signals R-Y, B-Y, and luminance signal Y, etc. However, when these component color video signals are subjected to AM modulation or FM modulation as they are, there is a problem that the occupied band becomes wider. Therefore, it is conceivable to narrow the occupied band by time-division multiplexing the component color video signals, and transmit the signals after AM modulation or FM modulation. However, it has been difficult to time-division multiplex component color video signals in an analog manner.

OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide a digital signal conversion circuit suitable for use in converting component color video signals into time division multiplexed color video signals using digital circuits.

[Summary of the Invention] The present invention is a circuit for converting n parallel digital input signals having the same sampling frequency into time-division multiplexed signals serially multiplexed by time pressure network. n pairs of memories are provided, and each pair of memories is switched between a write state and a read state at a predetermined period, and is controlled so that when one is in the write state, the other is in the read state, and n parallel digitization is performed. Each of the input signals is sequentially switched and inputted to one of the n memory pairs every sampling period, and is read from the other of the n memory pairs every sampling period and stored in the corresponding register. Select the contents sequentially within the sampling period,
This digital signal conversion circuit is configured such that each of the n input signals is time-compressed into -[ and sequentially obtained in information units of the predetermined period.

"Embodiment" Figure 1 shows a camera head and CCU to which this invention is applied.
(camera control unit). The camera head and CC0 are connected by a double-shielded coaxial cable indicated by 1. As shown in Figure 2, the coaxial cable 1 connected between the camera head and CC0 is used to send a color video signal from camera 2 to CCU 3, as well as a return video signal from CCU 3 to camera 2 and to the performer. A video signal for a teleprompter to show lines, etc. is sent. This allows the viewfinder 2A
And the photographed screen of the camera 2 is played back on the monitor 2B. Power is still being supplied to camera 2 from CCU3,
These three video signals and power are transmitted between the camera 2 and the CCU 3 via the coaxial cable 1.

In FIG. 1, reference numerals 4, 5.6 indicate input terminals, and analog component color video signals (luminance signal Y and color difference signals RY, B-Y) from the imaging section are input to the input terminals 4, 5.6.
6, respectively.

The component color video signals Y, R-Y, B'-Y supplied to the input terminals 4, 5.6 are band-limited via the low-pass filters 7.8.9, and the A/D converter 1
0.11.12 respectively. A/D converter 1
0.11.12 is supplied with a sampling clock of frequency fs from the clock generation circuit 13, and the A/D
The converters 10, 11, and 12 digitize the component output video signals Y, RY, and BY, respectively. The clock generation circuit 13 has, for example, a P'LL configuration, is supplied with a horizontal synchronizing signal from a terminal 14, and has a frequency fS (for example, 13.5 MH2) synchronized with the horizontal synchronizing signal.
) and a clock with a frequency of 3 fs and a sine wave with a frequency of 3 fs are formed.

The respective outputs of the A/D converters 10, 11, and 12 are supplied to a multiplexer 15 for time division multiplexing to which the present invention is applied. The digital component video signal supplied to the multiplexer 15 for time division multiplexing is digitally processed and time division multiplexed. The 3rd
Figure A, Figure 3B.

After being digitized, the analog component color video signals Y, RY, and BY shown in FIG. 3C are digitally processed by a multiplexer 15 for time division multiplexing. The multiplexer 15 for time division multiplexing includes
Clock having the remaining frequencies fS and 3f8 are supplied from the clock generation circuit 13.

A digital color video signal time-division multiplexed by a multiplexer 15 for time-division multiplexing is supplied to a D/A converter 16. The D/A converter 6 is supplied with a clock having a frequency of 3f from the clock generation circuit 13, and the D/A converter 6 converts the time-division multiplexed color video signal of the digital signal into an analog signal. . That is, as shown in the third diagram, a signal is obtained from the D/A converter 6 in which the component color video signal whose time axis is compressed to 1- is sequentially inserted into one horizontal section.

The time-division multiplexed color video signal from the D/A converter 6 is band-limited through a low-pass filter 7,
The signal is supplied to the AM modulation circuit 18. A sine wave with a frequency of 3f is supplied from the clock generation circuit 13 as a carrier wave to the AM modulation circuit 18, and the time division multiplexed color video signal is
M modulated.

The output of the AM modulation circuit 18 is supplied to the mixing circuit 19, which mixes the audio signal supplied from the terminal 20 with the AM modulation circuit 1.
The outputs of 8 are mixed. The output of the mixing circuit 19 is supplied to the drive amplifier 21, amplified, and then transmitted to the CCU side via the coaxial cable 1.

The output transmitted from the camera head side via the coaxial cable 1 is supplied to the receiving amplifier 22 on the CCU side. The output amplified by the receiving amplifier 22 is sent to the filters 23 and 2.
4, the fill 23 extracts the audio signal, and the fill 24 extracts the modulated time division multiplexed color video signal. The filter 24 is provided with a filter (not shown) for carrier wave component separation.
The separated carrier wave component of frequency 3f is supplied to a clock recovery circuit 25, and the output of the fill 24 is supplied to an AM demodulation circuit 26.

The clock regeneration circuit 25 is for regenerating a clock synchronized with the carrier wave from the carrier wave having a frequency of 3fS extracted from the filter 24. The clock regeneration circuit 25 reproduces a clock having a frequency fs equal to the sampling clock and a clock having a frequency of 3fS. is formed, and the frequency f
A sine wave of 8.3 f and 6 fs is formed.

The AM demodulation circuit 26 is supplied with a sine wave having a frequency of 3f8 from the clock regeneration circuit 25, and the demodulation circuit 26 demodulates the time division multiplexed color video signal.

The time-division multiplexed color video signal demodulated by the AM demodulation circuit 26 is band-limited via the low-pass filter 21 and supplied to the A/D converter 28 .

The A/D converter 28 is supplied with a clock having a frequency of 3f from the clock regeneration circuit 25, and the time division multiplexed color video signal is digitized by the A/D converter 28. The time division multiplexed digital color video signal from the A/D converter 28 is sent to the demultiplexer 29.
supplied to

The demultiplexer 29 is supplied with a clock of frequency f8 from the clock recovery circuit 25, and the demultiplexer 29
9, the time-division multiplexed digital color video signal is digitally processed, the time axis is expanded three times,
Digital component color video signal Y, R-Y
, B-Y.

Digital component color video signals Y, R-Y converted by demultiplexer 29.

B-Y are supplied to D/A converters 30, 31, and 32, respectively. D/A converters 30, 31. 32 is supplied with a clock of frequency f from the clock regeneration circuit 25, and the D/A converters 30, 31 and 32 convert the digital component color video signals Y, R-Y,
B- and Y are converted into analog signals, band-limited through low-pass filters 33, 34, and 35, and output to an output terminal 36.
．． 37 and 38 respectively.

Luminance signal Y taken out as an output to the low-pass filter 33
is taken out to the output terminal 36 and the AM modulation circuit 3
9 and 40. One AM modulation circuit 39 is supplied with a sine wave of frequency f6 from the clock regeneration circuit 25, and this sine wave is AM-modulated by the luminance signal Y to form a return video signal. Further, the other AM modulation circuit 40 receives the frequency 6 f3 from the clock regeneration circuit 25.
A sine wave is supplied, and this sine wave is applied to the luminance signal Y.
M modulation is performed to form a video signal for telephotography.

The return video signal formed by the AM modulation circuits 39 and 40 and the video signal for the teleprompter are supplied to a mixing circuit 41, and the mixed output of the mixing circuit 41 is amplified by the drive amplifier 42, and the coaxial cable 1
is transmitted to the camera head side via.

The return video signal and the video signal for the teleprompter transmitted via the coaxial cable 1 are supplied to the receiving amplifier 43 on the camera head side, where they are subjected to signal processing such as AM demodulation (not shown), and sent to the viewfinder 2A and the monitor. It is played back by 2B.

The signal transmitted via this coaxial cable 1 has a frequency spectrum shown in FIG. 4E. In other words,
The output signal of the D/A converter 16 consists of the time division multiplexed color video signal Tf and its harmonic components, as shown in FIG. 4A.

The time division multiplexed color video signal was digitized with a sampling clock of frequency f. The three component color video signals Y, R-Y, and B-Y are time-axis compressed and time-division multiplexed for each horizontal section, and are equivalent to being digitized using a sampling clock with a frequency of 3fS. Therefore, the center frequency of this harmonic component is an integral multiple of 3fS.

The harmonic components are removed by the low-pass filter 17 as shown in FIG.
The carrier wave of f is AM modulated, and the carrier wave of A as shown in FIG.
The M-modulated time-division multiplexed color video signal TAM is transmitted to the CCLI side via the coaxial cable 1. The fourth diagram shows the frequency spectra of the AM-modulated return video signal Sr and the video signal St for the telephoto sensor transmitted from the CCU side to the camera head side, and these carrier waves are assumed to be an integral multiple of the sampling frequency fS. There is.

FIG. 5 shows an embodiment of the present invention. This embodiment is an application of the present invention to the above-mentioned multiplexer 15 for time division multiplexing.

Digital component color video signals Y, R-Y,
B-Y is supplied to registers 52, 53, and 54, respectively, and latched. A clock with a frequency of "8" is supplied as a latch pulse from a terminal 55 to the registers 52, 53, and 54.

The respective outputs of registers 52, 53, and 54 are output to selector 5.
Delivered on 6.57.58. selector 56.57.5
A select signal is supplied from a terminal 59 to memory circuits 60, 61, which select the respective outputs taken out to selectors 56, 57, and 58, and are shown surrounded by broken lines.

62, respectively. Memory circuits 60, 61.

62t/'i, each consisting of a pair of memories 60A, 60B and 61A, 61B, and 62A, 62B, and the writing state and reading state of each pair of memories are switched off from each other every horizontal section. When one is in the read state, the other is in the write state. Memory circuit 6
Writing and reading of 0.61.62 are performed as follows.

FIG. 6 shows data written to the memory circuits 60, 61, and 62, respectively. In FIG. 6, 'ro, T, .
"r2....." indicates the time, and each time T is T-
It was the time of the 8th. The address at each time is advanced by repeatedly incrementing for a period of three clocks and jumping once, and as shown in FIG. Each sample data is written.

The data written in the memory circuits 60, 61, and 62 are read out as shown in FIG. That is, if the number of samples in one horizontal section of a component color video signal is "," then time T indicates the section above the beginning of the data section. ~T
+J-, the sample data of the luminance signal Y is sequentially read out from the memory circuits 60, 61.
The sample data of the color difference signal R-Y is read out sequentially from 0.61.62, and the time T÷, ~T, which indicates the third - section, is read out sequentially.
In the interval j-1, sample data of the color difference signal B-Y is sequentially read out from the memory circuits 60, 61, and 62.

This reading is accomplished by advancing each address in the memory circuits 60, 61, and 62 as follows.

1. The memory circuit 60°61.6 shown in FIG.
The writing of data to 2 is proceeded by repeatedly incrementing the address for 3 clocks and jumping once, so by jumping the address of each memory circuit by 4, The same type of data is read. This reading can be realized by fixing the lower two bits of the address and advancing only the upper bits.

Therefore, time T as shown in FIG. In the interval ~T4g-, the lower two bits of the memory circuits 60, 61.62 are fixed to 0 and 1.2, respectively, and in the interval T1.~JT4j-, the lower two bits of the memory circuits 60, 61.62 are fixed to The -1: digit 2 bits of people are fixed at 2.0.1, respectively, and in the interval from time 1' to Tj-1, the lower 2 bits of each of the memory circuits 60, 61, and 62 are set to 1, 2, . fixed at 0,
The data shown in FIG. 6 is read by incrementing only the upper bits in accordance with the time.

The outputs read from the memory lj circuits 60, 61, and 62 are supplied to the selectors 63, 64.65, respectively, and the selectors 63, 64, 65 and the memory circuits 60, 61, and 62+
7) Mori 6 DA, 60B and 61A (constituting each)
, 61B, 62A, and 62B, the memory in the read state is selected, and this output is sent to registers 67, 68, and 62B.
9, each was served and had lunch. register 67.68
．． 69 is supplied with a latch pulse of frequency f from terminal 70, and the outputs of registers 67, 68, and 69 are sent to selector 7.
1.

A select signal is supplied to the selector 71 from a terminal 72, and each output of the registers 67, 68, and 69 is selected and outputted by the selector 71 for 17 periods each. The time T is set by the selector 71. -T+
In the section J-1, the output of register 61 is selected first, and then the output of register 68, register 69 . register 67,
Outputs are selected in the order of register 68, . . . , and at time T
In the interval yo.~JT+J-, the output of register 68 is selected first, and then the output of register 69. register 67, register 6
8. Register 69. The outputs are selected in the order of .
The output of register 67 is selected, and the output of register 6 is selected.
8. Register 69. Outputs are selected in the order of register 67, . . . .

The output of selector 71 is supplied to register 73. A latch pulse with a frequency of 3 fs is supplied to the register 73 from a terminal 74, and data from the register γ3 is taken out from an output terminal 75 as a time division multiplexed color video signal.

"Application example" This invention can be used as a component color video signal.
It can also be applied when primary color signals R, G, and B are used.

[Effects of the Invention] According to the present invention, for example, a component color video signal can be converted into a time division multiplexed color video signal by performing signal processing using a digital circuit.

However, in the present invention, it is sufficient that the memory, the selector on the input/output side of the memory, and the register before the input side selector operate at the input data sampling frequency fs. When performing time axis compression and multiplexing using 91 RAMs different from the present invention, the memory and peripheral circuits need to operate with a 6f5 clock.

Therefore, the present invention has the advantage that the operation is more stable than a configuration using one RAM, and problems such as mounting difficulties and high power consumption due to high-speed elements do not occur.

However, according to the present invention, the total memory capacity required can be minimized, and the memory can be easily controlled.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the specific configuration of a camera control system to which the present invention is applied, Fig. 2 is an overall block diagram of the camera control system, and Fig. 3 is used to explain this camera control system. Figure 4 is a waveform diagram, Figure 4 is a frequency spectrum diagram used to explain the camera controller) and roll stem, Figure 5 is a block diagram of an embodiment of this invention, Figures 6, 7, and 8 are diagrams of this invention. FIG. 2 is a route map used to explain one embodiment of the invention. 15 ・Multiplexer for time division multiplexing, 52.53,
54.6γ, 68, 69.73...Register, 56,57,58,63,64.6571...Selector, 60,61.62...Memory circuit. Agent Masato Sugiura

Claims (1)

[Claims] A circuit for converting n parallel digital input signals having the same sampling frequency into time-division multiplexed signals, each of which is time-compressed and linearly multiplexed, wherein n pairs of memories are provided, and each The pair of memories are controlled so that the writing state and the reading state are switched at a predetermined period, and when one is in the writing state, the other is in the reading state, and each of the n parallel digital input signals is sequentially inputted at each sampling period. The input is switched to one of the different memory pairs, and the data is read from the other of the n memory pairs at each sampling period and stored in the corresponding register, and the contents of this register are sequentially input within the sampling period. choose,
A digital signal conversion circuit configured to sequentially obtain each of the n input signals by time-compressing the information units of the predetermined period.