JPS60120619A - Pll circuit - Google Patents

Abstract

PURPOSE:To reduce steady phase errors by controlling the characteristics of an LPF so that the DC gain is set at a finite level in a non-locked mode of a PLL and then increased after the PLL is locked. CONSTITUTION:A phase comparator 1 compares a horizontal synchronizing signal H-SYNC with a pulse obtained by shifting a horizontal pulse PH obtained from a flyback transformer 4 is a TV receiver through a 90 deg. shifting circuit 5. The phase error output obtained from the comparison is applied to a VCO3 via a lead lag filter 2 in the form of the control voltage. Both the horizontal synchronizing signal and the horizontal pulse undergo the phase comparison through a multiplier 6. Then a lock/non-lock detecting circuit 7 detects a locked or non- locked state of a PLL loop. For the characteristics of the filter 2, the DC gain has a finite and incomplete integration form in a non-locked mode of the PLL loop and then changed to an infinite and complete integration form in a locked mode respectively. This attains a quick lock-in action and reduces steady phase errors in a locked mode of the PLL loop.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a PLL circuit, and is particularly applicable to APC circuits and APC circuits of video equipment.
This is suitable for use in FC circuits.

BACKGROUND ART AND PROBLEMS FIG. 1 is a graph showing the characteristics of a loop filter in a conventional general PLL circuit.
It has lag (lead/lag) characteristics. High pass region (
The advance region) is related to the synchronous pull-in (lock-in) characteristic,
The low-pass region (delay region) is related to the characteristics after locking. That is, if the loop gain is K, then the loop band is K and the loop noise band is (K(K+a) for the transient response.
))/(4(K+e)) (e is the roll-off frequency, a is the turnover frequency). Also, the steady phase error for the input frequency offset Δω is e/a・(Δω
)/K(e/a=A). Therefore, by reducing e/a=A, the steady phase error can be reduced. Note that if a is increased in order to reduce e/a, the above-mentioned loop noise band will be widened, so normally e is decreased to reduce the steady phase error.

Therefore, in general, as e→0 approaches, the steady path phase error becomes 0.
However, since the gain of the DC (direct current component) of the loop is theoretically infinite, the DC of the control input to the VCO is determined when it is locked, but when it is not locked, the DC of the loop It is influenced by unstable factors in the circuits that make up the circuit (changes in transistor VBB, etc.). This means that the free-running frequency of the VCO is not determined stably, and when the DC gain is infinite, the VCO
Although lock-in is possible in principle within the oscillation range of , it may be difficult to lock in if the free-running frequency f0 deviates significantly due to the DC offset of the circuit forming the loop. Furthermore, if a perfect integral characteristic is given to the loop filter in order to make the DC gain infinite, the high-frequency gain will be relatively reduced and the capture process will take a long time.

Therefore, in the loop filter of the conventional PLL circuit, it is necessary to reduce the steady phase error and to
This is contradictory to stabilizing the free-running frequency, so c and a in FIG. 1 are set to appropriate values to obtain a tolerance for both. In addition, if an acceptable point that satisfies both of the above cannot be obtained due to design conditions that take into consideration conditions that arise depending on the purpose of use of the PLL circuit, variations in constants and characteristics of circuit components, etc., the individual manufactured It becomes necessary to make adjustments to the PLL circuit.

Purpose of the Invention In view of the above-mentioned problems, the present invention has a simple structure that enables PL.
The steady phase error in the lock-in state of the L circuit can be extremely reduced, and the VC in the non-lock state can be
It is an object of the present invention to stably determine the free-running frequency of O without any adjustment without being affected by variations in constants or characteristics of circuit components.

Summary of the Invention The present invention provides characteristics of a low-pass filter that provides a phase error component to a VCO as a control voltage in a PLL circuit.
The DC gain is controlled to a finite value when LL is not locked, and the DC gain becomes extremely large after locking, depending on the locked state.

Example The present invention will be explained below based on examples.

FIG. 2 is a block diagram of an AFC circuit of a TV receiver showing an embodiment of the present invention. This AFC circuit has a PLL circuit configuration including a VCO, and its purpose is to generate an external horizontal synchronizing signal H-SYN as shown in FIGS. 3A and 3B.
Horizontal pulse PH obtained from the flyback transformer at C
The goal is to phase-synchronize the two. Note that FIG. 3A shows a case where the PLL is in an unlocked state, and FIG. 3B shows a case where the PLL is in a locked state.

In FIG. 2, an external horizontal synchronization signal H-SYNC,
The horizontal pulse PH obtained from the flyback transformer (4) in the TV receiver is compared with the pulse shifted by the 90° shift circuit (5) in the phase comparator (1), and the phase error output is passed through the lead-lag filter ( 2) as a control voltage to the VCO (3), and the horizontal oscillation within the receiver is phase-locked to the external horizontal synchronization signal.

Horizontal synchronization signal H-SYNC and flyback transformer (4
) is also applied to a multiplier (6) for phase comparison. While the horizontal scanning period is 63 μsec, the horizontal pulse PH is approximately 12 μsec, and the multiplication output is zero in the state shown in FIG. 3A, and exhibits a constant value in the state shown in FIG. 3B. The output of the multiplier (6) is sent to the lock/unlock detection circuit (7
), integrated here and then level discriminated, P
A locked or unlocked condition of the LL loop is detected.

The detection output is given to a lead-lag filter (2),
Filter characteristics are changed depending on lock/unlock. That is, in the unlocked state, the lead-lag filter (2) has an incomplete integral type with a finite DC gain, and in the locked state, it has a complete integral type with an infinite DC gain.

Figures 4A and 4B are block diagrams of the lead-lag filter (2), which when unlocked is composed of two stages of low-pass filters (8) and (9) with different time constants in tandem as shown in Figure 4A. . The front-stage filter (8) determines the high-frequency side characteristics, and the rear-stage filter (9) determines the low-frequency side (DC) characteristics. The transfer function is G(s)=1/(1+s1
)+1/(1+s1)・1/(1+s2)=(2+s2
)/(1+(s1+s2)+s1s2), and the fifth A
As shown in the frequency characteristic diagram in the figure, the DC gain is a finite value (2). For this reason, the free-running frequency of the VCO (3) in Figure 2 is stably determined regardless of variations in circuit constants, and the free-running frequency does not deviate significantly even if it is in the assembled state without adjustment, stably and quickly. lock in.

After lock-in, the low-pass filter (
9) is changed to the complete integral form. The transfer function is G(s)
=1/(1+s1)+1/(1+s1)・1/(s2)
Therefore, as shown in FIG. 5B, the DC gain becomes theoretically infinite. Therefore, the steady phase error in the locked state is theoretically zero.

FIG. 6 is a block diagram when the present invention is applied to an APC circuit. In FIG. 6, the chroma input is applied to a phase comparator (11) and is compared with the output of the VCO (13) in the burst portion. The phase difference output is a lead-lag filter (
12) and is given to the VCO (13) as a control voltage. The 3.581 MHz continuous wave output from the VCO (13) is given to the chroma demodulation circuit via the color phase adjustment circuit (14) and is derived as a color difference signal. In addition, the B-Y output of the chroma demodulation circuit (14) is connected to the color killer detection circuit (
16), and the presence or absence of the color burst signal is detected.

3.5 in the TV receiver based on this color killer detection.
The bandpass amplifier for the 8MHz band is turned on and off, but in this example, the color killer detection circuit (16) is turned on and off.
It is also used as a lock/unlock detection circuit for the LL loop. When unlocked, there is no color burst signal included in the B-Y output, and when locked, a color burst signal appears.

The output of the color killer detection circuit (16) is given as a switching signal to the lead-lag filter (12), and the filter characteristics are changed to incomplete integration type when unlocked and to complete integration type after locking.

FIG. 7 is a circuit diagram showing an example of the lead-lag filter (12) of FIG. 6. This filter (12) includes a first filter stage composed of a differential amplifier (18);
It is configured in cascade with a second filter stage consisting of a differential amplifier (19). The differential amplifier (18) is composed of transistors Q1 and Q2, a current source (20), and an active load (current source) (21), and has a predetermined time constant (
Forms a low-pass filter (4th A) on the wide area side)
(corresponds to filter (8) in the figure). Also, the differential amplifier (19
) consists of transistors Q3 and Q4, a current source (23), and an active load (24), and the emitter resistance of transistor Q4 and collector capacitor (25) form a low-pass filter that determines the time constant on the low frequency side. There is (4th A
(corresponds to filter (9) in the figure).

The output of the phase comparator (11) shown in FIG. It is derived from the base of Q4. Note that the outputs of the emitter follower transistors Q5 and Q6 are voltage-divided by resistors R1 and R2, and are negatively fed back to the differential amplifier (18) with an appropriate gain, thereby determining the gain of this filter stage.

The signal processed by the next stage filter is transmitted from the collector of transistor Q4 to emitter follower transistors Q7 and Q8.
, Q9 as the VCO control voltage. The signal at this output point is divided into appropriate values by resistors R3 and R4,
Negative feedback is provided to the differential amplifier (19) through the switching transistor Q10 and the resistor R, thereby controlling the DC gain of the filter output to a finite value when unlocked, as shown in FIG. 5A. Transistor Q13 is turned on by control current I from transistor Q11, and transistor Q11 outputs a lock/unlock detection output (sixth
In the figure, it is controlled by the color killer detection output). When unlocked, transistor Q11 is on and transistor Q10 is on.

When the PLL is locked, transistors Q10 and Q11 are turned off and the negative feedback path of the differential amplifier (19) is cut off, so the filter configured by the differential amplifier (19) is a fully integral type with infinite DC gain. becomes.

In addition, in FIG. 7, switches composed of transistors Q12 and Q13 are connected to the common emitters of the differential amplifiers (18) and (19) constituting each filter stage.
, Q13 is turned off, and the differential amplifier (18) (19)
is designed to operate as a filter. Outside the burst period, the burst flag pulse BF applied to the transistors Q12 and Q13 becomes low level, turning on these transistors Q12 and Q13, and transmitting current corresponding to the current sources (20) and (23) to each differential amplifier ( 18
) (19), so the differential amplifier (1
8) (19) is disabled. During this period of non-operation (2), each filter performs sample and hold to hold the previous value, which makes it possible to substantially increase the time constant of the filter.

Effects of the Invention As described above, the present invention changes the characteristics of the low-pass filter that applies the phase error component to the VCO as a control voltage, depending on the locked state of the PLL circuit, such that the DC gain is finite when it is not locked, and the DC gain is extremely large after it is locked. As a result, the steady state (residual) phase error in the lock-in state of the PLL circuit can be extremely reduced with a simple configuration, and the free-running frequency of the VCO in the non-lock state can be controlled Since the voltage DC gain is a finite value, it is stably determined without being affected by variations in constants or characteristics of circuit elements. Therefore, even if the circuit is assembled without adjustment, the VCO free-running frequency will not deviate significantly from the design point, and the performance of stably and quickly locking in to external signals can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a graph showing the frequency-gain characteristics of a conventional lead-lag filter incorporated in a PLL circuit. FIG. 2 is a block circuit diagram showing an embodiment in which the present invention is applied to an AFC circuit of a TV receiver. 3A and 3B are signal waveform diagrams of the unlocked state and locked state of FIG. 2, FIGS. 4A and 4B are block diagrams showing the characteristics of the lead-lag filter of FIG. 2, and FIGS. Fig. 5B is a graph showing the frequency-gain characteristics of the lead-lag filter shown in Fig. 2 when it is unlocked and when it is locked, and Fig. 6 is a block diagram showing another embodiment in which the present invention is applied to an APC circuit of a TV receiver. Circuit Diagram, FIG. 7 is a circuit diagram of the lead-lag filter of FIG. In addition, in the symbols used in the drawings, (1)................................... Phase comparator (2
)・・・・・・・・・・・・・・・Lead-lag filter (3)・・・・・・・・・・・・・・・VCO(4
)・・・・・・・・・・・・Flyback transformer (5)・・・・・・・・・・・・90° shift circuit (6)・・・・・・・・・・・・・・・Multiplier (7
)......This is a lock/unlock detection circuit.

Claims (1)

[Claims] The input signal and the signal based on the VCO oscillation output are phase-compared, and the phase error component is sent to the VCO through a low-pass filter.
In a PLL circuit that is applied as a control voltage, there is a detection circuit that detects the locked state of the PLL circuit, and the output of this detection circuit sets the DC gain to a finite value when it is not locked, and the DC gain becomes extremely large after locking. A PLL circuit comprising the above-mentioned low-pass filter controlled to