JPS60119483A - Detection signal indicator - Google Patents

Abstract

PURPOSE:To prevent the occurrence of missing of picture elements by storing signals of maximum level out of received signals to be written in each orthogonal coordinate address. CONSTITUTION:Signals received by an antenna 1 are written in a memory 4 through an amplifier detector circuit 2 and an A/D conversion circuit 3. Writing in the memory 4 is performed basing on an azimuth counter 5, a distance counter 6 and a coordinate conversion circuit 7. A circuit that includes a delay circuit 16, monostable multivibrator 17, AND gates 18, 19, latch 20, comparator circuit 21 and an OR gate 22 compares the signal of the last time with a signal of this time, and takes steps to write larger signal in the memory 4. The content of memory of the memory 4 is read out by the clock pulse from a clock pulse generating circuit 10, and supplied to an indicator 25 through a latch 26.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that once converts a detection signal received in a polar coordinate system, such as a radar or scanner, into orthogonal coordinates, stores the signal, and then displays the signal on a rask scanning display.

In recent years, Rask scanning type radars and scanners have been widely used to express character signals appropriately in the display to improve the recognition of detection signals, and to facilitate the colorization of signals. Geometrically, the signal is necessarily dense near the center 4=1, and becomes sparse towards the periphery, so in dense areas, the same location in the storage means is specified many times, which makes it difficult to process the signal properly. Undesirable. That is, since the same address is specified for multiple receptions, the contents of the address are always determined only by the state of the signal at the time of the last write.

The present invention was made in order to eliminate such inconveniences, and the signal memory that stores detection signals for one screen is kept in a normal reading state, and writing is performed at each orthogonal coordinate address (x, y).
This is executed only at the timing of the polar coordinate address (r, 0) when first specifying the polar coordinate address (r, 0) and the timing when a predetermined detection signal is obtained, to prevent so-called missing pixels, where the signal is not displayed even though the signal is present. A detection signal display device is provided.

The present invention basically consists of the following blocks. That is, (1) A block for converting the received signal from polar coordinates to rectangular coordinates and writing it to the specified address for one screen.

(2) A block that stores address information for first specifying each orthogonal coordinate address among the JZ polar coordinate addresses, and extracts the specification timing from this.

(3) A program that provides at least two periods within one distance section of the polar coordinate address.

(4) A block that compares the magnitude of the previous and current signals and performs update writing during the 2nd period of IZ.

(5) A block that reads and displays the stored contents on the display.

It consists of a total of five blocks, and especially blocks (3) and (4) are the main part of the present invention.

Each block will be explained below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a radar.

Regarding the block (1), (2) is an antenna that transmits and receives radio wave pulses, and transmission and reception are repeated at a constant period based on a transmission trigger means (not shown). The received signal is written into a signal memory 4 after passing through an amplification/detection circuit 2 and an A/D conversion circuit 3. The signal memory 4 is a RAM having address capacity for one screen, for example, n (rows) x n (columns), in which addresses are specified using orthogonal coordinates.

The detection signal is written in the signal memory 4 in orthogonal coordinates based on the azimuth counter 5, the distance counter 6, and the coordinate conversion circuit 7. That is, the azimuth counter 5 receives the bow pulse from the antenna 1 (or the 0° azimuth pulse after adding the azimuth data from the compass in the case of north-up display) and a fixed angle, for example 0.1' (which is sent to The angle data from the reference direction (bow or due north) is sent out based on the rotation pulse, and the distance counter 6 counts from 1 to a predetermined value at the sampling period of the A-D conversion circuit 3. Polar coordinate addresses (r, θ) of the distance counter 6 and direction counter 5
is guided to the coordinate conversion circuit 7 and converted into a rectangular coordinate address (x, y
) and output.

Then, these values (x, y) are sent to the signal memory 4 via the switching circuit 8, and as a result, the received signal is written to the address specified by the orthogonal coordinates.

Regarding the block (2), 9 is a ROM having the address capacity of the polar coordinate address (r, 0) specified by the direction counter 5 and the distance counter 6, and the stored contents are, for example, 1 at the corresponding address and 1 at the other addresses. O is written in advance.

2. The address in which 1 and O are written in the ROM will be explained with reference to FIG. Figure 2 shows the polar coordinate address (r,
θ) and orthogonal coordinate addresses (x, y), where r is r, r2, r3... and θ is...
...changes to k-1, to +1, etc. (
The antenna 1 is rotated in the direction of the arrow), and the polar coordinate address (r + θ) corresponding to the own ship position O is from the same figure (
r4, k), (+1 to r4.), (+2 to r3.
), (+2 to r 4.), a total of four. The polar coordinate address that first specifies the address is (r4, k) (indicated by φ mark in the figure), and ROM9 (7) (r4, k
) is written with the value 1 as the corresponding address. Similarly, the value l is written to the polar coordinate address that first specifies each of all the orthogonal coordinate addresses of geometry 1. As a result,
The read output 1 from the ROM 9 indicates the timing at which each orthogonal coordinate address is first specified.

Regarding block (3), IO is a clock pulse generation circuit that sends out basic pulses,
11 is a counter that counts the reference pulses. The output count value of the counter 11 is led to one input terminal of the comparison circuit 12, while a predetermined value, which will be described later, from the range signal generation circuit 13 is guided to the other input terminal, so that the count value of the counter 11 is "2". A coincidence pulse is sent when a predetermined value is reached. Note that the comparator circuit 11 includes, for example, a monostable multi-channel circuit, and is configured to hold a matching pulse for one cycle of the clock pulse. The coincidence pulse functions as a sampling clock for the A/D conversion circuit 3, a counting clock for the distance counter 6, and a reset pulse for the counter 11. The range signal generating circuit 13 outputs, for example, a value of 2 in the shortest distance range, and thereafter changes in conjunction with range switching so as to output a value compared to the detection range. Therefore, when the detection range is switched to, for example, twice, the matching Hals transmission period of the comparator circuit 12 is doubled in proportion, so that the sampling and counting operations of the distance counter 6 are also performed at twice the period. As a result, the number of samples to be sampled is always the same in each detection range. Reference numeral 14 denotes an adder circuit that adds the value 1 to the output count value of counter 1, and this adder circuit is sent to comparator circuit 15. The comparator circuit 15 is configured to send out a matching pulse every time the input value matches O. In this way, the two periods mentioned above are formed by the coincidence pulses from comparator circuit 12 and comparator circuit 15.

Regarding this point, if we explain with reference to the waveform diagram in Fig. 3,
Assuming that the detection range is now set to twice the shortest range, the range signal generation circuit 13 outputs a value of 4. Then, in synchronization with the coincidence pulse from the comparator circuit 12, the distance counter 6 calculates the counted values, for example, as shown in FIG.
, corresponding to S+r6). Also, the coincidence pulse from the comparator circuit 12 is sent at the beginning of each distance section (second
Figure e), the coincidence pulse from the comparator circuit 15 is at the end (
Figure 2 f) Appears.

Update writing to prevent pixel omission for the block (4) involves comparing the (+) previous stored contents with the current received signal and writing later, but this alone is not sufficient. That is, when the (ti) orthogonal coordinate address is specified for the first time, it is also necessary to update the past memory contents (one rotation of the antenna 1). Note that the previous signal refers to the signal most recently written to the address.

First, case (i) will be explained. However, in this case, since there is a period in which the magnitudes of the previous and current signals are compared and a period in which update writing is performed based on the result, the magnitude comparison operation will be explained first. As a circuit for this purpose, a delay circuit 16,
Monostable multi 17, AND game) 1B, 19, latch 2
0, a comparison circuit 21 and an OR gate 22 are newly used.

Clock pulse a(
3) is a delay circuit 1B, which delays the signal by, for example, 174 cycles, and then sends it to the monostable multi-channel 17. The monostable multi 1
7 operates at the timing of sending the delayed clock pulse and sends out a short pulse b (FIG. 3).

Now, the coincidence pulse e appearing at the beginning of each distance section and the rag pulse b are sent to an AND gate 18, which sends out a pulse g. This pulse g is used for the latch operation of the latch 20. That is, the latch 20 latches the previous signal read from the signal memory 4 every time the pulse g is sent. As will be described later, writing to the signal memory 4 is always performed only in the last period of each distance section by the coincidence pulse f, so the signal memory 4 is in the read state at the time of sending out the pulse g, and moreover, when the clock pulse a is high, the signal memory 4 is in the read state. Since the level period is sent to the switching circuit 8, the write address from the coordinate conversion circuit 7 is guided to the signal memory 4. As a result, the contents of the latch 20 become the storage signal at the corresponding address.

The comparison circuit 21 has an input terminal A connected to the A-D conversion circuit 3 and an input terminal connected to the latch 20, and sends out a comparison pulse only when the level of the signal sent to the input terminal A is higher. It is done like this. For example, r= in FIG.
A comparison pulse j is sent out as in case 6.

The comparison pulse j is fed into an AND gate 19. AN
The D gate 19 is in a waiting state in the last period of each distance section due to the input of the coincidence pulse f and the rag pulse b, and the pulse k is output due to the input of the comparison pulse j, which is sent to the signal memory via the OR gate 22. It is guided to the write/read control terminal No. 4. As a result, the signal memory 4 is put into a write state during that time and writes the signal sent from the A-D conversion circuit 3 obtained this time. Conversely, as in the case of r=5, that is, when the level of the signal sent to input terminal A is low or equal, the comparison pulse j is not sent out and the signal memory 4 maintains the read state, so that the previous stored signal will continue to be retained without being updated.

Next, case (i) will be explained. An AND gate 23 is newly used as a circuit for this purpose.

The match pulse f from the comparator circuit 15 and the rag pulse b are sent to the AND gate 23, and both pulses f and b keep the gate waiting state at all times during the last period of each distance section. That is, the distance counter 6 is now r=4(
If the month corresponds to r, and θ= , then ROM
A high level pulse h (Fig. 3) with a value of 1 is sent from 9 to 1.
As a result, a pulse i (FIG. 3) is sent out from the AND gate 23. After passing through the OR gate 22, this pulse i is led to the read/write control terminal of the signal memory 4. And”-
When the write/read control terminal is maintained at a high level by the pulse i, the signal memory 4 is put into a write state, and the signal obtained this time is updated and written in place of the past stored contents.

Regarding the block (5), the memory contents of the signal memory 4 are the clock pulse generation circuit lO
The readout address formed by the readout display control means based on the clock pulse a from the memory is led to the signal memory 4 via the switching circuit 8 and read out. The above read timing is obtained by switching the switching circuit 8 to the read side during the period when the clock pulse a is at a low level. By the way, in addition to the signals read out from the signal memory 4, there are also signals read out at the write address for the latch 20 as described above, so in order not to transfer these to the display 25 side, for example, A latch 28 is utilized. That is, by inverting the clock pulse delayed by the delay circuit 16 by the inverter 27 and sending it to the monostable multi 28,
A short l] pulse C whose phase is shifted by π from the aforementioned short l] pulse b.
(Fig. 3), and by latching at the timing of this pulse C, only the signal specified by the readout address and read out will be guided to the display 25 after passing through the A-to-reverse conversion means (not shown). .

Raster scanning of the display 25 is performed by a scanning signal generated by the readout display control means in synchronization with the readout address based on the clock pulse a.

As explained below, according to the present invention, the maximum level of the received signals to be written is stored at each orthogonal coordinate address, so that the reception signal when finally designated as in the conventional method is stored. The storage contents of the address are determined depending on the state of the signal, and the problem of missing pixels due to this does not occur.

In addition, due to the function of the ROM 9, the past signal from one revolution before the antenna is always updated to the current first received signal regardless of its level, so for example, if the past stored content was the maximum level signal, the signal Since the comparison pulse j is not sent out only by update writing based on level comparison, there is no problem that this maximum level signal remains forever.

In this embodiment, the comparator circuit 21 is used to capture the highest level signal among the signals specifying the same address into the display memory 4, but the signal is written only when the signal is present. Even with such a configuration, the intended purpose of the present invention can be achieved. In this case, latch 20, AND game) 18
and comparison circuit 20 are no longer necessary, and in their place, A-
Only when the output of the D conversion circuit 3 exists, it is sufficient to energize the pulse generating means (not shown) that leads the pulse output to the AND game (AND game) 19. The signal will be captured.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a geometric diagram showing the correspondence between orthogonal coordinate addresses and polar coordinate addresses to explain the storage state of the ROM 9. FIG. 3 is a waveform diagram. Patent applicant Furuno Electric Co., Ltd. A (:, Q-, R-)

Claims (3)

[Claims] (1) In a detection signal display device that converts a detection signal from polar coordinates to rectangular coordinates and once writes it into a memory for one screen designated by an address, reads it out sequentially and displays it once on a rask scanning display, a signal sending means for sending out an output signal when a predetermined detection signal is obtained; a first write control means for putting the memory into a writing state by the output of the signal sending means; a timing signal sending means having address information for first specifying a coordinate address and sending out an output at the timing when the polar coordinate address is obtained; 2. A detection signal display device comprising: 2 writing control means. (2) The detection signal display device according to claim 1, wherein the predetermined detection signal for operating the signal sending means is simply a detection signal. (3) Detection according to claim 1, characterized in that the predetermined detection signal for operating the signal sending means is a signal with a higher level of the previous stored content and the current detection signal. Signal display device.