JPS6011915A - Back-up circuit of memory - Google Patents

Abstract

PURPOSE:To suppress a rush current by connecting a resistance in series to a capacitor which functions as a back-up power supply. CONSTITUTION:A main power supply line 1 and an auxiliary power supply line 2 are connected to a power supply bus bar l1 via a transistor 4 and a reverse current preventing diode 5 respectively. A power supply back-up capacitor 3 is connected to the bar l1 to supply the electric power to a nonvolatile memory A in a service interruption mode. In this case, a resistance 8 is connected in series to the capacitor 3. Thus the current flowing to the capacitor 3 through a diode 7 is suppressed by the resistance 8 when the power supply is applied. Furthermore the voltage (b) of the bar l1 is instantaneously fixed with a voltage drop due to the resistance 8. The the memory A is immediately actuated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory backup circuit in which a capacitor is connected between the power supply terminals of the memory so as to act as a backup power source for the volatile memory for a short period of time immediately after shutdown. It is something.

[Technical drawbacks of the invention and its problems]

In a]IA-resistance systems that control various plants by applying microcomputers.

Parameters and the like for optimally controlling the plan If υ1 are generally stored in a volatile memory (random access memory) and are constantly rewritten to the optimum values. Therefore, industrial computers etc.
In particular, in order to perform correct control after a power outage, it is necessary to protect the RAM during a power outage.

FIG. 1 shows a conventional RAM backup circuit in the event of a power outage. In Figure 1, A is Makoto.

The power terminal is the power bus 1. ,l,.

1 is a main power line; 2 is an auxiliary power line; 3 is a capacitor connected between the power bus lines 11t and 12; the main power line 1 is connected to the power bus l through a transistor 4; The auxiliary load line 2 is connected to the power supply bus 11 via a current blocking diode 5. Reference numeral 6 denotes a circuit for detecting a stoppage of the main power line 1, and its pressure is supplied from the bus 1+.

In addition, as auxiliary electrolytic corrosion, a highly reliable power source, battery,
A battery or the like is used. Further, a diode 7 is connected in parallel to the transistor 4.

In the above power supply circuit, power is normally supplied from the main power supply input 1 to the power supply bus 11 through all the transistors 4. At this time, diode 5 is in a cutoff state.

If the main power supply fails, immediately after that, the RAM
1 due to the charging voltage of capacitor 3 since the current consumption of A is small. The power supply voltage of A A is maintained and then the auxiliary power line 2 (= switched. At this time, the power failure detection circuit 6 (2) detects the loss of heavy pressure in the main power line 1, and the main power is stopped. It is confirmed.

In this way, the power supply backup for the RAM is performed, but since the capacitor a is connected between the mold warm bus 11r and tJ2, the power supply line voltage increases as shown in Fig. 2 when the power is turned on.
Even if the voltage rises instantaneously as shown in a), an inrush current flows through the diodes 7 as shown in Figure 2 (C), and the voltage on the power supply bus 11 gradually rises (= rises) as shown in Figure 2 (C). As a result, a waiting time is required for memory operation.

[Object of the Invention] An object of the present invention is to provide an entire memory backup circuit that can put the memo 9'x into the operating state at the same time as the power is turned on, and can suppress rush current.

[Summary of the invention]

In the present invention, all resistors are connected in a row in a row to a capacitor that acts as a backup K YJJA during a power outage, thereby quickly establishing the terminal voltage of the memory when the power is turned on, and also suppressing the 95% current input θ. In the circuit.

[Practice of the invention]

FIG. 3 shows an embodiment of the present invention, where A is RAll
vl, 11. It is the power bus line, 1 is the main power line, 2 is the auxiliary power line, and 91t is the capacitor.

4 is a transistor, 5 and 7 are diodes, and 6 is a power failure detection circuit, and their connection relationship is the same as that of the conventional device (FIG. 1).

In this embodiment, C, a resistor 8 is connected in series with the nIj capacitor 3.
are connected. That is, the entire series circuit of the capacitor 3 and the resistor 8 is connected between the source bus 11 and llt.

With such a circuit configuration, the current flowing to the capacitor 3 through the diode 7 when the power is turned on is limited by the resistor 8, resulting in a suppressed rush current as shown in FIG. (= means that the charging current flows through the resistor 8 and a voltage drop occurs, so the power supply bus 7
1 voltage is established instantaneously as shown in Figure 4(b), and R
AMA becomes operational immediately.

〔Effect of the invention〕

As described above, according to the present invention, since the resistor is connected in series with the capacitor, the memory power supply voltage is established at the same time as the power is turned on, and Memo 9 (RAbl) enters the operating state. It is no longer necessary to completely access the RAM for several mIIeC (i-). This is very effective in various controllers using microcomputers, particularly high-speed controllers.

Furthermore, since the inrush current is limited, there are advantages such as preventing damage to elements such as diodes and extending their lifespan.

4. Simple explanation of 1% 1 plane't, 1° Figure 1 is a circuit diagram showing a conventional example of a memory backup kl path, 2nd seat 1 (aJ (bJ (c, J are the voltages of the same column Tsuquag circuit, Current waveform diagram, circuit diagram showing one embodiment of the 3rd ward lid Honjim Akira, Figure 4 (nl (bl jin 1.
This is a waveform diagram for explaining the operation of the same implementation.

A...RAM-j2. and 12...RAM tunlin mating,
1... Main power line, 2... Kyusuke? Ii source line,
3...Connley, 8...Resistance.

Figure 1: Patent attorney Suzu T.L. Figure 2 (C) -11, /'-1 Figure 3 f et al. Figure 4 (b) -1''-1111

Claims (1)

[Claims] A series circuit of a capacitor and a resistor for power backup is fully connected between the power supply terminals of volatile memory in a computer system. Characteristic memory backup circuit.