JPS60117979A - Picture signal transmission system - Google Patents
Picture signal transmission systemInfo
- Publication number
- JPS60117979A JPS60117979A JP22608883A JP22608883A JPS60117979A JP S60117979 A JPS60117979 A JP S60117979A JP 22608883 A JP22608883 A JP 22608883A JP 22608883 A JP22608883 A JP 22608883A JP S60117979 A JPS60117979 A JP S60117979A
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- terminal
- circuit
- vertical synchronizing
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
(al 発明の技術分野
本発明は画像信号伝送方式に係り、特に画像にスクラン
ブルをかけ充分な秘密性を持たせる様にした画像伝送方
式に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an image signal transmission system, and more particularly to an image transmission system in which images are scrambled to provide sufficient secrecy.
(b) 従来技術と問題点
従来、画像信号に対して無線装置の送信側で乱れを作り
秘密通信する様な手段は種々検討され実用化されつつあ
る。(b) Prior Art and Problems Conventionally, various means have been studied and put into practical use for creating a disturbance in the image signal on the transmitting side of a wireless device for secret communication.
その一つはベースバンドの画像信号に複数個の正弦波を
妨害波として立てる事であって受信側ではこの妨害を簡
単に除去できる。One of them is to generate a plurality of sine waves as interference waves in the baseband image signal, and this interference can be easily removed on the receiving side.
しかし、第三者が周波数分析器等を使用すると妨害波の
周波数が容易に検知できるから、それを除去して原画像
を取り出すことが容易にできると云う問題があった。However, there is a problem in that if a third party uses a frequency analyzer or the like, the frequency of the interference wave can be easily detected and the original image can be easily removed by removing it.
(C) 発明の目的
本発明は上記従来技術の問題に鑑みなされたものであっ
て、画像信号よりある時間差の変化量を伝送する方式に
於て、この時間差を任意に制御する事により容易に原画
像信号を取り出すことのできない画像伝送方式を提供す
ることを目的とする。(C) Purpose of the Invention The present invention has been made in view of the above-mentioned problems of the prior art.In a method of transmitting a change amount of a certain time difference from an image signal, it is possible to easily control the time difference by arbitrarily controlling it. It is an object of the present invention to provide an image transmission method in which the original image signal cannot be extracted.
(dl 発明の構成
上記発明の目的は画像信号を2分し第1の部分の画像信
号と遅延回路を通った残りの部分の画像信号の差分を伝
送する画像信号伝送方式に於て、送信側では該遅延回路
の遅延時間を制御すると共に該制御の基準を示すタイミ
ング情報を伝送し、受信側では受信信号と検出した該タ
イミング情報を用いて該遅延回路の遅延時間と同一にな
る様に制御された受信遅延回路を通過した受信信号との
和を取ることにより該受信信号より画像信号を取り出す
ことを特徴とする画像信号伝送方式を提供する事により
達成される。(dl Structure of the Invention The object of the invention is to divide an image signal into two and transmit the difference between the first part of the image signal and the remaining part of the image signal that has passed through a delay circuit. Then, the delay time of the delay circuit is controlled and timing information indicating the control standard is transmitted, and the receiving side uses the received signal and the detected timing information to control the delay time to be the same as the delay time of the delay circuit. This is achieved by providing an image signal transmission system characterized in that an image signal is extracted from the received signal by calculating the sum of the received signal that has passed through the received signal and the received signal that has passed through the received delay circuit.
(e) 発明の実施例
第1図は本発明を実施する為のブロック接続図の一例で
、第1図(a)は送信側スクランブル回路を第1図(b
lは受信側デスクランブル回路をそれぞれ示す。(e) Embodiment of the invention FIG. 1 is an example of a block connection diagram for carrying out the present invention, and FIG. 1(a) shows the transmitting side scramble circuit.
1 indicates a descrambling circuit on the receiving side.
図中、1及び7は水平垂直同期信号検出部を、2及び8
は遅延時間制御部を、3及び10は可変遅延回路を、4
は差動増幅部を、9はハイブリッド回路を、12はビデ
オ増幅部を、11は高域ろ波器を、5.6.13及び1
4はそれぞれ端子を示す。In the figure, 1 and 7 are horizontal and vertical synchronization signal detection units, and 2 and 8 are horizontal and vertical synchronization signal detection units.
3 and 10 are variable delay circuits; 4 is a delay time control section; 3 and 10 are variable delay circuits;
9 is a differential amplifier section, 9 is a hybrid circuit, 12 is a video amplifier section, 11 is a high-pass filter, 5.6.13 and 1
4 each indicate a terminal.
これら各要素は次の様に接続されている。These elements are connected as follows.
先ず第1図talに於て、可変遅延回路3の端子(11
は差動増幅部4を介して端子6と、端子(2)は遅延時
間制御部2及び水平垂直同期信号検出部1を介して端子
5と、端子(3)は差動増幅部4の別の端子及び端子5
とそれぞれ接続される。First, in FIG. 1, the terminal (11) of the variable delay circuit 3 is
is connected to terminal 6 via differential amplifier section 4, terminal (2) is connected to terminal 5 via delay time control section 2 and horizontal/vertical synchronization signal detection section 1, and terminal (3) is connected to another terminal of differential amplifier section 4. terminal and terminal 5
are connected to each other.
第1図(blに於て、可変遅延回路10の端子(1)は
/’%イブリッド回路9及びビデオ増幅器12を介して
端子14と、端子(2)は高域ろ波器11を介して端子
14と、端子(3)は遅延時間制御部8及び水平垂直同
期信号検出部7を介して端子13及びハイブリッド回路
9の別の端子にそれぞれ接続される。In FIG. 1 (bl), the terminal (1) of the variable delay circuit 10 is connected to the terminal 14 via the hybrid circuit 9 and the video amplifier 12, and the terminal (2) is connected to the terminal 14 via the high-pass filter 11. Terminal 14 and terminal (3) are connected to terminal 13 and another terminal of hybrid circuit 9 via delay time control section 8 and horizontal/vertical synchronization signal detection section 7, respectively.
第2図(a)及び第2図(blはそれぞれ第1図(a)
及び第1図(b)の動作を説明する為の図で、これを参
照しながら先ず第1図(alの動作を説明する。Figure 2 (a) and Figure 2 (bl are respectively Figure 1 (a)
This is a diagram for explaining the operation of FIG. 1(b), and the operation of FIG.
尚、第2図の左側の数字は第1図の同じ数字の部分の波
形を示す。Note that the numbers on the left side of FIG. 2 indicate the waveforms of the portions with the same numbers in FIG.
入力端子5に加えられた画像信号(音声信号の有無に無
関係)は2つに分割され1部は直接差動増幅部4に、残
りは水平垂直同期信号検出部1に加えられる(第2図T
a)−■)。The image signal applied to the input terminal 5 (irrespective of the presence or absence of an audio signal) is divided into two parts, one part is directly applied to the differential amplification section 4, and the rest is applied to the horizontal and vertical synchronization signal detection section 1 (see Fig. 2). T
a)-■).
水平垂直同期信号検出部1では公知の方法でこの画像信
号から水平同期信号と垂直同期信号を検出する。これら
の2つの同期信号は遅延時間制御部2に入力されるが、
これは検出した水平同期信号及び垂直同期信号を基準タ
イミングとして用いる為である。尚、基準タイミングは
水平及び垂直同期−信号を使用せずに外部のものを利用
する事もできる。A horizontal/vertical synchronizing signal detection section 1 detects a horizontal synchronizing signal and a vertical synchronizing signal from this image signal using a known method. These two synchronization signals are input to the delay time control section 2,
This is to use the detected horizontal synchronization signal and vertical synchronization signal as reference timing. Incidentally, the reference timing can also be externally used without using the horizontal and vertical synchronization signals.
遅延時間制御回路2では入力された水平同期信号が垂直
同期信号を基準にして何番目のものかを検出する。一方
、それぞれの水平同期信号に対応して可変遅延回路3の
遅延量が予め決められ、この対応表が例えば記憶装置(
図示せず)に入っている。そこで、遅延時間制御部2は
入力された水平同期信号に対応する遅延時間を記憶装置
から読出し、定められた遅延時間になる様に可変遅延回
路3を制御する。The delay time control circuit 2 detects the number of the input horizontal synchronizing signal with respect to the vertical synchronizing signal. On the other hand, the delay amount of the variable delay circuit 3 is determined in advance corresponding to each horizontal synchronization signal, and this correspondence table is stored in a storage device (
(not shown). Therefore, the delay time control section 2 reads the delay time corresponding to the input horizontal synchronizing signal from the storage device, and controls the variable delay circuit 3 so that the predetermined delay time is achieved.
そこで、端子5に入力された画像信号の残りの部分は可
変遅延回路3で前記の時間だけ遅延を受け差動増幅部4
の別の端子に入力される(第2図+8)−〇)。Therefore, the remaining part of the image signal input to the terminal 5 is delayed by the above-mentioned time in the variable delay circuit 3, and is then delayed by the differential amplifier 4.
is input to another terminal (Figure 2 +8)-〇).
ここで直接入力された画像信号と遅延された画像信号は
差を取られてスクランブルされ端子6から出力される(
第2図Ta)−■)。Here, the difference between the directly input image signal and the delayed image signal is taken, scrambled, and output from terminal 6 (
Figure 2 Ta)-■).
次に受信側では、端子13に入力された受信信号(第2
図(b)−〇)は2つに分割され一部は直接ハイブリッ
ド回路9を通ってビデオ増幅器12に入力される。ここ
で増幅された出力の一部は高域ろ波器11を通って可変
遅延回路10に入力される。Next, on the receiving side, the received signal (second
The signal shown in (b)-◯) is divided into two parts, and one part is directly input to the video amplifier 12 through the hybrid circuit 9. A part of the amplified output passes through a high-pass filter 11 and is input to a variable delay circuit 10.
一方、入力された受信信号の残りは水平垂直同期信号検
出部7で水平同期信号及び垂直同期信号が検出され、こ
の2つの同期信号を用いて送信側の遅延時間制御部2が
行ったのと全く同じ制御を可変遅延回路10に対して行
う。On the other hand, the horizontal and vertical synchronization signal detection section 7 detects the horizontal synchronization signal and the vertical synchronization signal from the rest of the input received signal, and uses these two synchronization signals to perform the processing performed by the delay time control section 2 on the transmitting side. Exactly the same control is performed on the variable delay circuit 10.
従って、同一の水平同期信号に対して2つの可変遅延回
路は全く同じ遅延時間を持つ事になる。Therefore, the two variable delay circuits have exactly the same delay time for the same horizontal synchronizing signal.
この様に制御された可変遅延回路10を通った受信信号
はハイプリント回路9で前記の受信信号と加算されるの
で、スクランブルされた受信信号はデスクランブルされ
元の画像信号が取り出せる(第2図(bl−■)。The received signal that has passed through the variable delay circuit 10 controlled in this way is added to the above-mentioned received signal in the high print circuit 9, so that the scrambled received signal is descrambled and the original image signal can be extracted (see Figure 2). (bl-■).
第3図Ta)は水平垂直同期信号検出部の構成例を示す
図で、15.18及び19はコンパレータを、16は積
分回路を、17は微分回路をそれぞれ示す。FIG. 3 Ta) is a diagram showing an example of the configuration of a horizontal/vertical synchronizing signal detection section, in which 15, 18 and 19 are comparators, 16 is an integrating circuit, and 17 is a differentiating circuit.
第3図(blは第3図(alの動作を説明する為の図で
、左側の数字は第3図(a)の中の同じ数字の部分の波
形を示す。FIG. 3 (bl is a diagram for explaining the operation of FIG. 3 (al), and the numbers on the left side indicate the waveforms of the portions with the same numbers in FIG. 3(a).
第3図(alに示した水平垂直同期信号検出部は第3図
(b)に示す様な動作をして端子35に入力した画像信
号から水平同期信号及び垂直同期信号を取出し、端子3
6から垂直同期信号を、端子37から水平同期信号を出
力し第5図の端子54及び53にそれぞれ加える。The horizontal/vertical synchronizing signal detection section shown in FIG. 3(al) operates as shown in FIG.
A vertical synchronizing signal is output from terminal 6, and a horizontal synchronizing signal is output from terminal 37, which are applied to terminals 54 and 53 in FIG. 5, respectively.
第4図は可変遅延回路の構成例を示す図で20〜24は
線輪を、30〜34は可変容量ダイオードを、35は抵
抗器を、40は入力端子を、41は出力端子を、42は
制御用バイアス端子をそれぞれ示す。FIG. 4 is a diagram showing an example of the configuration of a variable delay circuit, in which 20 to 24 are coils, 30 to 34 are variable capacitance diodes, 35 is a resistor, 40 is an input terminal, 41 is an output terminal, and 42 is a resistor. indicate control bias terminals, respectively.
同図に於て、遅延時間制御部8から端子42に加えられ
る直流制御電圧により可変容量ダイオード30〜34の
容量値を制御して端子40と41の間の線路の遅延時間
を所要の値にする。In the figure, the capacitance values of the variable capacitance diodes 30 to 34 are controlled by the DC control voltage applied from the delay time control section 8 to the terminal 42, and the delay time of the line between the terminals 40 and 41 is set to a required value. do.
第4図に示した遅延回路の遅延時間τは次の式よりめる
事ができる。The delay time τ of the delay circuit shown in FIG. 4 can be calculated from the following equation.
τ−(1−(1/nテ・ (ω/ωd〕/ここで、L−
C=1/ω、を、M−C=1/ω二を、ωa−(1/n
) ・ωbを、Lは線輪のインダクタンスを、Cはコン
デンサの容量値を、Mは線輪の相互インダクタンスをそ
れぞれ示す。τ-(1-(1/nte・(ω/ωd))/Here, L-
C=1/ω, MC=1/ω2, ωa-(1/n
) ・ωb, L indicates the inductance of the coil, C indicates the capacitance value of the capacitor, and M indicates the mutual inductance of the coil.
第5図は遅延時間制御部の構成例を示ず図で、50はカ
ウンタを、51はコード変換器を、52はディジタル/
アナログ変換器をそれぞれ示す。FIG. 5 is a diagram without showing an example of the configuration of the delay time control section, in which 50 is a counter, 51 is a code converter, and 52 is a digital/digital converter.
Each analog converter is shown.
同図に於て、カウンタ50は端子53から入力される水
平同期信号の数をカウントし、端子54から入力される
垂直同期信号でカウンタ50はリセットされる。In the figure, a counter 50 counts the number of horizontal synchronizing signals inputted from a terminal 53, and is reset by a vertical synchronizing signal inputted from a terminal 54.
カウンタ50からの出力が入力されたコード変換器51
は、入力されたデータに対応する予め設定されディジタ
ル化された遅延量を例えば記憶装置(図示せず)から読
み出して来て、これをディジタル/アナログ変換器52
でアナログ量に変換し端子55からそれを出力し第4図
の端子42に加える。Code converter 51 to which the output from the counter 50 is input
reads out a preset and digitized delay amount corresponding to the input data from, for example, a storage device (not shown) and converts it into a digital/analog converter 52.
It converts it into an analog quantity, outputs it from terminal 55, and adds it to terminal 42 in FIG.
(f) 発明の詳細
な説明した様に、本発明によれば画像信号の差分を取り
差分の時間量を可変する事により画像信号にスクランブ
ルを掛ける。 −
この時間量は任意に設定し且つ時間によりその時間量を
変えるので画像信号の検出は難しくなり秘話性は充分に
保たれる。(f) As described in detail, according to the present invention, the image signal is scrambled by taking the difference between the image signals and varying the time amount of the difference. - Since the amount of time is set arbitrarily and the amount of time is changed depending on the time, detection of the image signal becomes difficult and confidentiality is sufficiently maintained.
第1図は本発明を実施する為の一例を、第2図は第1図
の動作を説明する為の図を、第3図は水平垂直同期信号
検出部の構成例及びそれの動作説明の為の°図を、第4
図は可変遅延回路の構成例を、第5図は遅延時間制御部
の構成例をそれぞれ示す。
同図に於て、1及び7は水平垂直同期信号検出部を、2
及び8は遅延時間制御部を、3及び10は可変遅延回路
を、4は差動増幅部を、9はハイブリッド回路を、11
は高域ろ波器を、12はビデオ増幅器をそれぞれ示す。
寥 3 図
(a)
■ −口側丁■−
答 4 図FIG. 1 shows an example for implementing the present invention, FIG. 2 is a diagram for explaining the operation of FIG. 1, and FIG. The diagram for the 4th
The figure shows an example of the configuration of the variable delay circuit, and FIG. 5 shows an example of the configuration of the delay time control section. In the figure, 1 and 7 are horizontal and vertical synchronization signal detection sections, 2
and 8 are delay time control sections, 3 and 10 are variable delay circuits, 4 is a differential amplifier section, 9 is a hybrid circuit, 11
12 indicates a high-pass filter, and 12 indicates a video amplifier.寥 3 Diagram (a) ■ -mouth side ■- Answer 4 Diagram
Claims (1)
った残りの部分の画像信号の差分を伝送する画像信号伝
送方式に於て、送信側では該遅延回路の遅延時間を制御
すると共に該制御の基準を示すタイミング情報を伝送し
、受信側では受信信号と検出した該タイミング情報を用
いて遅延時間が該遅延回路の遅延時間と同一になる様に
制御された受信遅延回路を通過した受信信号との和を取
ることにより該受信信号より画像信号を取出すことを特
徴とする画像信号伝送方式。In an image signal transmission method that divides an image signal into two and transmits the difference between the image signal of the first part and the image signal of the remaining part after passing through a delay circuit, the transmitting side controls the delay time of the delay circuit. At the same time, timing information indicating the control standard is transmitted, and on the receiving side, using the received signal and the detected timing information, a reception delay circuit is controlled so that the delay time is the same as the delay time of the delay circuit. An image signal transmission method characterized in that an image signal is extracted from the received signal by calculating the sum with the passed received signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22608883A JPS60117979A (en) | 1983-11-30 | 1983-11-30 | Picture signal transmission system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22608883A JPS60117979A (en) | 1983-11-30 | 1983-11-30 | Picture signal transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60117979A true JPS60117979A (en) | 1985-06-25 |
Family
ID=16839629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22608883A Pending JPS60117979A (en) | 1983-11-30 | 1983-11-30 | Picture signal transmission system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60117979A (en) |
-
1983
- 1983-11-30 JP JP22608883A patent/JPS60117979A/en active Pending
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