JPS60117919A - Pll system - Google Patents
Pll systemInfo
- Publication number
- JPS60117919A JPS60117919A JP58225686A JP22568683A JPS60117919A JP S60117919 A JPS60117919 A JP S60117919A JP 58225686 A JP58225686 A JP 58225686A JP 22568683 A JP22568683 A JP 22568683A JP S60117919 A JPS60117919 A JP S60117919A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- input
- counter
- frequencies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 1
- 101150060298 add2 gene Proteins 0.000 abstract description 5
- 230000001360 synchronised effect Effects 0.000 abstract description 3
- 101150005267 Add1 gene Proteins 0.000 abstract 1
- 101100490488 Mus musculus Add3 gene Proteins 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 102100034185 E3 ubiquitin-protein ligase RLIM Human genes 0.000 description 1
- 101000711924 Homo sapiens E3 ubiquitin-protein ligase RLIM Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
(aJ 発明の技術分野
本発明は伝送装置のクロックの周期引き込みに係り、特
に入力信号周波数とPLLの発振周波数とが異る場合の
PLL方式に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to the period acquisition of a clock of a transmission device, and particularly to a PLL system when the input signal frequency and the oscillation frequency of the PLL are different.
(b) 従来技術と問題点
従来、入力信号周波数f t (以下、人力周波数f1
と称す)と出力信号周波数ft(以下、出力周波数f!
と称す)とのクロックの最大公約数1里□にてPLL
1に構成している。ここで、f1t=fJN”fz/M
でl/N、l/Nは分周比を示す。(b) Conventional technology and problems Conventionally, input signal frequency f t (hereinafter referred to as human frequency f1
) and output signal frequency ft (hereinafter referred to as output frequency f!).
PLL at the greatest common divisor of the clocks, 1ri□
1. Here, f1t=fJN”fz/M
where l/N and l/N indicate the frequency division ratio.
以下、従来のPLL方式について、第1図1こ従って説
明する。図中、lはl/N分周器、2は1重M分周器、
3は位相比較器、4は低域通過1波器(以下、LPFと
称す)、5は電圧制御発振器(以下、■COと称すハf
1は人力周波数、f!は出力周波数を示す。The conventional PLL system will be explained below with reference to FIG. 1. In the figure, l is an l/N frequency divider, 2 is a single M frequency divider,
3 is a phase comparator, 4 is a low-pass single wave filter (hereinafter referred to as LPF), and 5 is a voltage controlled oscillator (hereinafter referred to as CO).
1 is the human power frequency, f! indicates the output frequency.
第1図において、入力周波数11はl/N分周器lにお
いてt/Nに分周さn1出力周波数f!は1重M分周器
2にて1重MEこ分周され、夫々の分周された周amは
位相比較器3にて比較され1その比較出力は1.PF4
を経てVC(35に人力され、入力周a数fIに引込ま
れた出力周波1lXftを出力する。In FIG. 1, the input frequency 11 is divided by t/N in the l/N frequency divider l and the output frequency f! is divided by a single ME frequency by a single M frequency divider 2, and each divided frequency am is compared by a phase comparator 3, and the comparison output is 1. PF4
It outputs an output frequency 11Xft which is manually input to the VC (35) and drawn into the input frequency a number fI.
上記において、分周比1/N、l/Mと周波数f、tf
8との間に次の関係がある。7t/N=7t/M=f■
・・・・・・・・・最大公約数。In the above, the frequency division ratio 1/N, l/M and the frequencies f, tf
8 has the following relationship. 7t/N=7t/M=f■
...... Greatest common divisor.
上記において、位相比較器3に入力する周波数の位相比
較は分局さnた周波Wi、 j1/N 、ft7Mによ
って行われるのでft fI/N及びfz −flハの
周m数のPL、L処理が行われないため、fl−f h
/ N及びft ft7Mの周波数に差違が主じたと
き、この期間でジッタが生ずる欠点を有する。In the above, the phase comparison of the frequencies input to the phase comparator 3 is performed by the divided frequencies Wi, j1/N, ft7M, so the PL and L processing of the frequency m of ft fI/N and fz - fl C is performed. Since it is not done, fl-f h
/N and ft ft7M has a drawback that jitter occurs in this period when the difference is mainly in frequency.
(C) 発明の目的
本発明は上記の欠点を解決するために、入力周波数71
+出力周波e、fxの周期引込み状態でfl及びf諺周
波数に対応する周波数パターンをおき、周波数f1.の
一周期全域にわたって位相比較を行うPLL方式を提供
すること1gI:目的とする。(C) Object of the Invention In order to solve the above-mentioned drawbacks, the present invention aims to improve the input frequency 71.
+ A frequency pattern corresponding to the fl and f frequencies is set in the periodic pull-in state of the output frequencies e and fx, and the frequency f1. 1gI: An objective is to provide a PLL system that performs phase comparison over one period.
(d) 発明の構成
本発明は前記の目的を達成するために、人力信号部波数
71に引込味れて、出力信号周波数f。(d) Structure of the Invention In order to achieve the above-mentioned object, the present invention focuses on a human-powered signal section with a wave number of 71 and an output signal frequency f.
が整形されるPLL方式において、前記入力信号周波数
j1を第1カウンタで計数し、出力信号周波数f3を第
2カウンタで計数し、前記第1及び第2カウンタを夫々
f t / Nでクリアし、該クリアされた第1及び第
2カウンタの夫々の出力はROMに入力して前記入力信
号周波数ft と出力信号周波数f、との位相比較パタ
ーンを整形する手段を設け、該整形された位相比較パタ
ーンは該出力信号周波数f、でラッチされるラッチ回路
を介して該出力信号周波af冨が整形される手段を設け
たことを特徴とする。in a PLL system in which the input signal frequency j1 is counted by a first counter, the output signal frequency f3 is counted by a second counter, and the first and second counters are each cleared by f t /N, Means is provided for inputting the cleared outputs of the first and second counters into a ROM to shape a phase comparison pattern between the input signal frequency ft and the output signal frequency f, and the shaped phase comparison pattern is characterized by providing means for shaping the output signal frequency af through a latch circuit that latches the output signal frequency f.
(e) 発明の実施例
本発明は人力周波数f1+出力出力ftがPLLにおい
て、f I/N = f冨/M=fstなる関係にある
とき、前記周波数f r 、f tが同期引き込み状態
の場合、R(JMのアドレスAdd2.Add2は決っ
たパターンとなり、RLIMのアクセスされる領域は限
定される。もし、周波数f11f!が周期状態にない場
合は、上記の限定された偵域外のアドレスがアクセスさ
れ、周波air、f重の遅れ域いは進み状態の倒定か行
われる。(e) Embodiments of the Invention The present invention is applicable to the case where the human power frequency f1+output output ft has the following relationship in PLL: fI/N=ftension/M=fst, and the frequencies fr and ft are in a synchronous pull-in state. , R (JM's address Add2.Add2 has a fixed pattern, and the accessed area of RLIM is limited. If the frequency f11f! is not in a periodic state, the address outside the limited reconnaissance area mentioned above is accessed. Then, the delay region of the frequency air and f is determined, and the leading state is determined.
以下、本発明のPLL方式の一実施例な第2図に従って
説明する。図中、第1図と同一番号、符号は同一部材を
示し、6.7はカウンタ、8は几OM19はラッチ回路
、lOはD/A変換回路を示す。Hereinafter, a description will be given with reference to FIG. 2, which is an embodiment of the PLL system of the present invention. In the figure, the same numbers and symbols as in FIG. 1 indicate the same members, 6.7 indicates a counter, 8 indicates a latch circuit, and 1O indicates a D/A conversion circuit.
第3図は第2図に用いられるROMを示す0第3図にお
いて、アドレスAddl(周波数f1に対ゐする〕、ア
ドレスAdd2(周波数fatこ対応する)が周波数f
1及びf、で説み出されて位相比較され、同期引込みの
ときは00.遅れのときは01、進みのときは、10を
出力する。Figure 3 shows the ROM used in Figure 2. In Figure 3, address Addl (corresponding to frequency f1) and address Add2 (corresponding to frequency fat) are frequency f.
1 and f, and the phases are compared, and when synchronous pull-in occurs, 00. Outputs 01 when it is delayed, and outputs 10 when it is ahead.
第2図において、入力周波数ノ□は第1カクンタ6に入
力され、出力周波数ftは第2カウンタ7に入力される
。入力周波数f1はl/N分周器1にて17N分周され
、17N分周波は第1カウ インク6と第2カウンタ7
を同時にクリアする。In FIG. 2, the input frequency □ is input to the first counter 6, and the output frequency ft is input to the second counter 7. The input frequency f1 is divided by 17N by the l/N frequency divider 1, and the 17N frequency divided wave is sent to the first counter 6 and the second counter 7.
clear at the same time.
第1カウンタ6、第2カウンタ7の出力は几OM8に入
力され、夫々、周波e、jr、ftに対応したアドレス
Addl、Add2が読み出され、1(0M8において
位相比較が行なわれる。比IIRM来は第3図に示す如
(、同期引込みのときはooが、出力され1遅れ位相の
ときは、Olが出力される。The outputs of the first counter 6 and the second counter 7 are input to the box OM8, and the addresses Addl and Add2 corresponding to the frequencies e, jr, and ft are read out, respectively, and phase comparison is performed at 1 (0M8. Ratio IIRM In the past, as shown in FIG. 3, oo is output when the synchronization is pulled in, and Ol is output when the phase is delayed by one.
RLIM8の出力は出方周波数ftでラッチされるラッ
チ回路9を経て、i)/A変換回路1oでアナログ量に
変換され、その出方はLP11を経てVC05を駆動し
、入力周波数f、に同期した出方周波数f、を出力する
。The output of RLIM8 passes through a latch circuit 9 that is latched at the output frequency ft, and is converted into an analog quantity by the i)/A conversion circuit 1o.The output passes through LP11 and drives VC05, synchronizing with the input frequency f. output frequency f.
(f) 発明の効果
従来分局された周波数f1/l111.f!/Mの位相
比較は周波数が分周比以外の所では比較されないため、
出力周波数f!にジ會夕が発生する欠点があったが、本
発明では直接、fl とfl1ftkLoMを用いて比
較するためジッタが発生しない利点がある0(f) Effect of the invention Conventionally divided frequency f1/l111. f! /M phase comparison does not compare frequencies except at the division ratio, so
Output frequency f! However, in the present invention, since fl and fl1ftkLoM are directly compared, there is no jitter.
第五図は従来例のPI、L方式、第2図は本発明の実施
例、第3図は本発明のRUMi示す図中、lは1/N分
周器、2は17M分周器、3は位相比IR1,4は1.
PF、5はVC,’0.6は第1カウンタ、7は第2カ
ウンタ、8はROM。
9はラッチ回路、10はD/ム変換回路、Addl。FIG. 5 shows the conventional PI, L system, FIG. 2 shows the embodiment of the present invention, and FIG. 3 shows the RUMi of the present invention, where l is a 1/N frequency divider, 2 is a 17M frequency divider, 3 is the phase ratio IR1, 4 is 1.
PF, 5 is VC, '0.6 is first counter, 7 is second counter, 8 is ROM. 9 is a latch circuit, 10 is a D/MU conversion circuit, and Addl.
Claims (1)
が整形されるPLL方式において、前記入力信号周波数
ftw第1カウンタで計数し、出力信号周波数f友を第
2カクンタで計数し、前記第1及び第2カウンタを夫々
f t / Nでクリアし、該クリアされた第1及び第
2カウンタの夫々の出力は几OMに人力して前記入力信
号周波数fIと出力信号周波数f、との位相比較パター
ンを整形する手段を設け、該整形された位相比較パター
ンは該出力信号周波数12でラッチされるう、子回路を
介して該出力信号燭(ll Hf mが整形される手段
を設けたことを%徴とするPLL方式。In the PLL system in which the input signal frequency 11 is input and the output signal frequency is shaped, the input signal frequency ftw is counted by a first counter, the output signal frequency f is counted by a second counter, and the output signal frequency ftw is counted by a second counter. The first and second counters are each cleared by f t /N, and the respective outputs of the cleared first and second counters are manually input to the OM to calculate the difference between the input signal frequency fI and the output signal frequency f. Means is provided for shaping the phase comparison pattern, and means is provided for shaping the output signal (ll Hf m) via a slave circuit so that the shaped phase comparison pattern is latched at the output signal frequency 12. PLL method that takes this as a percentage feature.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58225686A JPS60117919A (en) | 1983-11-30 | 1983-11-30 | Pll system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58225686A JPS60117919A (en) | 1983-11-30 | 1983-11-30 | Pll system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60117919A true JPS60117919A (en) | 1985-06-25 |
Family
ID=16833198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58225686A Pending JPS60117919A (en) | 1983-11-30 | 1983-11-30 | Pll system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60117919A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63152223A (en) * | 1986-12-17 | 1988-06-24 | Toyo Commun Equip Co Ltd | Digital temperature compensation oscillator |
US7011965B2 (en) * | 2001-03-09 | 2006-03-14 | Regents Of The University Of Minnesota | Compositions and methods for stimulating wound healing and fibroblast proliferation |
-
1983
- 1983-11-30 JP JP58225686A patent/JPS60117919A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63152223A (en) * | 1986-12-17 | 1988-06-24 | Toyo Commun Equip Co Ltd | Digital temperature compensation oscillator |
US7011965B2 (en) * | 2001-03-09 | 2006-03-14 | Regents Of The University Of Minnesota | Compositions and methods for stimulating wound healing and fibroblast proliferation |
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