JPS60117919A - Pll system - Google Patents

Abstract

PURPOSE:To prevent the generation of jitters by forming the frequency patterns corresponding to both input and output frequencies in the pull-in mode of both frequencies and performing the comparison of phases over the entire area of a frequency cycle. CONSTITUTION:An input frequency f1 is supplied to the 1st counter 6, and an output frequency f2 is supplied to the 2nd counter 7. The frequency f1 is divided into 1/N by a 1/N divider 1, and this 1/N-divided frequency clears both counters 6 and 7 at a time. The outputs of both counters are supplied to an ROM8, and addresses Add1 and Add2 corresponding to frequencies f1 and f2 are read out. Then the ROM8 performs the comparison of phases. For the result of comparison, 00 is delivered in a pull-in mode and 01 delivered with a delay phase respectively. The output of the ROM8 is converted into the analog quantity by a D/A converting circuit 10 via a latch circuit 9 which is latched with the frequency f2. The output of the analog quantity drives a VCO5 via an LPF4 to deliver the output frequency f2 synchronized with the frequency f1.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to the period acquisition of a clock of a transmission device, and particularly to a PLL system when the input signal frequency and the oscillation frequency of the PLL are different.

(b) Conventional technology and problems Conventionally, input signal frequency f t (hereinafter referred to as human frequency f1
) and output signal frequency ft (hereinafter referred to as output frequency f!).
PLL at the greatest common divisor of the clocks, 1ri□
1. Here, f1t=fJN”fz/M
where l/N and l/N indicate the frequency division ratio.

The conventional PLL system will be explained below with reference to FIG. 1. In the figure, l is an l/N frequency divider, 2 is a single M frequency divider,
3 is a phase comparator, 4 is a low-pass single wave filter (hereinafter referred to as LPF), and 5 is a voltage controlled oscillator (hereinafter referred to as CO).
1 is the human power frequency, f! indicates the output frequency.

In FIG. 1, the input frequency 11 is divided by t/N in the l/N frequency divider l and the output frequency f! is divided by a single ME frequency by a single M frequency divider 2, and each divided frequency am is compared by a phase comparator 3, and the comparison output is 1. PF4
It outputs an output frequency 11Xft which is manually input to the VC (35) and drawn into the input frequency a number fI.

In the above, the frequency division ratio 1/N, l/M and the frequencies f, tf
8 has the following relationship. 7t/N=7t/M=f■
...... Greatest common divisor.

In the above, the phase comparison of the frequencies input to the phase comparator 3 is performed by the divided frequencies Wi, j1/N, ft7M, so the PL and L processing of the frequency m of ft fI/N and fz - fl C is performed. Since it is not done, fl-f h
/N and ft ft7M has a drawback that jitter occurs in this period when the difference is mainly in frequency.

(C) Object of the Invention In order to solve the above-mentioned drawbacks, the present invention aims to improve the input frequency 71.
+ A frequency pattern corresponding to the fl and f frequencies is set in the periodic pull-in state of the output frequencies e and fx, and the frequency f1. 1gI: An objective is to provide a PLL system that performs phase comparison over one period.

(d) Structure of the Invention In order to achieve the above-mentioned object, the present invention focuses on a human-powered signal section with a wave number of 71 and an output signal frequency f.

in a PLL system in which the input signal frequency j1 is counted by a first counter, the output signal frequency f3 is counted by a second counter, and the first and second counters are each cleared by f t /N, Means is provided for inputting the cleared outputs of the first and second counters into a ROM to shape a phase comparison pattern between the input signal frequency ft and the output signal frequency f, and the shaped phase comparison pattern is characterized by providing means for shaping the output signal frequency af through a latch circuit that latches the output signal frequency f.

(e) Embodiments of the Invention The present invention is applicable to the case where the human power frequency f1+output output ft has the following relationship in PLL: fI/N=ftension/M=fst, and the frequencies fr and ft are in a synchronous pull-in state. , R (JM's address Add2.Add2 has a fixed pattern, and the accessed area of RLIM is limited. If the frequency f11f! is not in a periodic state, the address outside the limited reconnaissance area mentioned above is accessed. Then, the delay region of the frequency air and f is determined, and the leading state is determined.

Hereinafter, a description will be given with reference to FIG. 2, which is an embodiment of the PLL system of the present invention. In the figure, the same numbers and symbols as in FIG. 1 indicate the same members, 6.7 indicates a counter, 8 indicates a latch circuit, and 1O indicates a D/A conversion circuit.

Figure 3 shows the ROM used in Figure 2. In Figure 3, address Addl (corresponding to frequency f1) and address Add2 (corresponding to frequency fat) are frequency f.
1 and f, and the phases are compared, and when synchronous pull-in occurs, 00. Outputs 01 when it is delayed, and outputs 10 when it is ahead.

In FIG. 2, the input frequency □ is input to the first counter 6, and the output frequency ft is input to the second counter 7. The input frequency f1 is divided by 17N by the l/N frequency divider 1, and the 17N frequency divided wave is sent to the first counter 6 and the second counter 7.
clear at the same time.

The outputs of the first counter 6 and the second counter 7 are input to the box OM8, and the addresses Addl and Add2 corresponding to the frequencies e, jr, and ft are read out, respectively, and phase comparison is performed at 1 (0M8. Ratio IIRM In the past, as shown in FIG. 3, oo is output when the synchronization is pulled in, and Ol is output when the phase is delayed by one.

The output of RLIM8 passes through a latch circuit 9 that is latched at the output frequency ft, and is converted into an analog quantity by the i)/A conversion circuit 1o.The output passes through LP11 and drives VC05, synchronizing with the input frequency f. output frequency f.

(f) Effect of the invention Conventionally divided frequency f1/l111. f! /M phase comparison does not compare frequencies except at the division ratio, so
Output frequency f! However, in the present invention, since fl and fl1ftkLoM are directly compared, there is no jitter.

[Brief explanation of the drawing]

FIG. 5 shows the conventional PI, L system, FIG. 2 shows the embodiment of the present invention, and FIG. 3 shows the RUMi of the present invention, where l is a 1/N frequency divider, 2 is a 17M frequency divider, 3 is the phase ratio IR1, 4 is 1.
PF, 5 is VC, '0.6 is first counter, 7 is second counter, 8 is ROM. 9 is a latch circuit, 10 is a D/MU conversion circuit, and Addl.

Claims (1)

[Claims] In the PLL system in which the input signal frequency 11 is input and the output signal frequency is shaped, the input signal frequency ftw is counted by a first counter, the output signal frequency f is counted by a second counter, and the output signal frequency ftw is counted by a second counter. The first and second counters are each cleared by f t /N, and the respective outputs of the cleared first and second counters are manually input to the OM to calculate the difference between the input signal frequency fI and the output signal frequency f. Means is provided for shaping the phase comparison pattern, and means is provided for shaping the output signal (ll Hf m) via a slave circuit so that the shaped phase comparison pattern is latched at the output signal frequency 12. PLL method that takes this as a percentage feature.