JPS60113536A - A/d converter - Google Patents

Abstract

PURPOSE:To remove a conversion error by an offset voltage and to execute an A/D conversion with high speed and high accuracy by counting the time that an integration circuit output reaches to the first and an intermediate reference voltages, and an input voltage respectively, and operating them. CONSTITUTION:A fractional-pressure potential terminal 3 is selected by a switching circuit 4, an input terminal 18 is selected by a switching circuit 12, and magnitudes between a measured voltage VIN and a fractional-pressure voltage VR/2 are compared. A constant current from a constant current source 6 is supplied to a capacitor 7 through a terminal 2, the output is increased from zero V, and times T3-T1 whose potentials become equal to the first potential VR, an intermediate potential VR/2, and an input measured potential VIN are counted by the switching circuit 12 and a comparator 8. The following equation: VIN=[2(T3-T2)-(T3-T1)]VR/2(T3-T2) is operated by a CPU20, and an accu rate digital value which does not generate an offset error is obtained.

Description

Detailed Description of the Invention (Technical Field) The present invention provides high-speed, high-precision A/D conversion using an integration method that eliminates errors due to offset voltage of a comparator circuit by performing one integration with a simple circuit configuration. Concerning vessels.

(Prior art) In the converter using the conventional integration method, the offset voltage of the comparator, operational amplifier, etc.
/p conversion error, and in order to correct this, a quadruple integration method or an automatic zero compensation circuit must be used, making the circuit complex and the conversion time longer. Oh.

(Object of the invention) The object of the invention is to eliminate conversion errors caused by offset voltage and to enable high-speed, high-precision A/A conversion.
There are 70 converters to obtain.

(Summary of the Invention) The main point of this invention is to count the time for the input voltage 'f and the integrated value to reach the first and intermediate reference voltages and the time to reach the input voltage, and to correspond to the input terminal based on the difference between these times. It is in calculating the count value to be calculated.

(Example) Hereinafter, an example of the A/p converter of the present invention will be described based on the drawings. FIG. 1 is a circuit diagram of one embodiment. In this Figure 1, ground potential terminal 1, constant current terminal 2
, divided potential terminal 3 are selected by a switch circuit 4 and input to an integrating circuit 5.

This integrating circuit 5 consists of a constant current source 6 and a capacitor 7 of about 0.1 to 0.01 μF, whose output is fed to a comparator 8.
is connected to the (-) input terminal of the

Further, the (g) input terminal of this comparator 8 has a reference voltage VRE.
Two potentials R2VR/2 generated by a voltage dividing circuit 10 having an F terminal 9 or the output of an input voltage hold circuit 11 are selected by a switch circuit 12 and applied. If the reference voltage VRgF is 5v, VR=
4 V, VR/2 = about 2 V.

In the voltage dividing circuit 10, three resistors 13, 14 and 15 are connected in series between the reference voltage terminal 9 and the ground, and the potentials between the resistors 13 and 14 and between the resistors 14 and 15 are VR and VR, respectively. /2 as the input terminal 16 of the switch circuit 12
．． It is connected to 17. Here, the resistors 14 and 15 must have equal resistance values so as to provide the potential Vn l ''R/2.

Further, the output of the input voltage hold circuit 11 is connected to the input terminal 18 of the switch circuit 12.

An input terminal 19 to which a voltage to be measured Vin is applied is connected to the input voltage hold circuit 11 .

A microprocessor (hereinafter referred to as CPU) 20 controls the switch circuits 4 and 12 and the input terminal hold circuit 11 and measures time.
I'm starting to do better.

Next, regarding the operation of the A/D converter of the present invention configured as described above, we will explain the operation of the A/D converter according to the present invention as follows. Explain with reference to.

The A/1) converter according to the invention operates in three modes:
It consists of a magnitude comparison between the voltage to be measured Vin and the divided potential VR/2 (mode 1), an integration process (mode 2), and a calculation process (mode 3).

First, the operation in mode 1 will be explained. The switch circuit 4 selects the divided potential terminal 3 and applies the voltage of VR/2 to the (-) input terminal of the comparator 8. At the same time, the voltage to be measured V
in is applied to the voltage to be measured input terminal 19 and held in the input terminal hold circuit 11.

Thereafter, the multiple input terminal 18 is selected in the switch circuit 12, and the voltage to be measured Vin is applied to the (+) input terminal of the comparator 8. In this state, the voltage to be measured Min and the divided potential VR/2 are compared in magnitude, and the results of the comparisons are stored by the CPU 20. Then, the process moves to the next mode 2.

In mode 2, when the result of mode 1 is Vin≦VR/2, the operation is as follows (see FIG. 2(a)). First, the (g) input terminal of the comparator 8 is connected to the input terminal 18 by the switch circuit 12, and the ground potential terminal 1 is connected by the switch circuit 4.
is selected to discharge all charges in the capacitor 7, the constant current terminal 2 is selected, a constant current is applied to the integrating circuit 5, and the CPU 20 starts time measurement.

In this state, the pulse count number at the time when the matching signal is output from the comparator 8 is recorded as T in the CPU 20, and the input terminal 17 is selected by the switch circuit 12, and the (+) input terminal of the comparator 8 is is changed from the potential to be measured Vin to the potential VR/2.

In this state, the pulse count number at the time when the comparator 8 outputs the coincidence signal is recorded in the CPU 20 as T2, and the input terminal 16 is selected by the switch circuit 12, and the (+) input terminal of the comparator 8 is is changed from the potential VR/2 to the potential 2.

In this state, the count number at the time when the match signal is output from the comparator 8 is set as T, and is recorded in the CPU 20, and the switch circuit 4 selects the divided voltage terminal 3, and returns to the mode 1 and returns to the next mode. Move to operation mode 3. When the pulse count is 8 bits, 256 to 512 pulses are counted, and the required time is about 1 mS.

Also, in the case of Vin≧VR/2, it is almost the same as described above, but the order of connection to the (+) input terminal of the comparator 8 is as follows (see FIG. 2(b)). First, select the multiple input terminal 17 to the switch circuit 12, select the count number at this time T2, then select the input terminal 18, select the count number t-T at this time, and finally select the input terminal 16. Then, let the count at this time be e f Ts.

Next, in mode 3, calculations are performed as follows. Count values T, , T, , T obtained in mode 2.

includes an error due to the offset voltage d of the comparator 8.

Now, each count value when there is no offset voltage is TI' r T2' + T! ', the voltage to be measured Vin can be expressed by the potential vR.

Here, if the counting error due to the offset voltage d is TOFS, then T'-T+-TOFS, T2'-T2-T
OFS I Ts'-Ta-TOFS, and
The linearity of the integrating circuit 5 is Ts'-2 (Ts'L),
And since TX 'r,' -Ta, T+,
Equation (1) is vi, -” (Ta T2 ) (Ta 11.)
yR,9,(2)2 ('1:s T2) The measured voltage Vin is T obtained in mode 2.
+, T2, and Ts, it is converted into an accurate digital value that does not cause errors due to offset voltage. Furthermore, since mode 3 is processed in parallel with mode 1, speeding up can be achieved.

As explained above, in the first embodiment, the circuit configuration and control are relatively simple, and processing can be performed by the CPU 20fJ, making it easy to interface with a microprocessor, and it can be integrated on the same chip. It is easy to do.

Furthermore, since the offset voltage of the comparator, which is usually several tens of mV, does not cause an error and conversion can be performed by single integration, the integration method allows high-speed and highly accurate conversion.

In addition, the time required for one AD conversion is determined by the pulse count time of T in the case of 8 bits, and is 9.256 to 51.
It takes about 1 ms to count 2 pulses. In addition, calculation time f: 1 μs for each 100 steps, 0.1 mS
It takes a certain degree. If the charging time required for the hold circuit for the voltage to be measured Vin is set to 0 to 1 mS, the maximum charging time is about 2 ms.

Further, the charging time of the hold circuit can be ignored if the voltage to be measured varies little over time. In this case, one AD conversion is possible in 1 to 1.5 tylS. A great advantage of the present invention is that conversion without offset errors can be performed with only one integration.

(Effect of IJ: IJ) As explained above, the present invention counts the time for the integral value of the input voltage to reach the first and intermediate reference voltages and the time for it to reach the input terminal, and calculates the difference between these times. Since the count value corresponding to the reverse input voltage is calculated, the A/D conversion is performed using an integral method, but since offset voltages such as comparators do not cause errors, highly accurate conversion is possible.

In addition, since it uses a stacked valve system, it has the advantage of short conversion time, and the circuit configuration is simple.
Can be integrated on the same chip as a microprocessor,
This brings about an effect that can further demonstrate its true value.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the A/D converter of the present invention,
FIG. 2 is a graph showing the principle of A/D conversion. 1... Ground potential terminal, 2... Constant current terminal, 3...
Divided potential terminal %4.12...Switch circuit, 5 internal integration circuit, 6 middle foot current source, 7...Capacitor, 8...Comparator, 9...Reference voltage terminal, 1o...・Voltage dividing circuit, 1
1... Input terminal hold circuit, 13, 14.15...
・Resistance, 19...Failure measurement voltage input terminal, 20...c
PU0 Procedural Amendment June-7, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1, Indication of Case, 1982 Patent Application No. 220519 2, Title of Invention A/D Converter 3, Person Making Amendment Case and Relationship between patent applicant (02F) Oki Electric Co., Ltd., Kikoho Co., Ltd. 4, agent 5, date of amendment order Showa year, month, day (spontaneous) 6, subject of amendment detailed description of the invention of Meiji Kutsu ]■7. Contents of amendment 1) Page 7, line 11 of the specification "T' = T+ -TOFSJ
is corrected as r T+'= T+ ToFSj.

Claims (1)

[Scope of Claims] An integrating circuit comprising a constant current source and a capacitor, means for creating first and second reference voltages, means for holding an input voltage, an output of the integrating circuit and each of the reference voltages. or a comparison circuit that compares the input voltages and outputs a match signal when they match, and a first time when the output of the integration circuit reaches a first reference voltage from zero voltage, and a second time when the output of the integration circuit reaches an intermediate reference voltage. If the input voltage reaches the third
61 (corresponding to the above-mentioned input voltage).