JPS60111551U - FM recording and playback circuit - Google Patents
FM recording and playback circuitInfo
- Publication number
- JPS60111551U JPS60111551U JP20374583U JP20374583U JPS60111551U JP S60111551 U JPS60111551 U JP S60111551U JP 20374583 U JP20374583 U JP 20374583U JP 20374583 U JP20374583 U JP 20374583U JP S60111551 U JPS60111551 U JP S60111551U
- Authority
- JP
- Japan
- Prior art keywords
- recording
- circuit
- playback
- input
- playback circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は、本考案の回路図Ａ及びＢを表わし、１゜１′は入
力、２． ２’ｉよプリアンプ、３は被制御増幅器、４
・は制御電圧検出回路、５はアンプ、６゜６′は出力、
７はバッファアンプである。
補正 昭５９．５．１
図面の簡単な説明を次のように補正する。
図面の簡単な説明
図は、本考案ＦＭの録音、再生回路図を示し第１図は録
音回路で第２図は再生回路であって音声信号は１より入
力して録音され、録音された信号は６から出力して１′
に入力し、再生回路を通って６′に出力する回路構成を
、録音と再生に分けて表わし、１，１′は入力部、２，
２′はプリアンプ、３は被制御増幅器、４は制御電圧検
出回路、５はアンプ、６，６′は出力部、７はバッファ
アンプである。The figure shows circuit diagrams A and B of the present invention, where 1°1' is the input, 2. 2'i is the preamplifier, 3 is the controlled amplifier, 4
・ is the control voltage detection circuit, 5 is the amplifier, 6゜6' is the output,
7 is a buffer amplifier. Amendment May 1, 1982 The brief description of the drawing is amended as follows. A simple explanatory diagram of the drawings shows a recording and playback circuit diagram of the FM of the present invention. Fig. 1 is a recording circuit, and Fig. 2 is a playback circuit. The audio signal is input from 1 and recorded, and the recorded signal is is output from 6 and becomes 1'
The circuit configuration that inputs the input to 6' through the playback circuit and outputs it to 6' is shown separately for recording and playback, where 1, 1' is the input section, 2,
2' is a preamplifier, 3 is a controlled amplifier, 4 is a control voltage detection circuit, 5 is an amplifier, 6 and 6' are output sections, and 7 is a buffer amplifier.
Claims (1)
ョンを入れ、ＡＧＣ回路により入力の振幅を一定にして
ＦＭ変調を行ない記録に入力させて録音し、ヘッドから
の出力を前置アンプにより増幅し、リミッタ回路を入れ
てノイズ部分の振幅をそろえ、ＳＮ比を改善してＦＭ復
調し、ノイズルダクションでさらに調整し、アンプして
再生するように組合せた形態を特徴とするＦＭの録音再
生回路。Amplify the audio signal to a certain level, add noise reduction, keep the input amplitude constant using the AGC circuit, perform FM modulation, input it to record, and amplify the output from the head with a preamplifier. This FM recording and playback circuit is characterized by a combination of a limiter circuit to equalize the amplitude of the noise part, improved SN ratio, FM demodulation, further adjustment by noise reduction, and amplification for playback.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20374583U JPS60111551U (en) | 1983-12-29 | 1983-12-29 | FM recording and playback circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20374583U JPS60111551U (en) | 1983-12-29 | 1983-12-29 | FM recording and playback circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60111551U true JPS60111551U (en) | 1985-07-29 |
Family
ID=30766151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20374583U Pending JPS60111551U (en) | 1983-12-29 | 1983-12-29 | FM recording and playback circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60111551U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57140085A (en) * | 1981-02-23 | 1982-08-30 | Hitachi Ltd | Audio signal recording and reproducing circuit |
| JPS57190477A (en) * | 1981-05-18 | 1982-11-24 | Hitachi Ltd | Noise suppressing circuit |
-
1983
- 1983-12-29 JP JP20374583U patent/JPS60111551U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57140085A (en) * | 1981-02-23 | 1982-08-30 | Hitachi Ltd | Audio signal recording and reproducing circuit |
| JPS57190477A (en) * | 1981-05-18 | 1982-11-24 | Hitachi Ltd | Noise suppressing circuit |
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