JPS60109345A - Clock synchronizing system - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a burst signal by fixing the clock synchronization by plural burst signals transmitted from the same earth station and eliminating the need for the clock reproducing code contained in the burst signal. CONSTITUTION:A burst clock reproducing circuit 32 reproduces a burst clock 33 to a reception burst signal 31 and compares the phase of a master clock 44 of the own station with the phase of the clock 33 at the latter half part of the signal 31. The mean value of plural phase difference signals thus obtained are stored by a fixed latest number for plural burst signals. An identification clock 49 of the signal 31 is produced by meand of the mean value of the stored phase difference information and then supplied to a discriminating circuit 57. The synchronization of this clock is performed by a clock synchronization detecting circuit 59. Then a reception signal 58 is fetched by a clock synchronization fixing signal 60.

Description

Detailed Description of the Invention (Technical Field) The present invention provides a system for transmitting modulated burst signals intermittently at appropriate time intervals in TDMA-based satellite communications, and receiving the burst signals at 1111 intervals on the receiving side. This invention relates to a clock cycle system in a digital communication system.

(Background Art) A typical communication system that uses burst-like digital modulation signals that are time-divided and transmitted from a transmitting earth station at appropriate intervals is a time division multiple access (TDMA) system.

TDMA where the clock phase is not synchronized between bursts
Conventionally, clock synchronization is closed within l burst signals.

A clock recovery circuit and a typical burst configuration in a conventional TDMA system are shown in FIGS. 1 and 2, respectively. In FIG. 1, 1 is a modulated burst signal, 2 is a clock component extraction circuit, 3 is a clock component extracted by the clock component extraction circuit 2, and 4 is a resonator for the clock frequency (
tank circuit), 5 is a regenerated clock. 6 in Figure 2 is card time (GT), 7 is carrier reproduction code (CW)
), 8 is the clock recovery code (BTR), and 9 is the synchronization word (
UW), lO is an information signal (DATA).

In this conventional method, since clock synchronization is closed within the l burst signal, clock synchronization must be established before synchronization word 9 and information signal 10 in FIG. 2 are received.
It was necessary to attach a clock regeneration code 8 having a length necessary to establish clock synchronization to the front of the synchronization hh9. The length of the clock regeneration code 8 is related to the start-up characteristic of the tank circuit 4 shown in FIG. 1, and in order to regenerate a clock with a small phase error, the tank circuit 4 must have a narrow band. First, in this state, the rise time of the tank circuit 4 becomes long. Therefore, the clock regeneration code 8
becomes longer, and the proportion of the clock recovery code 8 in the burst signal becomes larger. Therefore, the conventional clock synchronization method has the drawback of low transmission efficiency.

(Problem to be solved by the invention) The present invention provides a relationship between bursts transmitted by the same earth station so that the clock frequency and phase hardly deviate, and demodulates the burst signal transmitted by the earth station. The clock synchronization is established by a plurality of burst signals transmitted by the earth station, and the establishment of the clock synchronization is determined by using means for detecting the establishment of the clock synchronization, The purpose of this is to improve the efficiency of burst utilization by eliminating the need for the clock code, which conventionally had 1,000 digits at the beginning of the burst signal.

(Structure and operation of the invention) First, the overall operation of the clock periodic circuit according to the present invention will be explained using a block diagram, and then the detailed operation of each part will be explained using examples of the circuits of each part. Thereafter, an embodiment of the clock synchronization detection method according to the present invention will be shown and explained.

FIG. 3 is a block diagram showing the configuration of the clock synchronization circuit in the method of the present invention, where 31 is a received burst signal, 32 is a burst clock recovery circuit 33 is a recovered burst clock for the received burst h31, and 36 is a recovered burst signal. Phase comparator of clock 35, 37 is phase comparator 3
6 phase comparison output, 38 counter section, 39 count output 38, 40 calculation section, 41 reception burst signal 3
1, 42 is a clock shift section, 43 is a timing generation section, 44 is a master clock, 45 is a clock selection gate signal, 4G is a sample gate signal, 47 is a manual timing signal, 48 is an output timing signal, 48 is an identification clock, 50 is a clock selection signal, 51 is a burst pulse, 52 is a clear pulse, 5
3 is sample pulse, 54 is shift clock, 55 is π
/2 shift clock, 5e is a clock generator, 57 is an identification circuit, 5th is a received signal after identification, 59 is a clock synchronization detection circuit, 60 is a clock synchronization establishment signal, and 61 is a gate signal. First, the burst clock regeneration circuit 32 generates a burst clock 3 for the received burst signal 31.
Play 3. The phase of the reproduced burst clock 33 is compared with the phase of the own station's master clock 44 by a phase comparator 36 in the second half of the received burst signal 31 when the output of the burst clock recovery circuit 32 rises sufficiently. Ru. The output 37 of the phase comparator 36 is a high-speed sample pulse 53 that is gated in the phase comparator 36 to form a burst, and the number of burst sample pulses 53 is counted by the counter 38.・To be done. At this time, this sampling is performed for the received burst signal 3.
This is done for multiple bits in the latter half of 1, so
The output 38 of the counter section 38 is the sum of phase difference information with respect to the mask clock 44 of the plurality of bits. Arithmetic unit 4o
Then, input the output 38 using the manual timing signal 47, divide the value of the output 38 by the measured number of bits, and calculate the reproduction parse! Determine the average phase of the clock 33 and store the average phase in the memory as phase difference information A with respect to the received burst signal 31. The above operation is performed on a plurality of burst signals transmitted from the same earth station as the received burst signal 31, and clock phase difference information A for each burst signal is stored in memory. The plurality of phase difference information A
The number of memories storing the information is a certain fixed number, and the oldest phase difference information A is replaced with the newest phase difference information A. By performing this operation, the newest constant number of phase difference information A is always stored in the memory. The identification clock of the received burst signal is created using the average value (phase difference information B) of the phase difference information A of the minus number. That is, the phase difference information B is generated from a certain number of burst signals transmitted from the same earth station preceding the received burst signal 31 to be identified, and is generated from the clock position by the calculation unit 40 based on the output timing signal 48 from the timing generation unit 43. It is output as a phase difference information signal 41. The clock phase difference information signal 4
1 enters the clock shift section 42, and the clock shift section 4 enters the clock shift section 42.
2, the master clock 44 is a high-speed shift clock 5.
4 and is supplied to an identification circuit 57 as an identification clock 49, by which the received burst signal 31 is identified. Further, the establishment of this clock synchronization is performed by the clock synchronization detection circuit 58, and a clock synchronization establishment signal 60 is output. The received signal 58 is taken in after the establishment of clock synchronization is confirmed by the clock synchronization establishment signal 60. The outline of this clock synchronization method has been explained below.

Examples of the circuits in each part of the block diagram will be shown, and detailed operations will be described below.

First, an example of the burst clock recovery circuit 32 is shown in FIG.

In this embodiment, the burst clock recovery circuit 32 is composed of a clock component extraction circuit and a resonant circuit, and the former is a fourth
The latter is FIG. 4B.

In FIG. 4A, 31 is a received burst signal, 35 is an extracted clock component, 62 is a level comparator, and 63 is a clock component extraction circuit. In this embodiment, a demodulated signal is used as the received/heast signal of 31, and the demodulated signal is converted to a TTL level by a level comparator 62, and then the rising and falling edges of the demodulated signal are converted to a TTL level by a level comparator 62. By hitting two monomultis with
Clock component 35 is extracted. 35 in FIG. 4B is the clock component extracted by the clock component extraction circuit, 3
3 is a reproduction/heast clock for the received burst signal 31, 64 is a resonant circuit (tank), and 65 is a resonance limiter (
limiter). In this embodiment, 65KH2 is used as the clock frequency, and the center frequency of the tank 64 is 65KH2.
At 5 KHz, the Q of tank 64 is approximately 54. Therefore, the amount of improvement in S/H by the tank 64 is about 17.3 dB. The resonant circuit uses 64 tanks to create a clock component with improved S/N, and further limits the tarok component to 8.
5, the received burst signal 31 is converted into a rectangular wave and outputted as a reproduction/heast clock 35 for the received burst signal 31.

FIG. 5 is a circuit example of the phase comparator 36 in FIG.
The figure shows the phase comparability of the phase comparator 3B.

In FIG. 6, 33 is a reproduced burst clock from the burst clock recovery circuit 32, 45 is a clock selection gate signal from the timing generator 43, 44 is a mask clock, 5
5 is a π/2 shift clock for creating the phase comparison characteristics shown in FIG. 6, 52 is a clear pulse from the timing generator 43, 53 is a sample pulse for phase comparison, and 50 is a clock selection signal to the calculation unit. , 37 is a phase comparison output of the counter, 66 is a clock selection circuit, 67 is a phase comparison circuit, and 68 is a selection clock.

H, 70 in FIG. 6 is the phase comparison characteristic of the present phase comparison section 36. The phase comparator of this phase comparator 36 has a preset,
A clear D flip-flop is used, and by comparing the phase of the reproduced burst clock 33 using two clocks shifted by ±π/2 with respect to the master clock 44, continuous burst clocks 33 can be detected. It is possible to set the equal phase from multiple hiras:・ to i+f. That is, when the phase of the reproduced eight-stroke clock 33 is in region 1 (0 to π) in FIG. Perform phase comparison using phase comparison characteristics. Furthermore, the phase of the reproduced burst clock 33 is in region 2 (π
~27c), the voltage is + with respect to the master clock 44.
By using a clock shifted by Tc/2, phase comparison is performed with a phase comparison characteristic of 70. The clock selection circuit 66 selects the master clock 44 and the burst clock 3 by the clock selection gate signal from the timing generator 43.
It is determined from the 1 bit of 3 whether it is in area 1 or area 2, and a clock selection signal 50 is sent to the calculation unit 40. Furthermore, a π/2 shift clock 55 from the clock generator
(2,08 MHz), the master clock 44 is delayed by π/2 using an 8-bit shift register, two types of clocks with a phase difference of ±π12 are created using an inverter, and furthermore, the clock selection signal 50 is used to delay the master clock 44 by π/2, and then use the clock selection signal 50 to delay the master clock 44 by π/2. One of the clocks with a phase shift of π/2 is selected and outputted as the selected clock 68 to the phase comparison circuit 67. The phase comparison circuit 67 uses the clock 68 and the burst clock 3.
The sample pulse 53 (18, 84 MHz) from the clock generator 56 is gated with a phase difference of 3.
The gated sample pulse 53 is sent as the output 37 of the phase comparison section 36 to the counter section 3g.

FIG. 7 shows an example of the circuit of the counter section 38, where 37 is the output of the phase comparison section 36, 38 is the output of the counter section 38, 46 is the sample gate signal from the timing generation section 43, and 52
is a clear pulse from the timing generator 43. The counter section 38 counts the pulse signal of the output 37 of the phase comparison section while the sample gate signal 46 is applied, and outputs the pulse signal of the output 37 of the calculation section 40 to the I10 port of the calculation section 40.

Further, when the next eight-stroke signal arrives, the output 38 of the counter section 38 is reset by the clear signal 52.

FIG. 8 shows a circuit example of the calculation unit 40, where 38 is the output of the counter unit, 50 is the clock selection signal from the phase comparator 36, 41 is phase difference information with respect to the master clock 44 of the identification clock for the burst signal to be demodulated, 47 is the output value 'f!' of the counter section. Manual timing signal for inputting f39, 48 is identification clock, 2 master clocks 4
This is an output timing signal for outputting phase difference information 41 for 4. The calculation unit 40 is composed of three chips: a GPU, an old ROM on the I10 port, and a RAM on the r10 port. The calculation unit 40 receives an input timing signal 47.
The output 39 of the counter section is taken in by , the value of the output 39 is divided by the number of bits determined by Jll, and the average value per bit is calculated. Furthermore, it is determined whether the phase of the reproduced burst clock 33 is in region l or region 2 in FIG. 6 by the clock selection signal 50 from the phase comparator 36, and the average value for each l bit is determined. By adding phase correction (±π/2) to the region, R
Store in AM. Next, phase difference information A with respect to the master clock of the reproduced burst clock 33 similar to the above for a certain number of plural burst signals transmitted from the same transmitting station preceding the received burst signal 31 and the received burst signal 31 The average value of the phase difference information A of the regenerated burst clock 33 with respect to the mask clock for the burst 45 that is transmitted from the same earth station as the received burst signal 31 and that comes after the received burst signal 31
The information is stored in the RAM as phase difference information B between the identification clock for the signal and the master clock 44. Then, the phase information B is output as phase difference information 41 of the identification clock 48 with respect to the master clock 44 for the received burst signal demodulated by the output timing signal 48 when the burst signal arrives.

FIG. 9 is a circuit example of the clock shift section 42, where 41 is the output signal from the calculation section 40, 44 is the master clock,
49 is an identification clock, and 54 is a shift clock. The clock shift section 42 consists only of a l-chip variable length shift register of up to 64 bits. In the clock shift unit 42, the shift clock 54 (4,1
B MHz), phase difference information 41 from the calculation unit 40
A delay corresponding to 1 is applied to the master clock 44, and the delayed clock is output as the identification clock 49.

The timing generator 44 in FIG. 3 uses the burst pulse 51 synchronized with the beginning of the received burst signal 31 supplied from the outside and the master clock 44 from the clock generator 56, and uses the burst I pulse 51 as a reference. , shift registers, etc., generate timing signals and gate signals necessary for each part.

The clock generating section 56 in FIG. 3 uses the 18.84 MHz clock as a reference, divides the frequency of the clock, generates a required clock, and supplies it to each section.

Next, an embodiment of the clock synchronization detection method according to the present invention will be described.

Figure 1O is an example of this clock synchronization detection method, and shows 58
80 is the received signal after identification, 80 is the clock synchronization establishment signal,
61 is a gate signal, 101 is a uw detection circuit, 102 is a detection pulse, 103 is a reset signal, 104 is a counter,
105 is the output of the counter 104, 10? is a judgment circuit, 1
06 is a boundary value to the determination circuit 107, and 10B is an aperture signal.

First, from the received signal 58 after identification, the UW detection circuit +01
detects the UW in the received burst signal and outputs the detection pulse ]02. Then, the detection pulse 102 is counted by a counter 103. At this time, the output +02 of the UW detection circuit 101 is a signal detected in sequence among the burst signals sent from a plurality of earth stations, and includes a mixture of UW detection pulses for the plurality of earth stations. Therefore, the gate signal 61 corresponding to the reception timing of the burst signal transmitted from each earth station is obtained from the outside, and the
The UW detection pulses present in J and S are separated for each earth station and counted by a counter 104. Then, at 41ij when the preset boundary value 10Ei and the output 105 of the counter 104 match, the determination circuit 107 outputs a clock synchronization establishment signal 60. Note that the clock period establishment signal 60
If it fails to detect Uw before it is output, the corresponding UW
The counter 104 corresponding to the earth station that sent (,?) is reset by the reset signal 103. That is, in this embodiment, the establishment of clock synchronization is determined by continuously detecting the UW a plurality of times.

FIG. 11 shows another embodiment of this clock synchronization establishment detection method, and shows a flowchart of the operation. 11
0 is the beginning of flowchart 1, 111°112, 11
3. [4, 115, 118 are the contents to be executed, 116 is the condition judgment, 117.118 is the route after the condition judgment, 12
0 indicates the end of the flowchart. This flowchart can be executed by incorporating a program in the calculation unit 40 of FIG. 3. First, the value of the phase difference information B mentioned above is initially the same as the phase difference information A.
are being accumulated one by one, so it is thought that the fluctuations will be large until a certain number of 4th place difference information A is collected. Therefore, as shown in Figure 7511, the first phase difference information B is read out at 113, the i-th phase difference information B is read out at 114, and the difference ΔB between the two phase difference information B is determined at 115. A preset value ΔBre
Establishment of clock synchronization can be determined by comparing f and 11Ef and detecting a state in which ΔB×ΔBref.

Another method is shown below. The number of phase difference information A mentioned above is a value determined in the design of the system and is a known value. Therefore, by counting the number of phase difference information A using a counter, it is possible to automatically
You can know the establishment of This embodiment is shown in FIG. 121 is a received burst signal before demodulation, 122 is a burst signal detection circuit, 123 is a detection pulse of 122, 124
is a counter, 125 is a gate signal to the counter 124,
126 is the output of the counter 124, 127 is a judgment circuit, +
28 is a boundary value of the determination circuit 127, and 129 is a clock synchronization establishment signal t''i.As a method for detecting the burst signal 121 before demodulation, 122 uses envelope detection.
This is a burst signal detection circuit. This circuit 122 first performs envelope detection of the received burst signal, and outputs a detection pulse 123 using the level of the envelope detection output as a trigger force. The detection pulse 123 is a mixture of signals sent from multiple earth stations, and in order to separate the detection pulse 123 for each earth station, it is necessary to receive the burst signal t) sent from each earth station from the outside. A gate signal 125 corresponding to the timing is received, and the counter 124 is controlled by the gate signal 125 to count the detected pulses 123 of the burst signal 121 for each earth station. The output 126 of the counter 124 corresponding to each earth station is input to the judgment circuit 127, and the output 126 is inputted to a predetermined boundary value 128 and
A tarokk synchronization establishment signal 123 is output from the poem determining circuit 127 in which 26 matches.

(Effects of the Invention) As explained above, the normal TDMA system requires about 80 symbols for clock recovery (BTR).
When the tree clock synchronization method is used, the clock recovery code (BTR) becomes unnecessary, and burst utilization efficiency can be improved. Figure f515 shows the transmission capacity per burst and the utilization efficiency of 7 hests when the frame period is constant at 50 m5. FIG. 13(a) is a curve of the conventional method, and FIG. 13(b) is a curve using the method of the present invention. As can be seen from FIG. 13, when the method of the present invention is used, the smaller the transmission capacity per burst, the greater the improvement in burst utilization efficiency. In other words, the method of the present invention has a low speed T
It is more effective for the DMA method.

In this clock cycle method, phase difference information of the identification clock is obtained by taking a moving average over multiple frames. That is, this operation is equivalent to performing integration in determining the clock phase, and serves to increase the Q of the tank of the burst clock regeneration circuit isometrically. Therefore, it has the effect of improving CIH, and in the experimental example of this clock synchronization method, by taking a moving average over 8 frames, l
An improvement effect of about EidB was obtained compared to the case of only frames. FIG. 14 shows an example of the results of this experiment. The horizontal axis is Eb/
Na [dB E (signal power per bit and 1) 1
(ratio of noise power per z) The vertical axis is the clock phase jitter [
deg ]. a is a moving average over 8 frames, and an average of 32 bits per frame. b is the average of 32 bits per frame. Comparing a and b, it can be seen that an improvement effect of about EidB can be obtained.

3 is a clock diagram of a clock synchronization circuit, FIG. 4A is a clock component extraction circuit, FIG. 4B is a resonant circuit, FIG. 5 is a phase comparison section, and FIG. 6 is a phase comparison characteristic. ff17 figure shows the counter section,
Fig. 8 shows the yI calculation section, Fig. 9 shows the clock shift section, and Fig. 10 shows the yI calculation section.
The figure shows an example of a clock synchronization detection circuit. FIG. 14 is a graph of the clock phase jitter versus the ratio of power per bit to power per lHz (El,/No).

■-Modulated burst signal, 2-Clock component extraction circuit, 3-Extracted clock component, 4-Resonance circuit, 5-M-Regeneration clock, 6-Card time, 7-Carrier regeneration code, 8-Clock reproduction code, 9- synchronization word (UW), 10- information signal, 31-
Received burst signal, 32- Burst clock regeneration circuit, 33- Regenerated burst clock, 3G- Phase comparison section, 37- Output of phase comparison section 3G, 38- Counter section, 39- Output of counter section 38, 40- Arithmetic unit, 41-
Output of calculation unit 40, 42- clock shift unit, 43- timing generation unit, 44- mask clock, 45- clock selection gate signal, 48- sample gate signal, 47- manual timing signal, 48- output timing signal, 49- identification clock, 50- clock selection signal, 51- burst pulse, 52-/7 rear pulse, 53
- sample pulse, 54- shift clock, 55- π/2 shift clock, 56- clock generator, 57- identification circuit, 58-
Received signal after identification, 59- Clock synchronization detection circuit.

60--clock synchronization establishment signal, 61- gate signal, 62- level comparator, 63-
Clock component extraction circuit, 64- Resonant circuit (tank), 65- Amplitude limiter, 66- Clock selection circuit, 67- Phase comparison circuit, 68- Selection clock, 89
, 70- phase comparison characteristic of phase comparison section 36, +01--
- UW detection circuit, 102- detection pulse, 103-
recent signal, 104- counter, 105- output of counter 104, 106- boundary value, 10? -m-judgment circuit, 108-
Aperture signal, 110--Start of flowchart, 111, 112.113.114.115.119 is content to be executed, 116-Condition judgment, [7,118-11 Path after condition judgment, 120-End of flowchart, 121- Received burst signal, 122- Burst signal detection circuit, 123- Detection pulse, 124- Counter, 125
- Gate signal, 126- Output of counter 124, 127- Judgment circuit, 128- Boundary value, 129- Clock synchronization establishment signal.

patent applicant Nippon Telegraph and Telephone Corporation patent application agent Patent Attorney Megumi Yamaki

Claims (1)

[Claims] A transmitting earth station transmits modulated burst signals intermittently at appropriate time intervals, a receiving earth station receives the burst signals at appropriate time intervals, and the transmitting and receiving sides have highly stable reference clocks with the same nominal frequency. , adjacent burst signals transmitted from the same earth station have a relationship such that there is almost no shift in clock frequency and phase. In a digital communication system in which a clock recovered from one or more preceding burst signals to be transmitted is used as an identification clock for the received burst signal, the clock is recovered using means for detecting the establishment of clock synchronization when the receiving earth station starts reception. A clock synchronization method characterized by determining that synchronization has been established.