JPS60107955A - Reference carrier regenerating circuit - Google Patents

Reference carrier regenerating circuit

Info

Publication number
JPS60107955A
JPS60107955A JP58215244A JP21524483A JPS60107955A JP S60107955 A JPS60107955 A JP S60107955A JP 58215244 A JP58215244 A JP 58215244A JP 21524483 A JP21524483 A JP 21524483A JP S60107955 A JPS60107955 A JP S60107955A
Authority
JP
Japan
Prior art keywords
circuit
phase
signal
oscillation
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58215244A
Other languages
Japanese (ja)
Inventor
Shunsuke Hayashi
俊介 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58215244A priority Critical patent/JPS60107955A/en
Publication of JPS60107955A publication Critical patent/JPS60107955A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/227Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H04L27/2273Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals associated with quadrature demodulation, e.g. Costas loop

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To miniaturize and simplify the circuit constitution by switching a phase locked loop for continuous wave and a reference carrier regenerated circuit. CONSTITUTION:A branch circuit 1 divides a 2-phase PSK signal, the result is detected by phase detectors 2a, 2b, discriminated by discriminators 3a, 3b and converted into a binary digital signal. The signals are synthesized by an EX- NOR4 via a logical circuit 14, filtered by a low pass filter 5, a voltage controlled oscillator is controlled and the result is branched by a 0-pi/2 branch circuit 7. When an external control signal A is at ''HI'' level, a phase locked loop is constituted and when ''LO'', a carrier regenerating circuit is constituted.

Description

【発明の詳細な説明】 〔発明の゛技術分野〕 ′ この発明はディジタル乗算形コスタスルーズによる
2相PSK信号波用基準搬送波再生装置に係り、特に搬
送波再生時における位相77 ヒキュイテ4 (pha
se Ambjguity )除去を目的とするもので
ある。
Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a reference carrier regeneration device for a two-phase PSK signal wave using a digital multiplication type Costa Sloose, and particularly relates to a reference carrier wave regeneration device for a two-phase PSK signal wave at the time of carrier wave regeneration.
se Ambjguity) removal.

〔従来技術〕[Prior art]

従来のディジタル乗算形コスタスループによる2相PS
K信号波用基準搬送波再生装置として第1図に示すもの
があった。図において(1)は信号分波回路(以下第1
の分波回路という。)、(2a)(2b)は第1.第2
の位相検波器、(3a)(3b)は第1.第2の識別器
、(4)はEx−NOR論理回路、(5)は低域通過フ
ィルタ。
Two-phase PS using conventional digital multiplication type Costas loop
There was a standard carrier wave regenerator for K signal waves as shown in FIG. In the figure, (1) is the signal branching circuit (hereinafter the first
This is called a branching circuit. ), (2a) and (2b) are the first. Second
The phase detectors (3a) and (3b) are the first. The second discriminator, (4) is an Ex-NOR logic circuit, and (5) is a low-pass filter.

【6)は電圧制御発振器(以下VOOという。)、(7
)は0−π/2分波回路(以下第2の分波回路という。
[6] is a voltage controlled oscillator (hereinafter referred to as VOO), (7
) is a 0-π/2 branching circuit (hereinafter referred to as a second branching circuit).

)である。).

次に動作について説明する。2相P8に信号は第1の分
波回路(1)により2分割され、第1の信号は第2の分
波回路(7)にて移相されないほうのV (I Q :
6)の出力と共にatの移相検波器(2a)Ic、第2
の信号は第2の分波回路(7)にてπ/2移相されたV
 (10Fi+の出力と共に第2の位相検波器(2b)
にそれぞれ入力される。
Next, the operation will be explained. The signal to the two-phase P8 is divided into two by the first branching circuit (1), and the first signal is divided into two by the second branching circuit (7).
6) together with the output of at's phase shift detector (2a) Ic, second
The signal is phase-shifted by π/2 in the second branching circuit (7).
(Along with the output of 10Fi+, the second phase detector (2b)
are input respectively.

第1 、’ 第2 (DR相相液波器2a)(2j))
 Fi第2図(a)に示すように、それぞれ2つの入力
信号の位相差θに応じた信号を出力し、第2の位相検波
器(2b)の出力は・畑θに比例した信号Bを出力する
。このようにして得られた2つの各アナログ出力信号A
、Bについて第1.第2の識別器(3a)(3b)で2
値のディジタル信号に変換することによシ第2図(b)
に示すように、各々周期が2πの矩形状位相比f!5!
特性の出力信号0. Dを得る。これら出力信号O0D
けEX−、NOR論理回路(4)にて排他的論理和をと
ることにより、出力信号C,l)に対し燥り返し故の2
倍の繰シ返し数を持つ矩形波状位相比較特性を有する出
力信号Eを得る。この位相比較特性は位相差2πの間に
2個の位相安定点(位相引込み点)を有する。これより
第1゜第2の位相検波器(2a)(211) Kて検出
された2相PSK信号とv(]0出力との位相差に対し
第2図(C)に示す位相比較特性にて位相誤差信号を発
し、V(10!6)の発振周波数を制御するところで、
2相PSK信号波からペースノ(ンド(Ba5eban
d )・データを復調するためには、同期検波用の基準
搬送波を再生する必要がある。したがって2相PSK信
号波にてデータを伝送する場合、データ伝送部分の前に
搬送波再生用の連続波を設定し、ベースバンドデータを
正確KvlfJI4するだめの所要位相を持つ同期検波
用の基準搬送波を再生する必要がある。従来のディジタ
ル乗算形コスタスループによる2相P8に信号波用基準
搬送波再生装置では位相差2πの間に2個の安定点を有
する位相比較特性を有するため、基準搬送波再生時にお
いて、再生搬送波は上記211Mの安定点のどれか1つ
の安に点に引き込まれ。
1st, 2nd (DR phase liquid wave device 2a) (2j))
As shown in Fig. 2 (a), each outputs a signal according to the phase difference θ between the two input signals, and the output of the second phase detector (2b) outputs a signal B proportional to the field θ. Output. Each of the two analog output signals A obtained in this way
, B. 1st. 2 in the second discriminator (3a) (3b)
Figure 2(b)
As shown in , each rectangular phase ratio f! has a period of 2π. 5!
Characteristic output signal 0. Get D. These output signals O0D
By calculating the exclusive OR in the NOR logic circuit (4), the output signal C, l) is
An output signal E having a rectangular wave phase comparison characteristic with twice the number of repetitions is obtained. This phase comparison characteristic has two phase stable points (phase attraction points) between a phase difference of 2π. From this, the phase difference between the two-phase PSK signal detected by the first and second phase detectors (2a) (211) K and the v(]0 output has the phase comparison characteristic shown in Fig. 2 (C). When controlling the oscillation frequency of V(10!6) by emitting a phase error signal,
From the two-phase PSK signal wave to the pace node (Ba5eban)
d) In order to demodulate data, it is necessary to reproduce the reference carrier wave for coherent detection. Therefore, when transmitting data using a two-phase PSK signal wave, a continuous wave for carrier wave recovery is set before the data transmission part, and a reference carrier wave for synchronous detection with the required phase to accurately KvlfJI4 baseband data is set. Need to play. The conventional two-phase P8 signal wave reference carrier regeneration device using a digital multiplication type Costas loop has a phase comparison characteristic with two stable points between the phase difference of 2π, so when the reference carrier is regenerated, the regenerated carrier wave is It is pulled into a point by one of the stable points of 211M.

常時所要位相の基準搬送波を再生することが不可能とな
る。hわゆる位相アンビギュイティが生ずる。この位相
アンビギュイティを昨去するには、2イロPSK信号波
のキャリア[「)生部とデータ伝送部の間にユニークワ
ード(Unigne Word )を挿入し、2相PS
K信号波の復調器にユニークワードディテクタ (Un
igue Word 1)elector )を附加す
る必?2がある。このことから、従来のディジタル乗算
形コスタスルーズによる基準搬送波再生装置を用いた場
合、2相PSK信号波の復調器は第3図に示す構成とな
る。図eこおいて(8)は信号分波回路、(9)は2相
P8に信号波よりベースバンド波形の波形整形に必要な
ピットタイミングの抽出を行うビットタイミング再生回
路、 (IIは2相1) 8 K信号を横波・波形整形
することにより2411p s +< 1yS号からベ
ースバンドデータを復θ・1するベースバンド抽出回路
、(IIは2相P 8 K信号より検波に必要な1.(
準搬送波を再生する基準搬送波再生時路、0はユニーク
ワードを検出し2位相アンビギュイティがある場合アン
ビギュイティ除去信号を発するユニークワード検出器、
alは位相アンビギュイティがある場合°rンビギ五イ
ティを除去するアンビギュイティ除去回路である。
It becomes impossible to always reproduce the reference carrier wave of the required phase. h So-called phase ambiguity occurs. In order to eliminate this phase ambiguity, a unique word is inserted between the carrier ['') raw part and the data transmission part of the 2-phase PSK signal wave.
A unique word detector (Un
igue Word 1) Is it necessary to add “elector”? There are 2. From this, when using the conventional reference carrier regeneration device using the digital multiplication type Costa Sloose, the demodulator for the two-phase PSK signal wave has the configuration shown in FIG. In Figure e, (8) is a signal branching circuit, (9) is a bit timing regeneration circuit that extracts the pit timing necessary for waveform shaping of the baseband waveform from the signal wave from the two-phase P8, (II is the two-phase 1) A baseband extraction circuit that decodes the baseband data from the 2411ps + < 1yS signal by performing transverse wave/waveform shaping on the 8K signal. (
a reference carrier regeneration circuit for regenerating the subcarrier; 0 is a unique word detector that detects a unique word and emits an ambiguity removal signal when there is a two-phase ambiguity;
al is an ambiguity removal circuit that removes phase ambiguity if it exists.

したがって従来は復調器にユニークワード検出器及びア
ンビギュイティ除去回路が必要であった0 〔発明の概峨〕 この発明は、このような点を鑑みてなされたもので、デ
ィジタル乗算形コスタスルーズにおいて、連続波用の位
相同期ループと2相P8に信号波用の基準搬送波再生回
路とを切替えることにより、常時位相アンビギュイティ
除去が0工能な基準搬送波再生回路を提供するものであ
る。
Therefore, in the past, a unique word detector and an ambiguity removal circuit were required in the demodulator. By switching the phase-locked loop for continuous waves and the reference carrier regeneration circuit for signal waves to the two-phase P8, a reference carrier regeneration circuit that can always eliminate phase ambiguity is provided.

〔発明の実施例〕[Embodiments of the invention]

第4図はこの発明の一実施例を示す。(1)〜(7)は
上記従来装置と全く同一のものである。
FIG. 4 shows an embodiment of the invention. (1) to (7) are completely the same as the conventional device described above.

蝶◆はOR論理l路で、第2の識別回路(3b)の出力
と外部コントロール信号アを人力し、出力信号を13X
−NOル論理回路(4)へ出力する。
The butterfly ◆ is an OR logic circuit, which manually inputs the output of the second identification circuit (3b) and the external control signal A, and converts the output signal to 13X.
-NO Output to logic circuit (4).

搬送波[1)少時には、送信m+は搬送波再生用信号と
して規定されたπ/4の同定位相を持つ連続波が送信さ
れる。この時4準搬送波再生回路は0ル1愉理回路a4
の外ベロコントロール悟硅ア人力を°Fti”レベルと
することにより、V(]0 :6)に加える制御III
信号として第2の識別回路(3b)の出力が加えられる
。その結果、虚準搬送波再生回路は第2図(b)に示す
周期2πの矩形状位相比較特性りを持つ位相同期ループ
となり2位相は唯一の引き込み妥定点であるπ/4の位
相に引き込まれる。搬送波再生用信号姉は、0)L論理
回路な4の外部コントロール1g号ア入力を’、LO”
レベルとすることにより、v O(J F6)に加える
制御信号として第2図1c)に示す回期πの矩形状位相
比較特性Eの制(財)信号が加わシ、2相1) S K
信号波用のノ^準搬込波再生回路となり、以鏝規足され
た固定位相にて4相psK侶号波の暎波を行うだめの基
準搬送波が再生されるO このように、この発明による基準搬送波再生装置を用い
れば、ユニークワード検出器等の付加装置がなくても位
相アンビギュイテイのない基準搬送波が再生でき、2相
P8に信号波用復調器は第5図に示すよう忙簡易化が可
能となる。なお、第5図において(8)は信号分波回路
、(9)はビットタイミング再生回路。
When the carrier wave [1] is small, the transmission m+ is a continuous wave having an identified phase of π/4 defined as a carrier wave regeneration signal. At this time, the 4th subcarrier regeneration circuit is 0 le 1 pleasure circuit a4
Control III added to V(]0:6) by setting the external velocity control Goku's power to the °Fti'' level.
The output of the second identification circuit (3b) is added as a signal. As a result, the virtual quasi-carrier regeneration circuit becomes a phase-locked loop having a rectangular phase comparison characteristic with a period of 2π as shown in Fig. 2(b), and the two phases are pulled into the phase of π/4, which is the only valid point. . The signal for carrier wave regeneration is 0) L logic circuit 4's external control No. 1g A input ', LO'
By setting the level to V O (J F6), a control signal of the rectangular phase comparison characteristic E with period π shown in FIG.
This becomes a quasi-carrying wave regeneration circuit for signal waves, and the reference carrier wave for reproducing the 4-phase PSK signal wave is regenerated at a fixed phase. In this way, the present invention By using the reference carrier wave reproducing device according to the above, it is possible to reproduce the reference carrier wave without phase ambiguity without additional equipment such as a unique word detector, and the signal wave demodulator for the two-phase P8 can be simplified as shown in Fig. 5. becomes possible. In FIG. 5, (8) is a signal branching circuit, and (9) is a bit timing recovery circuit.

alはベースバンド抽出回路、 QOは基準搬送波再生
回路である。
al is a baseband extraction circuit, and QO is a reference carrier recovery circuit.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、ユニークワード検出
器等の付加装置を必要とせずに、位相アンビギュイティ
の生じない搬送波の再生が常時可能となり、2相PSK
信号波用復調器の小型・簡易化も可能となる。
As described above, according to the present invention, it is possible to always reproduce a carrier wave without phase ambiguity without requiring an additional device such as a unique word detector, and
It also becomes possible to downsize and simplify the signal wave demodulator.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のディジタル乗算形コスタスルーズによる
2相PSK信号波用基準搬送波再生回路を示すブロック
図、第2図は第1図の動作波形図、第3図は従来のJ↓
準搬送波再生回路を用いた時の2相P8に信号用復調器
のブロック図、第4図はこの発明忙よる2相PSK信号
波用基準搬送波再生回路の一実施例を示すブロック図、
第5図はこの発明による某jφ搬送波再生回路を用いた
時の2相PSK信号波用復fJ?4iのブロック図であ
る。図中、(1)は信号分波回路。 (2a)(2b)は第t、 第2の位相検波器、(3a
)(:+b)は第1.第2の識別器、(4)はgX−N
otも論理回路、(5)は低域通過フィルタ、(6)は
V(+Q、(71は0−π/2分波回路、(8)は信号
分波回路、(9)はピットタイミング再生回路、GIF
iベースバンド抽出回路、aυは基準搬送波再生回路、
θりはユニークワード検出器、(I3は位相アンビギュ
イティ除去回路、 04)はOR論理回路である。 なお図中、同一あるいは相当部分には同一符号を付して
示しである◎ 代理人 大 岩 増 准 第1図 第3r4 第 4 図
Figure 1 is a block diagram showing a reference carrier regeneration circuit for a two-phase PSK signal wave using a conventional digital multiplication type Costa Sloose, Figure 2 is an operating waveform diagram of Figure 1, and Figure 3 is a conventional J↓
A block diagram of a two-phase P8 signal demodulator when using a quasi-carrier regeneration circuit, FIG. 4 is a block diagram showing an embodiment of a two-phase PSK signal wave reference carrier regeneration circuit according to the present invention,
FIG. 5 shows a two-phase PSK signal wave recovery fJ? when using a certain jφ carrier wave regeneration circuit according to the present invention. 4i is a block diagram. In the figure, (1) is a signal branching circuit. (2a) (2b) is the t-th, second phase detector, (3a
)(:+b) is the first. The second discriminator, (4) is gX-N
ot is also a logic circuit, (5) is a low-pass filter, (6) is V(+Q), (71 is a 0-π/2 branching circuit, (8) is a signal branching circuit, (9) is a pit timing regeneration circuit, gif
i baseband extraction circuit, aυ is reference carrier recovery circuit,
θ is a unique word detector, (I3 is a phase ambiguity removal circuit, and 04 is an OR logic circuit. In the figures, the same or corresponding parts are indicated by the same reference numerals.◎ Agent Masu Oiwa Figure 1 Figure 3r4 Figure 4

Claims (1)

【特許請求の範囲】 2相PSK信号の搬送波周波数に近い発振周波数を持ち
、かつ発振周波数を制御し得る発振器と、上記2相PS
K信号を互いに同相な2つの2相PSK信号に分割する
第1の分波回路と、上記発振器の発振波を一方が他方に
対しπ/2移相した2つの発振波に分割する第2の分波
回路と、上記第1の分波回路により2つに分割された2
相P8に信号の一方と上記第2の分波回路により2つに
分割された発振波のうち入力された発振波からπ/2移
相された発振波との位相差を検出する#!1の位相検波
器と、上記第1の分波回路にて2つに分割された2相P
8に信号の他方と上記第2分波回路釦て2つに分割され
た発振波のうち入力された発振波と同相の発振波との位
相差を検出する第2の位相検波器と。 上記第1の位相検波器の出力信号に対し所定値以上の時
は正の所定電圧を、所定値以下の時は負の所定電圧を出
力することによりアナログ信号を2値のディジタル信号
に変換する第1の識別回路と、上記第2の位相検波器の
出力信号に対し2値のディジタル信号に変換する第2の
識別回路と、上記第1の識別回路より出力されるディジ
タル信号及び上記第2の識別回路より出力されるディジ
タル48号に対しuト他的論理和金取ることによりその
信号の繰し返し数の2倍の繰少返し数を持つ信号の出力
を行うEX−NOR論理回路と、上記EX−NO几論理
回路の出力を低域通過フィルタを介して上記発振器へ加
えてその発振周波数を制御すると共に、上記発振器から
基準搬送波を取り出すようにした基準搬送波再生回路に
おいて、上記第2の識別回路とEX−NO几回路との間
に上記第2の識別回路より出力されるディジタル信号と
外部コントロール、信号に対しOR1埋を取り、その出
力を上記1(X−NOR論理回路に入力させる01Lr
#f8理回路を設けたことを特徴とする基準搬送波再生
回路。
[Claims] An oscillator having an oscillation frequency close to the carrier frequency of a two-phase PSK signal and capable of controlling the oscillation frequency;
a first branching circuit that divides the K signal into two two-phase PSK signals that are in phase with each other; and a second branching circuit that divides the oscillation wave of the oscillator into two oscillation waves, one of which has a phase shift of π/2 with respect to the other. 2 divided into two by a branching circuit and the first branching circuit.
In phase P8, detect the phase difference between one of the signals and the oscillation wave whose phase is shifted by π/2 from the input oscillation wave among the oscillation waves divided into two by the second branching circuit.#! 1 phase detector and the 2-phase P divided into two by the first branching circuit.
8, a second phase detector for detecting the phase difference between the other of the signals and the input oscillation wave and the oscillation wave in the same phase among the oscillation waves divided into two by the second branching circuit button; The analog signal is converted into a binary digital signal by outputting a positive predetermined voltage when the output signal of the first phase detector is above a predetermined value, and outputting a negative predetermined voltage when the output signal is below a predetermined value. a first identification circuit, a second identification circuit that converts the output signal of the second phase detector into a binary digital signal, and a digital signal output from the first identification circuit and the second identification circuit; An EX-NOR logic circuit which outputs a signal having twice the number of repetitions of the signal by taking an altruistic logical sum on the digital No. 48 outputted from the identification circuit. , in the reference carrier regeneration circuit, which applies the output of the EX-NO logic circuit to the oscillator via a low-pass filter to control its oscillation frequency, and extracts the reference carrier from the oscillator; The digital signal output from the second identification circuit and the external control signal are ORed between the identification circuit and the EX-NO logic circuit, and the output is input to the 1 (X-NOR logic circuit). Let 01Lr
#A reference carrier regeneration circuit characterized by being provided with an f8 logic circuit.
JP58215244A 1983-11-16 1983-11-16 Reference carrier regenerating circuit Pending JPS60107955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58215244A JPS60107955A (en) 1983-11-16 1983-11-16 Reference carrier regenerating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58215244A JPS60107955A (en) 1983-11-16 1983-11-16 Reference carrier regenerating circuit

Publications (1)

Publication Number Publication Date
JPS60107955A true JPS60107955A (en) 1985-06-13

Family

ID=16669104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58215244A Pending JPS60107955A (en) 1983-11-16 1983-11-16 Reference carrier regenerating circuit

Country Status (1)

Country Link
JP (1) JPS60107955A (en)

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