JPS6010774A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6010774A JPS6010774A JP11908083A JP11908083A JPS6010774A JP S6010774 A JPS6010774 A JP S6010774A JP 11908083 A JP11908083 A JP 11908083A JP 11908083 A JP11908083 A JP 11908083A JP S6010774 A JPS6010774 A JP S6010774A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- type
- inp
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 16
- 239000000969 carrier Substances 0.000 abstract description 5
- 230000001052 transient effect Effects 0.000 abstract description 5
- 238000005275 alloying Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000005192 partition Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 240000002329 Inga feuillei Species 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置に係り、特に価電子帯にスパイク状
の障壁を設けたＰＮＰ型へテロ接合トランジスタに関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a PNP type heterojunction transistor in which a spike-like barrier is provided in the valence band.
（２）技術の背景
従来、バイポーラ型のトランジスタのスイッチング時間
の高速化を図るためには次式で表わされるスイッチング
時間（τＳ）が小さくなる様に工夫していた。(2) Background of the Technology Conventionally, in order to speed up the switching time of bipolar transistors, efforts have been made to reduce the switching time (τS) expressed by the following equation.
ここでＲし：ベース抵抗Ｉ ＣＣコレクタ容量ＣＬ：負
荷容量ＩＲＬ’負荷抵抗、τし ：ベース中少数キャリ
ヤのトランジェントクイムで表わせる。Here, R: base resistance I CC collector capacitance CL: load capacitance IRL' load resistance, τ: expressed by the transient quim of minority carriers in the base.
上式から高速のスイッチング時間τＳを得るにはバイポ
ーラトランジスタベース抵抗Ｒ）を小さくシ、且つベー
ス中の少数キャリヤのトランジェントタイムτ−を短く
する必要があることが解る。From the above equation, it can be seen that in order to obtain a high-speed switching time .tau.S, it is necessary to make the bipolar transistor base resistance R) small and to shorten the transient time .tau.- of minority carriers in the base.
（３）従来技術の問題点
上記したＲ１の値を小さくするためにはベース領域の面
積を小さくし微細加工技術によってトランジスタの寸法
を微細化すると共にトランジスタのベース領域の厚さを
小さくして電子がベースを通過する時間、即ちτＳを短
くする努力が払われている。(3) Problems with the conventional technology In order to reduce the above-mentioned value of R1, the area of the base region is reduced and the dimensions of the transistor are miniaturized using microfabrication technology, and the thickness of the base region of the transistor is also reduced. Efforts are being made to shorten the time it takes for τ to pass through the base, ie, τS.
ベースを微細化するためには従来のトランジスタ形成工
程に３枚のホトマスクを用いてホトエツチングによる３
回の加工を必要とするのでホトマスクの位置合せに一定
の誤差を持つ分だけ余裕を持った設計を行なう必要があ
りベースの縮小には限界があったがセルファライニング
（ｓｅｌｆ −ａｌｔｇｎｉｎｇ）技術により１回のホ
トマスク即ちホトエツチングを用いた５ｕｐｅｒ ５ｅ
ｌｆ ａｌｉｇｎｅｄ ＰｒｏｃｅｓｓＴｅｃｈｎｏａ
ｌｏｇｙ （ＳＳＴ ）等が提案され従来のブレーナ型
トランジスタに比べてベース領域の大きさを１／３に縮
小し、伝搬遅延時間６３ピコ秒／ゲートを得た報告がな
されているが微細化してベース領域を小さくするには現
在の技術では限界に達しているのが現状である。In order to miniaturize the base, three photomasks are used in the conventional transistor forming process, and three
Since this process requires several times of processing, it is necessary to design with a margin for a certain error in the alignment of the photomask, and there is a limit to the reduction of the base. 5upper 5e using multiple photomasks or photoetching
lf aligned Process Technoa
Logic (SST) etc. have been proposed, and it has been reported that the size of the base region was reduced to 1/3 compared to the conventional Brainer type transistor, and a propagation delay time of 63 picoseconds/gate was obtained. Currently, the current technology has reached its limit in reducing the area.
（４）発明の目的
本発明は上記従来の欠点に鑑みなされたものでベース抵
抗Ｒｂを下げるためにベース部に移動度の高いｎタイプ
の半導体を用いるとともにエミッタ・ベース接合部の価
電子帯にスパイク状の障壁を設は該障壁を本来移動度の
低いホールを通過させる事により、高速のホールをベー
スに注入し、少数キャリヤのトランジェントタイムτし
の減少を図った半導体装置を提供することを目的とす
るものである。(4) Purpose of the Invention The present invention has been made in view of the above-mentioned drawbacks of the conventional technology.In order to lower the base resistance Rb, an n-type semiconductor with high mobility is used in the base part, and the valence band of the emitter-base junction is By providing a spike-shaped barrier and allowing holes with originally low mobility to pass through the barrier, high-speed holes are injected into the base, thereby providing a semiconductor device in which the transient time τ of minority carriers is reduced. This is the purpose.
（５）発明の構成
上記目的は本発明によればエミッタとベース間のヘテロ
接合面の価電子帯にスパイク状の障壁を形成し、該障壁
を乗り越えた初速のついた高速なホールを上記ベースへ
注入するようにしたことを特徴とするＰＮＰへテロ接合
の半導体装置を提供することによって達成される。(5) Structure of the Invention According to the present invention, the above object is to form a spike-shaped barrier in the valence band of the heterojunction surface between the emitter and the base, and to transfer high-speed holes with an initial velocity that have overcome the barrier to the base. This is achieved by providing a PNP heterojunction semiconductor device characterized by implantation into a PNP heterojunction.
（６）発明の実施例 以下本発明の一実施例を図面について詳記する。(6) Examples of the invention An embodiment of the present invention will be described in detail below with reference to the drawings.
第１図は本発明の動作時のエネルギーバンド図を示すも
ので具体的にはＰ−１ｎＰ ／ ｎ−ＩｎＧａＡｓ／
Ｐ−ＩｎＧａＡｓのへテロ構造を有する化合物半導体に
ついて説明する。FIG. 1 shows an energy band diagram during operation of the present invention, specifically, P-1nP/n-InGaAs/
A compound semiconductor having a P-InGaAs heterostructure will be described.
上記のＰ型のＩｎＰで構成されたエミッタとｎ型のＩｎ
ＧａＡｓで構成したベースが順方向にバイアスされると
通常ホールはベース中に注入されるが、第１図に示すよ
うにベース・エミッタ接合を急峻部４をなすようにする
と価電子帯にスパイク状の障壁２が生じるためにホール
１は上記障壁２を越えたものしかベース領域に注入され
ないためにホール１の持つポテンシャルエネルギーは運
動エネルギーに変換されてベース中を５ Ｘ １０りｃ
ｍ ／ ｓｅｃの初速度を持って５００人厚０ベース中
を０．１ピコ秒程度で通過する。又、ベース部分がｎ−
１ｎＧａＡｓで構成されているので電子の移動度は太き
（なり、ベース抵抗Ｒｈは小さくなる。更にベース中の
少数キャリヤのトランジェントタイムτし について考
察した場合、ホールは元来移動度が低いとされているが
障壁２を形成して初速度を持ったホールをベースへ注入
すればスイッチング時間τＳの早いＰＮＰへテロ接合バ
イポーラトランジスタを得ることが出来る。The above emitter made of P-type InP and n-type InP
When a base made of GaAs is forward biased, holes are normally injected into the base, but if the base-emitter junction is made to form a steep part 4 as shown in Figure 1, a spike-shaped hole is injected into the valence band. Since the barrier 2 is generated, only the hole 1 that exceeds the barrier 2 is injected into the base region, so the potential energy of the hole 1 is converted into kinetic energy and flows through the base as 5 x 10
It has an initial velocity of m/sec and passes through a 500-person thick zero base in about 0.1 picosecond. Also, the base part is n-
Since it is composed of 1nGaAs, the mobility of electrons is high (and the base resistance Rh is small.Furthermore, when considering the transient time τ of minority carriers in the base, it is assumed that holes have originally low mobility. However, if a barrier 2 is formed and holes with an initial velocity are injected into the base, a PNP heterojunction bipolar transistor with a fast switching time τS can be obtained.
なお、エミッタにＰ−１ｎＰをベースにＮ −Ｉｎ Ｇ
ａＡｓを選択すると上記したスパイク状の障壁２は０．
４８ｅＶ、伝導帯のエネルギー差４は０．１１ｅＶとな
る。In addition, N-In G based on P-1nP is used as the emitter.
When aAs is selected, the spike-shaped barrier 2 described above becomes 0.
48 eV, and the conduction band energy difference 4 is 0.11 eV.
尚、第１図で３は電子を５はフェルミレベルを示す。In FIG. 1, 3 indicates an electron and 5 indicates a Fermi level.
上記したバイポーラ型のＰＮＰへテロ接合トランジスタ
の構造の一実施例を第２図に示す。An example of the structure of the above bipolar type PNP heterojunction transistor is shown in FIG.
第２図に於て６はＩｎＰのＰ十 基板であり気相成長法
により上記基板６上に第１層目のＰ型のＩｎＧａＡｓ層
７を形成し、更に該Ｐ型−Ｉｎ ＧａＡｓ層上にｎ型５
−
ＯＴｎＧａＡｓ層８を更にその上にＰ型のＩｎＰ層９を
形成し、第３層目のＩｎＰ層のエミッタ領域を残して第
２層目のｎ型ＩｎＧａ’ＡｓＮ迄エツチング９ａ、９ｂ
を施してベース電極と成るＡｕＧｅ／Ａｕの電極１１．
１２を第２Ｎ目のｎｌｎＧａＡｓ層８上に形成しアロう
イングしオーミックコンタクトを取ってベースと成し、
第３Ｎ目のＰ型１ｎＰ層９並びにｐ中型ＩｎＰ ６の裏
面にＡｕ／ Ｚｎ／ Ａｕの電極１０．１３を形成して
オーミックをとってエミッタ及びコレクタ電極とするこ
とでＰＮＰへテロ接合バイポーラトランジスタが構成で
きる。In FIG. 2, reference numeral 6 denotes an InP substrate, and a first P-type InGaAs layer 7 is formed on the substrate 6 by vapor phase growth, and then a first P-type InGaAs layer 7 is formed on the P-InGaAs layer. n-type 5
- A p-type InP layer 9 is further formed on the OTnGaAs layer 8, and etched to the second n-type InGa'AsN layer 9a, 9b, leaving the emitter region of the third InP layer.
An AuGe/Au electrode 11. is applied to form a base electrode.
12 is formed on the 2N-th nlnGaAs layer 8 and arrowed to form an ohmic contact to form a base,
A PNP heterojunction bipolar transistor is formed by forming Au/Zn/Au electrodes 10.13 on the back surface of the 3N-th P-type 1nP layer 9 and the p-medium InP 6 and using them as emitter and collector electrodes with ohmic properties. Can be configured.
上記構成で第２層目のｎ−Ｉｎ ＧａＡｓ層８と第３層
のＰ−１ｎＰ層９とのＰＮ接合を気相成長装置によって
急峻に形成するための一実施例を第３図及び第４図につ
いて説明する。An example of steeply forming a PN junction between the second n-In GaAs layer 8 and the third P-1nP layer 9 using a vapor phase growth apparatus in the above configuration is shown in FIGS. 3 and 4. The diagram will be explained.
第３図及び第４図は上記気相成長装置を示す側断面図で
ある。FIGS. 3 and 4 are side sectional views showing the vapor phase growth apparatus.
上記気相成長装置は第１の領域１４と第２の領域１５を
有し、第１の領域１４には１ｎ１６が設けられ、管１７
からはＬとＰＣＩＩ ３のガスが導入６−
される。The vapor phase growth apparatus has a first region 14 and a second region 15, the first region 14 is provided with 1n16, and the tube 17 is provided with 1n16.
L and PCII 3 gases are introduced from 6-.
一方第２の領域１５にはＧａ１８が設けられており管６
からはＨ２とＡｓＣ１２３ガスが導入される。On the other hand, Ga 18 is provided in the second region 15 and the tube 6
H2 and AsC123 gas are introduced.
領域１４と領域１５間には区切り板２０が設けられてお
り更には基板２１としては第２図に示す基板６上に第１
層目のＰ−ＩｎＧａＡｓ層７が形成されたものが配置さ
れているとする。上記基板２１を配置した基板ホルダー
２２は気相成長装置内で前後に移動可能に設けられてい
る。第３図では基板２１はガス流の下流方向に引いてい
るため基板２１には領域１４．１５を流れる反応ガスが
接触して基板２１上にＩｎＧａＡｓの気相成長が行われ
ている。次に第４図に示すように基板ホルダー２２をガ
ス流の上流に移動させ区切り板２０に対接させると領域
１４の反応ガスのみ基板２（に接触しＩｎＰが成長する
。A partition plate 20 is provided between the area 14 and the area 15, and furthermore, a partition plate 20 is provided as a substrate 21 on a substrate 6 shown in FIG.
It is assumed that a P-InGaAs layer 7 is formed thereon. A substrate holder 22 on which the substrate 21 is placed is provided so as to be movable back and forth within the vapor phase growth apparatus. In FIG. 3, since the substrate 21 is drawn in the downstream direction of the gas flow, the reactive gas flowing in the region 14.15 comes into contact with the substrate 21, and InGaAs is vapor-phase grown on the substrate 21. Next, as shown in FIG. 4, when the substrate holder 22 is moved upstream of the gas flow and brought into contact with the partition plate 20, only the reaction gas in the region 14 comes into contact with the substrate 2, and InP grows.
このように気相成長させるとＰ−ＩｎＰ層とｎ−ＩｎＧ
ａＡｓ層間のへテロ接合面を急峻にすることが可能とな
る。即ち従来ではＮ型のＩｎＧａＡｓ層成長後に次のガ
ス吹き込みまでＩｎＧａＡｓ層の形成された基板２１を
待機させる待機法を取っているためにその間に基板上に
成長したＩｎＧａＡｓ層が劣化していたが本発明でガス
の切換えを機械的なシャッタ構造で行なうためにヘテロ
接合面を急峻にすることが出来る。By vapor phase growth in this way, a P-InP layer and an n-InG layer are formed.
It becomes possible to make the heterojunction surface between the aAs layers steep. In other words, in the past, after the growth of the N-type InGaAs layer, the substrate 21 on which the InGaAs layer was formed was kept on standby until the next gas injection, which caused the InGaAs layer grown on the substrate to deteriorate during that time. In the invention, the heterojunction surface can be made steep in order to perform gas switching using a mechanical shutter structure.
（７）発明の効果
本発明は叙上の如く構成し動作させたのでベース部分の
ｎ型半導体によってベース抵抗Ｒ）を小さくすることが
出来ると共にエミッタ、ベース間の接合を急峻にし、こ
れら接合部の価電子帯にスパイク状の障壁を形成したの
で初速の与えられたホールをエミッタ、ベース間に通過
させることが出来るのでスイッチング特性が０．１ピコ
秒程度のバイポーラ型ＰＮＰ ）ランジスタを得ること
が出来る結果を有する。(7) Effects of the Invention Since the present invention is configured and operated as described above, it is possible to reduce the base resistance (R) by using the n-type semiconductor in the base portion, and also to make the junction between the emitter and the base steep. Since a spike-shaped barrier is formed in the valence band of the transistor, holes with a given initial velocity can pass between the emitter and the base, making it possible to obtain a bipolar PNP transistor with switching characteristics of about 0.1 picoseconds. have possible results.
第１図は本発明の半導体装置の動作時のエネルギーバン
ド図、第２図は本発明の半導体装置の一実施例を示す側
断面図、第３図及び第４図は本発明の半導体装置を気相
成長法で得る場合の気相成長装置の動作を説明する側断
面図である。
１・・・ホール ２・・・スパイク状障壁 。
３・・・電子 ４・・・急峻部
６・・・基板 ７ ・・・Ｐ−ＩｎＧａＡｓ層 ８・・
・ｎ−ＩｎＧａＡｓ層 ９・・・Ｐ−１０２層１０・・
・エミッタ電極 １１．１２・・・ベース電極 １３・
・・コレクタ電極
１４．１５・・・第１及び第２領域
１６・・・ＩｎＰ １８・・・Ｇａ ２１・・・基板
９−
第２図FIG. 1 is an energy band diagram during operation of the semiconductor device of the present invention, FIG. 2 is a side sectional view showing an embodiment of the semiconductor device of the present invention, and FIGS. 3 and 4 are diagrams showing the semiconductor device of the present invention. FIG. 3 is a side sectional view illustrating the operation of a vapor phase growth apparatus when obtaining by a vapor phase growth method. 1...Hole 2...Spike-like barrier. 3...Electron 4...Steep part 6...Substrate 7...P-InGaAs layer 8...
・n-InGaAs layer 9...P-102 layer 10...
・Emitter electrode 11.12...Base electrode 13・
...Collector electrode 14.15...First and second region 16...InP 18...Ga 21...Substrate 9- FIG.
Claims (1)
ク状の障壁を形成し、該障壁を乗り越えた初速のついた
高速なホールを該ベースに注入するようにしたことを特
徴とするＰＮＰへテロ接合の半導体装置。A PNP characterized in that a spike-shaped barrier is formed in the valence band of the heterojunction surface between the emitter and the base, and high-speed holes with an initial velocity that overcome the barrier are injected into the base. Terojunction semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11908083A JPS6010774A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11908083A JPS6010774A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6010774A true JPS6010774A (en) | 1985-01-19 |
Family
ID=14752379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11908083A Pending JPS6010774A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010774A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62229878A (en) * | 1986-03-04 | 1987-10-08 | Fujitsu Ltd | High speed semiconductor device |
| US5206524A (en) * | 1988-09-28 | 1993-04-27 | At&T Bell Laboratories | Heterostructure bipolar transistor |
| US5283448A (en) * | 1989-11-29 | 1994-02-01 | Texas Instruments Incorporated | MESFET with indium gallium arsenide etch stop |
| US5925783A (en) * | 1994-11-17 | 1999-07-20 | Bayer Aktiengesellschaft | Process for the preparation of isocyanates |
| US6188137B1 (en) * | 1995-05-25 | 2001-02-13 | Sharp Kabushiki Kaisha | Ohmic electrode structure, semiconductor device including such ohmic electrode structure, and method for producing such semiconductor device |
| US7851648B2 (en) | 2002-12-19 | 2010-12-14 | Basf Aktiengesellschaft | Method for the continuous production of isocyanates |
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|---|---|---|---|---|
| JPS4943583A (en) * | 1972-08-30 | 1974-04-24 | ||
| JPS4998970A (en) * | 1973-01-24 | 1974-09-19 | ||
| JPS5185677A (en) * | 1975-01-27 | 1976-07-27 | Hitachi Ltd | WAIDOGYATSU PUEMITSUTATORAN JISUTA |
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- 1983-06-30 JP JP11908083A patent/JPS6010774A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4943583A (en) * | 1972-08-30 | 1974-04-24 | ||
| JPS4998970A (en) * | 1973-01-24 | 1974-09-19 | ||
| JPS5185677A (en) * | 1975-01-27 | 1976-07-27 | Hitachi Ltd | WAIDOGYATSU PUEMITSUTATORAN JISUTA |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62229878A (en) * | 1986-03-04 | 1987-10-08 | Fujitsu Ltd | High speed semiconductor device |
| US5206524A (en) * | 1988-09-28 | 1993-04-27 | At&T Bell Laboratories | Heterostructure bipolar transistor |
| US5283448A (en) * | 1989-11-29 | 1994-02-01 | Texas Instruments Incorporated | MESFET with indium gallium arsenide etch stop |
| US6057567A (en) * | 1989-11-29 | 2000-05-02 | Texas Instruments Incorporated | Integrated circuit and method |
| US5925783A (en) * | 1994-11-17 | 1999-07-20 | Bayer Aktiengesellschaft | Process for the preparation of isocyanates |
| US6188137B1 (en) * | 1995-05-25 | 2001-02-13 | Sharp Kabushiki Kaisha | Ohmic electrode structure, semiconductor device including such ohmic electrode structure, and method for producing such semiconductor device |
| US7851648B2 (en) | 2002-12-19 | 2010-12-14 | Basf Aktiengesellschaft | Method for the continuous production of isocyanates |
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