JPS60105313A - Time separable variable equalizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time-discrete variable fixture based on Soede's principle of a constant resistor, which has a constant-resistance bridge circuit terminated with a variable resistor.

Problems to be Solved by the Invention In the technical fields mentioned at the beginning (e.g. sound studio technology; bass and treble adjustment, presence filters), attenuation characteristics that are symmetrical to the basic attenuation process are based on the basic attenuation process. The problem of setting (fan-like characteristics) often arises. In this case, the deviation from the basic damping profile (which does not necessarily have to be constant) must be symmetrical both in the direction of large damping quantities and in the direction of small damping quantities. Furthermore, the fan-like extent must be strictly proportional to one edge of the fan-like extent. This is schematically illustrated in FIG.

The problems of the present invention are as follows: a change in the parameter 1 as small as possible, a change in the damping characteristic symmetrical to the basic attenuation (fan-shaped characteristic Faa
heroharakterietik) is obtained,
The object of the present invention is to provide a time-discrete variable equalizer of the type mentioned at the beginning.

First means for solving the problem According to the present invention, this problem is solved by the following configuration. That is, the reflectance of a constant resistance bridge circuit terminated with a resistor is converted into a series circuit of a multiplier with adjustable coefficients and a reflectance having only one of the two bridge impedances of said bridge circuit, according to the wave digital filter principle. In the case of a fixture in which a constant resistance bridge circuit is arranged with a series impedance in a series branch with a series impedance, the series impedance is constituted by a 3/-to parallel adapter; In the case of a terminal equalizer in which the corresponding terminal pairs of a three-point parallel adapter are terminated with a reflector system with a series impedance, and a constant resistance bridge circuit is provided with a parallel impedance in the parallel branch with said parallel impedance. , the parallel impedance is configured by a 3-point series adapter, and the corresponding terminal pair of the 3-point series adapter is connected to the parallel impedance tOW.
Connect another first 3-boat adapter between the human-powered boat and the output port;
3. branching the second 3/-t parallel adapter or the second 3/1-t series adapter from the fr-) adapter;
Furthermore, this first 3-port adapter is configured as a *v, y-) series adapter or a 3-to-1 parallel adapter.

Effects of the Invention The configuration of the present invention as set forth in claim 1 provides the following advantages over conventional variable equalizers. In other words, the structure of the I-de fixture can also be used for time-discrete amplitude continuous signals! Then, the frequency characteristics can be changed simply by changing the coefficient of the multiplier, the complementary frequency characteristics can be simply differentiated by the sign of this coefficient, and the equalizer can be automatically adjusted to the transmission interval to be equalized. There is a very suitable structure 1, in which only the coefficients need to be adjusted, 1 for the whole area of the sector characteristic curve, from -1 to +
It is only necessary to change the coefficients up to 1, and the device of the present invention can also be used for time-continuous and value-continuous signals.

A second means to solve the problem is based on the wave digital filter theory explained above.
- In the fixture structure 1, a loop without delay is formed. This cannot be realized by digital signal processing 1. Therefore, the second problem of the present invention is to find a method that is suitable for digital signal processing and that requires only a random change as much as possible to achieve the desired fan-like characteristic. The purpose of this invention is to provide the structure of a de-equalizer.

This problem is solved by the second aspect of the present invention described in claim 3.
According to the configuration of the first configuration of the present invention, the three-point parallel adapter that configures the series impedance or the three-point series adapter that configures the parallel impedance, the multiplier, and the multiplier are connected in series. A third three-point one-port circuit having seven rectances in the series circuit to the multiplier is provided with one input port and one output port, and an input signal terminal is provided at the input yjt'-) and the output port, respectively. and a terminal for an output signal, and the two-port circuit has two port parallel branches and two port series branches, each of the two port series branches being connected from the input signal terminal of one port. of the other yl? signal through the branch point and then through the adder. -), and the parallel branches of both ports are connected in opposite directions to one ttr-
) from the branch point of the series branch to the adder or one signal of the other boat series branch, and in this case at least one of the series branches of both ports and at least one of the parallel branches of both ports. The solution is to provide one multiplier for each.

Effects of the Invention The configuration of the present invention as described in claim 3 has the following advantages. That is, since digital signal processing is possible and the 7g-de equalizer operates according to the principle of a wave digital filter, there is no problem with stability; that is, any coefficient β ((-1, +1) is stable. A situation arises.

Furthermore, it is only necessary to change three coefficients to form the sector characteristic, and this does not depend on the overall grade of the L-de equalizer. This significantly reduces the number of coefficients to be stored in the case of a variable equalizer with a large number of intermediate stages.

BACKGROUND OF THE INVENTION The solution according to the invention is based on the principle of a wave digital filter, which principle A.

7etweia' Digital Filter
5truaturea Re1a-teki to 0
1aasioal Filter Networka
' Am U25. 1971, page X) 79-89,
and Federal Republic of Germany Patent Application Publication No. 2027303
There is a publicly known version f from the publication No. As an analog reference filter, for example, a known 2-D equalizer structure (FIG. 2 of the drawings of the present specification) shown in FIG. 11 of US Pat. No. 2,096,027 is used.

In FIG. 2, M is a non-reflection auxiliary four-terminal circuit having characteristic impedance R0, and a=eaB0↑. Confusion. is the level of fundamental attenuation of the Nenozo unit f in FIG. The non-reflective auxiliary four-terminal circuit can be represented, for example, as a bridge having impedances z1 and z2, as shown in FIG. In the auxiliary four-terminal circuit of FIG. 3, output ports 4 and -4 are terminated with variable resistors ~f. The bridge impedances 21 and 22 are connected to the f1 terminals 3 and 3, which are paired with each other. -3 to terminal 4. The transmittance to -4 can be expressed as follows when matching (that is, when R, = Ro): 543-->Cs, -52)=syu=S1.

This is the case. Terminal 4. If -4 is terminated with a resistor ~, then terminal 3
．． For the reflectance of -3, the following formula % formula % At that time, -1 = β = +11, when Rv = 0 (short circuit), β = -1 R, = Ro (1M connection), β - 〇Rv = Co (No load), β=+1.

Therefore, according to the wave digital filter principle shown in the article by A. Fettweis, a filter having a structure suitable for time-discrete processing can be obtained in place of the reference filter of FIG. This is schematically illustrated in FIG. S in FIG. 4 represents the reflectance of impedance z1 (FIG. 31). (2) is a 3-point parallel adapter with a wave sync on the output side, and (2) is a 3-point parallel adapter 1.

Example Next, an embodiment of the equalizer of the present invention will be described.

EMBODIMENT OF THE FIRST CONFIGURATION OF THE INVENTION In the time-continuous (analog) circuit of a 2-de equalizer with characteristic impedance R8 in FIG. 2, a = 2.
Then, the circuit shown in FIG. 5a is obtained. The bridge impedances 21 and 22 are configured as shown in FIGS. 5b to 5c. The carp is F−jψ=j, which is known from the theory of wave digital filter of A, Fattyθ1 day.
Let the frequency variable have the relationship “°”ξ, where f=
Commercial frequency, fA = sampling frequency t for time-discrete signal processing. Which bridge impedance zs (sth
b) or z2 (Fig. 5c) based on the reflection coefficient S(
The circuit shown in Fig. 6 (2,
(when z2 is used) or the circuit shown in FIG. 7 (when z2 is used) is constructed.

The symbols of adapters ■ to ■ in FIGS. 6 and 7 are, for example,
The one described in the publication was used. A detailed circuit diagram is also shown in this publication. Two constituent units) II and ■
together form a single delay-free loop. The illustrated structure is therefore suitable only for time-discrete S-width continuous signal processing.

Both circuits have complementary characteristics with respect to operational damping. This is shown in FIGS. 8 and 9.

The fan-shaped characteristics shown here are R0=1Ω, RL--=1
The coefficient β as a group A parameter of grade 2 for Ω
f was measured in an example of a time-discrete zeta equalizer in which f is used.

FIG. 10 shows a dual type zeta equalizer for the circuit of FIG. 5a. A corresponding equalizer of the present invention is schematically shown in FIG.

FIG. 12 shows an embodiment of the unit structure of a circuit of a zeta equalizer according to the wave digital filter principle for time-discrete amplitude continuous signals.

12 in FIG. 12 and 2 in FIG. 12 correspond to a zeta equalizer in which the series impedance is provided in a series branch with a constant resistance bridge circuit.

12 is a circuit corresponding to the parallel connection of the preferably purely resistive series impedance 2Ro of the I-D equalizer of FIG. 5a and the ohmic parallel impedance R8 of FIG. 5b. Similarly, 2 in FIG. 12 is a circuit f corresponding to the parallel connection of 2R0 (FIG. 5a) and an ohmic series resistor R8 (FIG. 5C). β denotes a multiplier with a variable coefficient β, that is, a fan-like characteristic. Are numbers 3 in Figure 12 and 4 in Figure 12 dual-type in meaning? This corresponds to the circuit 1 of the I-D equalizer (FIG. 10), in which a parallel impedance is provided in the parallel branch of the I-D equalizer together with a bridge circuit.

Embodiment of the second configuration of the present invention Claim 3 describes a circuit that can digitally process the unit structure shown in FIG. 12 (see FIG. 12). The adapters 1 and 2 that have been replaced are adapters H to ■ in the explanation of Figs.
). However, in this case no delay-free loop is formed.

According to the second configuration of the present invention, each of the circuits shown in 1 to 4 of FIG. 12 can be realized by ten different circuit structures. These structures are shown at a=k in FIG.

The magnitude of the multiplication coefficient (1) δ4 shown in FIG. 13 is preset as follows (coefficient (1) δj in FIG.
1 on the left shoulder corresponds to each of the four structures in FIG. 12). First, (1)a, (1)a3. (2) a(2) 11 α3 is the coefficient of 1 in FIG. 12 calculated according to the theory of the wave digital filter 5 (here, 1 indicates the coefficient 1 on the left shoulder, and 2 indicates the adapter 2. ). At this time, the following equation is obtained.

In that case, A=1-β(]-(1)α3”)CI-(2)α□)
(4) Fan-shaped characteristic/ξ parameter β can be changed by 1 between -1 and +1. The coefficients of FIG. 13 are applied to the four structures of FIG. 12 in the following form.

Structure 1: (1) δ − δ 1 (1) δ = δ (5) 2 2 (1) δ − δ 3 Structure 2: (2) δ = δ 1 (2) δ −−δ (6) 2 ( ') δ3=-δ3 Structure 3. (3) δ −−δ1 ! (Sδ = δ 2 □ (7) (S δ = −δ3 Structure 4: (S δ = −δ 1 (S δ = −22 2(8) (“) δ = −δ3 Figure 14 shows (6) (corresponding to the figure) shows an example of an equalizer of grade 20I-de, which is a basic circuit type for time-discrete signal processing, in which the delay element produces a delay of the reciprocal of the sampling rate. ~ and RI are the above A, ]
This is a terminating resistor based on Fettweia's wave particle filter theory.

FIG. 15 shows an embodiment corresponding to FIG. 14 using the wave 2 port circuit of FIG. 13a, and in the circuit of FIG. 15, the circuit part st of FIG. circuit is used.

In the circuit shown in FIG. 15, the following equation holds true according to equations (1) to (8) above.

FIG. 16 shows the fan-like characteristic of attenuation (1β1≦1) when Ro = 1Ω in the circuit in FIG. 15.
At that time, each coefficient is also shown.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the attenuation characteristics of a known Gesode equalizer in units of 1 square, Fig. 2 is a circuit diagram of a known Gesor equalizer, and Fig. 3 is a non-reflection auxiliary 4-terminal diagram. A circuit diagram of the circuit, FIG. 4 is a block circuit diagram of a time-discrete variable equalizer according to the present invention, FIG.
Figure a is a circuit diagram of the circuit in Figure 2 when a=2, and Figure 5b is a diagram. FIG. 5c is a circuit diagram of the bridge impedance, and FIGS. 6 and 7 each show an impedance of 2.5 cm for the reflectance of the circuit of FIG. 8 is a diagram showing the fan-shaped characteristic of the circuit in FIG. 5b, FIG. 9 is a diagram showing the fan-shaped characteristic of the circuit in FIG. 5c, and 10. 1.2.3 of FIG. 12; FIG. 11 is a block diagram of an equalizer according to the invention corresponding to the circuit of FIG. 1O; FIG. ．．
4 is a block circuit diagram showing four different structures of adapters (red to black) in Geso's equalizer for time-discrete amplitude continuous signals according to the present invention; FIG. 13;
FIG. 14 is a circuit diagram showing 11 embodiments for configuring the circuit shown in FIG. 4 into a circuit for digital signal processing, and FIG. FIG. 15 is a block circuit diagram of an embodiment in which the circuit portion St of FIG. 14 is configured using the two-bottom circuit of FIG. FIG. 3 is a diagram showing fan-shaped attenuation characteristics when RL=Ro=19 of the equalizer for use. ~...variable resistance, M...constant resistance bridge circuit, 2.
. z2...Bridge impedance, 2R...Series in 0 beadance, Ro/IL...Parallel impedance, 1
, I', II, II', III, In'
・7 days, 1, -1 ・-person I-to, 2. -2...
・Output port, W... Wave sync, β... Multiplier or multiplication coefficient, (1) δ... Multiplication coefficient FIG, 2 Fl (i, 4 Procedural amendment (method) December 1980 2C Mr. Commissioner of the Japan Patent Office 1, Indication of the case Patent Application No. 170545 of 1982 2
, Name of the invention Time-discrete variable equalizer 3, Person making the amendment Relationship with the case: Patent applicant 4, Agent November 27, 1980 (Shipping date) 6. Subject of the amendment

Claims (1)

[Claims] 1. In a time-discrete variable equalizer based on the Deso equalizer principle, having a constant resistance bridge circuit terminated with a variable resistance (Rv), the resistance (Rv)! The reflectance of the terminated constant resistance bridge circuit (M) is changed according to the wave digital filter principle, with a multiplier with an adjustable coefficient and only one of the two bridge impedances (21 or 22) of said bridge circuit (M). It consists of a series circuit with a reflexance (S), and a constant resistance bridge circuit (M) has a series impedance (2R
o), in the case of a deso equalizer installed in a series branch with the series impedance, the series impedance (2R0) is constituted by a 3-point parallel adapter (II), in which case the 3-point parallel adapter (II) The corresponding terminal pair of the parallel adapter (II) is terminated with a reflexance 1 having a series impedance, and a constant resistance bridge circuit (M) terminates the parallel impedance (R0
/&), and in the case of an I-de equalizer provided in a parallel branch with said parallel impedance, the parallel impedance (Ro/a) is constituted by a 3-point series adapter (n), in which case The corresponding terminal pairs of the 3-point series adapter (II) are reflectance-terminated with parallel impedance, and another first 3-point terminal is connected between the input port (1, -1) and the output port (2, -2). Connect the port adapter and the first 3
port adapter to the second 3-vote parallel adapter (
II) or a second 3-point series adapter (■'), and further convert this first 3-port adapter into a 3-point series adapter (1) or a 3-point parallel adapter (I).
′). 2. In case of pure resistive series impedance (2Ro) or pure resistive parallel impedance (Ro/a), the corresponding value of the second 3&-) parallel adapter (II) or the second 3-point series adapter (1) Wave sync the terminal (
A time-discrete variable equalizer according to claim 1, wherein the time-discrete variable equalizer terminates in W). 3. According to the wave digital filter principle, the reflectance of the constant resistance bridge circuit (M) terminated with a resistor (Rv) ffi is determined by a multiplier with an adjustable coefficient and one of the bridge impedances of the bridge circuit (M). It consists of a series circuit with a reflexance (S) having only Z□ or 22), and a constant resistance bridge circuit (M) has a series impedance (2R
0), and in the case of an equalizer provided in a series branch having the series impedance, the series impedance (2R0) is configured by a 3-point parallel adapter (It), and the -3 point One parallel adapter (one pair of corresponding terminals with a series impedance of one reflectance)
The constant resistance bridge circuit (M) connects the parallel impedance (R0
/a), and in the case of a save equalizer provided in a parallel branch with parallel impedance (R0/a), the parallel impedance (R0/a) is replaced by a three-vote series adapter (II
), in which case a 3-boat 1-column adapter (■'
) with a parallel impedance and terminated with a rectance of 7 and another first 3-board adapter between the capo (1,-1) and the output port (2,-2). Connect the first 3
from the boat adapter to the second 3-point parallel adapter (
It) or second 3. ff-to series adapter (Il)
This first 3-to-1 adapter is configured as a 3-vote series adapter (I) or a 3-vote parallel adapter (1) and is also terminated with a variable resistor (Rv). In a time-discrete variable equalizer based on the principle of the zeta equalizer with a fixed resistance bridge circuit, a three-point parallel adapter (II) or a parallel impedance (R/& ) and a multiplier (β
), and the multiplier (β) is connected in series with the multiplier (β).
A third 3-boat adapter (■ or ■) having a reflexance (8) in the series circuit to the wave-2 is configured with a knee-boo 2-port circuit that operates in the same way as these circuit parts, and in this case, this wave-2 The one-point circuit is provided with one input port and one output port, the input port and the output port are each provided with an input signal terminal and an output signal terminal, and the wave-two-point circuit has two A parallel branch and two series branches are provided, each of the two series branches having one ? −
The signal from the human input signal terminal of one boat is supplied to the output signal terminal of the other boat through a branch point and then through an adder, while the parallel branches of both wave ports are arranged in opposite directions to each other. A signal is provided from the branch point of one of the wave-port series branches to the adder of the other wave-port series branch, and in the process at least one of the series branches of both wave-ports, as well as both wave-port series branches. A time-discrete variable equalizer, characterized in that at least one of the parallel branches of the wave port is each provided with one multiplier. 4. The time-discrete variable equalizer according to claim 11ff, wherein the wave-two-point circuit is simply provided with three multipliers. 5. One multiplier is provided in both parallel branches of the Wave-2-1 point circuit and one series branch of the Wave-24-1 point circuit, and the multiplier in the series branch of the Wave-2-1 point circuit is In the direction of signal flow, the wave-2sr-) circuit is located between the parallel branches of the wave-2 point circuit before (Fig. 13, h) or in the middle (Fig.
The time-discrete variable equalizer according to claim 3 or 4, which is placed at (a, f) or after (o, g of the 13th FXJ) in the figure. 6. Pre-connect one multiplier to each side of the adder provided at the output port, and the third multiplier in the wave-two-bot circuit series branch is simply one human-powered boat. The time-discrete variable fixture according to claim 3 (FIG. 13 d, 1) connected to the terminals (&1 to bl). 7. Post-connect one multiplier to each branch of the branch point on the human power port side, output the third multiplier in the series branch of the wave-two-point circuit, and output only one multiplier of the wave-two-point circuit. Terminal (
b2 + IL2) (FIG. 13, 8.k). The time-discrete variable equalizer according to claim 3.