JPS6010447B2 - monostable multivibrator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monostable multipipelator in which a delay circuit and a flip-flop are stitched together.

Monostable multipipelators are used to generate pulses with a constant pulse width after being triggered, and various configurations are known.

FIG. 1 shows the configuration of an example of a conventional monostable multipipulator, which consists of a flip-flop consisting of NAND circuits N2 and N3, a delay circuit DL, and NAND circuits N1 and N4 on the input/output side. It outputs a pulse with a pulse width determined by the delay time of the circuit DL. NAND circuit N2 in this monostable multipipulator,
The logic of N3 is that the two inputs are each low level “L”
The output becomes a high level "H" only when the input conditions are the same, and the output becomes a low level "L" under other input conditions. If the input of the NAND circuit NI becomes a no-signal state for some reason and the "H" level continues, the NAND circuit NI
If the output of NAND circuit N3 is "L" level, the output of NAND circuit N2 is "L" level, and conversely, if the output of NAND circuit N3 is "L" level, then the output of NAND circuit N3 is "L" level. In this case, the output of the NAND circuit N2 becomes "H" level.

That is, the output of the NAND circuit N4 is in an uncertain state of either "H" level or "L" level. Such output level uncertainty is often disadvantageous for circuits driven by the output of monostable multipipulators. The present invention has been made to improve the above-mentioned drawbacks of the conventional art, and its object is to always maintain a predetermined output level even when there is no signal due to input interruption.

Examples will be described in detail below. FIG. 2 is a circuit diagram of an embodiment of the present invention, where NI to N4 are NAND circuits omitted.
1 to R4 are resistors, CI is a capacitor, and a circuit CKT in the wire constitutes an integrating circuit that integrates the output of the NAND circuit N3.

Here, a capacitor C9 having a sufficiently large capacity is used so that the output of the integrating circuit CRT remains at a constant level.

3A to 3G show an example of the waveforms of each part a to g in FIG. 2. When a signal with a period T shown in FIG. The signal inputted from the delay circuit DL to the NAND circuit N3 has a delay time of the delay circuit DL as shown in FIG. 3d.
The signal is delayed by the output signal of the NAND circuit.
Therefore, the output of the NAND circuit N2 and the output of the NAND circuit N3 each have a pulse width as shown in Fig. 3 (c). It becomes a signal.

The output of the NAND circuit N3 is integrated in the circuit CKT, and the integrated output becomes a constant level Vx as shown in FIG. 3f, even if the input signal has a constant period T. This V
The signal at level x is added to the NAND circuit N4' together with the output of NAND circuit N2, and the resistor
By setting the values of capacitor C and capacitor C, the output shown in diagram c of NAND circuit N2 is output from NAND circuit NW.
This results in an inverted version as shown in FIG. 3g. As shown in Figure 3e, the output of the NAND circuit N3 is V,,V
2, it is averaged by the circuit CKT and its output is VX: V・0? Ten reeds n-7)
Mother: Jigun...It will be represented by Q1.

When the input of the NAND circuit N3 continuously becomes a "bell", the output of the NAND circuit N3 becomes "H" or "L" as described above.
It will be one of the following levels.

At that time, Noke H'? Level is V, “L” level is V2
``Output VxH, Vx of circuit CKT in each case
L becomes ``VXH: V.; Ashitune Misaki ■ VXL=V2; Military -...{31.

Therefore, if the threshold level of NAND circuit N4 is V..., then yxL<V with VxH...
. . . The values of the resistors R1 and R2 are selected so that [4} is satisfied.

Therefore, if we consider the case where the input of the NAND circuit NI becomes "H" level continuously, the output of the NAND circuit N3 becomes "H" level.
' When the output of the NAND circuit N2 becomes the "L" level, the output of the circuit CKT becomes VxH>V, so the output of the NAND circuit N4 becomes the "L" level.

Also, when the output of NAND circuit N3 is at "L" level and the output of NAND circuit N2 is at "H" level, circuit CKT
Since the output of VxL<VTH, the output of the NAND circuit N4 becomes the "1" level. In other words, regardless of the state of the flip-flop, the output of the NAND circuit N4 becomes the "L" level. When a signal is applied to the NAND circuit NI, the output Vx of the circuit CKT is Vx<V
By setting the relationship TH, a pulse output with a pulse width determined by the delay time of the delay circuit DL can be obtained from the NAND circuit N, and the input signal of the NAND circuit N is disconnected, resulting in a continuous " When reaching the H' level, the output of the NAND circuit N3 becomes either 64H'' or 40X8', but the output of the circuit CKT correspondingly becomes Vx.
Since the relationship is H>VTH>VxL, NAND circuit N4
The output is always at "1" level.

Also, when the input signal is applied to the NAND circuit N4 at a speed higher than a predetermined period, the output Vx of the circuit CKT increases as seen from the formula tl}, and Vx'>V..., so the NAND circuit N4 The output becomes a continuous LM level.

That is, for an input signal having a speed exceeding a predetermined period, the output as a monostable multipipulator can be stopped. Such a function is useful for preventing malfunctions when applied to optical repeaters in optical communication systems, for example. The second umbrella diagram is a block diagram of an optical repeater, in which 1 is an optical fin converter, 2 is an amplifier, and 3 is a single-leg multipipe plate W or an electro-optical converter for waveform shaping.

The amplifier 2 is a wideband amplifier with AGC (automatic gain control), and since the optical signal input to the photoelectric converter 1 has a predetermined bit rate, it is amplified by the amplifier 2 and sent to the monostable multipipulator 3. In addition, the monostable multipipelator 3 has the configuration shown in FIG. 2, and converts an input optical signal with a predetermined bit rate into an electrical signal and converts the amplified signal into a pulse signal with a constant pulse width. I will do it. By driving the electro-optical converter 4 with this pulse signal, the optical signal is regenerated and relayed. Assuming that the signal applied from the amplifier 2 to the monostable multipipulator 3 in response to the input optical signal is shown in FIG.
It is a series of levels.

However, as described above, the output of the monostable multipipelator 3 is at the "L" level regardless of the state of the flip-flop, so the optical output from the electro-optical converter 4 is zero. By removing uncertainty in the output, the output optical signal can be cut off when the input optical signal is cut off.Furthermore, when the input optical signal is cut off, the gain of the amplifier 2 is increased by the AGC function, and a noise component is output. There are cases.

Since the amplifier 2 has a broadband characteristic, this noise component includes components having a speed higher than the bit rate of the input optical signal. The monostable multipipulator 3 is then triggered by this noise component. However, as mentioned above, the monostable multipipulator 3 is equipped with a circuit CKT having an integration function, so that "for an input signal having a speed higher than a predetermined bit rate," the output of the NAND circuit N4 is set to "L" level. Therefore, the pulse output for the noise component is blocked.Therefore, malfunction can be prevented.As explained above, the present invention provides the first and second NAND circuits N2. ，
In a monostable multipipulator that outputs a pulse with a pulse width determined by the delay time of the delay circuit DL using a flip-flop consisting of N3 and a delay circuit DL, a circuit CKT that integrates the output of the NAND circuit N3, and this circuit A third NAND circuit N4 is provided which adds the output of CKT and the output of the NAND circuit N2, and the circuit CKT has an output of a level lower than the threshold level of the NAND circuit N4 in the case of an input signal of a predetermined period. By configuring this, when the inputs of the NAND circuits N2 and N3 become "L" level continuously due to input signal disconnection, the state of the flip-flop becomes uncertain, but the output of the circuit CKT causes the third
Since the output of the NAND circuit N4 can always be at the "L" level, it is possible to prevent malfunction of the circuit driven by the output of the monostable multipipulator.

Furthermore, if the input signal exceeds a predetermined period due to noise components, etc., the output of the circuit CKT goes to the "H" level, so the output of the third NAND circuit N4 is forced to the "L" level. , the output of the monostable multipipulator can be stopped.

Therefore, malfunctions due to noise components can be prevented.

[Brief explanation of the drawing]

Fig. 1 shows a monostable multipipe layer of a slave, Fig. 2 shows a monostable multipipulator according to an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 shows an optical repeater. It shows a block diagram. NI~N4 is a NAND circuit, DL is a delay circuit, RI~R4
is a resistor, and CI is a capacitor. Sai 1 zu ga 2 box disaster 3 zu 4 candles

Claims (1)

[Claims] 1. In a monostable multivibrator consisting of a flip-flop consisting of first and second NAND circuits and a delay circuit that delays the input of the second NAND circuit with respect to the input of the first NAND circuit, a circuit that integrates the output of the second NAND circuit, and a third NAND circuit that adds the output of this circuit and the output of the first NAND circuit, and the output of the second NAND circuit is at "H" level. When the output voltage of the integrating circuit is set to a level higher than the threshold level of the third NAND circuit, and when the output of the second NAND circuit is at the "L" level, the output voltage of the integrating circuit is set to the level higher than the threshold level of the third NAND circuit. A monostable multivibrator, characterized in that the circuit is configured so that the threshold level is lower than the threshold level of the third NAND circuit.