JPS60103822A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain a delay circuit in which a maximum variable delay time is set optionally by providing a waveform shaping circuit having an output stage of open emitter and a comparator circuit comparing the output of waveform shaping circuit with a reference voltage in response to a desired delay time and obtaining an output pulse giving a desired delay time to the front edge or the rear edge to decrease the control voltage. CONSTITUTION:An IC1 is a comparator (or line receiver) whose output stage is open emitter and a constant current circuit CG and a capacitor C are connected to the output terminal. An IC2 is a comparator (or line receiver) with a high input impedance, an output of the comparator IC1 is connected to one input terminal E and a DC reference voltage Vref is applied to the other input terminal F. The constant current circuit CG can be a circuit comprising an operatonal amplifier IC, a transistor Q and a resistor R, the maximum variable delay time is set optionally and the delay time of the front edge and rear edge of an input pulse waveform is set independently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a delay circuit that can independently set a delay time for each leading edge or trailing edge of an input pulse waveform.

[Background of the invention]

As logic circuits become faster and more precise, timing accuracy has become an important issue. By the way, there are "variations" in the single components, wire lengths, wire capacitances, etc. used in this type of circuit, and the timing of the signal may not reach a desired value. Therefore, it is necessary to insert a delay circuit in the signal path and change the amount of delay to match the desired timing. Furthermore, since the active elements used in the circuit have different rise and fall characteristics, it is necessary to adjust the timing of the leading edge and trailing edge of the pulse waveform individually.

Fig. 1 is a block diagram of an example of a conventional delay circuit, in which resistors R*, Rn and a variable capacitance diode DVCA are connected between Banfaan jIC-1゜IC-■ which has a comparator function.
, CI consisting of Dvca? ,, insert the dipping circuit,
The delay time was controlled by changing the values of the piezoelectric pressure VB of the variable capacitance diode Dvc^ and DVCB. FIG. 2 is a time chart showing the concept of the above-mentioned delay timetable 1++I. For ease of understanding, buffer amplifier IC-1, IC
The propagation delay time inside -II is marked as 0.

Now, as shown in FIG. 2, when an input signal IN is input, an integrating circuit including variable capacitance diodes DvcAr and Dvc s is applied to the input terminals A and H of the buffer amplifier IC-It to calculate the rise υ and rise of the pulse. The bottom time increases. When this waveform is shaped by a conoparator (buffer amplifier) IC-II, an output pulse OUT delayed by Δt compared to the input waveform IN is obtained.

Such conventional circuits have the disadvantage that the delay time cannot be varied independently for the leading edge and trailing edge of the input pulse waveform. In addition, variable capacity diode DvcA+D
Since VCB is used, the control voltage range is 20 to 3
A voltage as high as 0 [V') is required.

Furthermore, the capacitance of the variable capacitance diode DVCA*Dvcn is on the order of pF to about 3oo [pF],
Resistors RA, I and B are several tens to hundreds of Ω due to the female nature of the circuit.
Therefore, the maximum variable delay amount is approximately 100 [, II
s , ] and the variable range is small, and this maximum 1j
J″A-delay amount is the variable capacitance diode DVC used
A + Dvc n and the resistance I(A, I(B) are fixed at a predetermined value determined by the values of 111■. Moreover,
Since variable capacitance diodes and comparators are used together, there is also the drawback that it is difficult to form a single-chip monolink IC due to the semiconductor IC process.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art,
The UIJ voltage can be set to a small value, the maximum variable delay time can be set arbitrarily, and the delay time of the leading and trailing edges of the human pulse waveform can be set independently.
The object of the present invention is to provide a delay circuit that can be converted into C.

[Summary of the invention]

In the 14'4 configuration of the delay circuit according to the present invention, a constant current source and a capacitor are connected so as to gradually change the waveform of either the leading edge or the trailing edge of the human-powered pulse according to a desired delay time. Comparison of a waveform shaping circuit with an open emitter output stage and its output compared with a reference voltage according to a desired delay time to obtain an output pulse with the desired delay time given to either the leading edge or the trailing edge. The input pulse is Output pulses having a desired total delay time are transmitted independently for either the edge or the trailing edge, or for each of the leading and trailing edges.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

In the figure, IC1 is a comparator (or line receiver and the same is the same) whose output stage is an open emitter, with a constant current circuit CG and a capacitor C connected to its output terminal, and IC2 is a comparator with a high input impedance. is a comparator (or line receiver), one input terminal E of which is connected to the output of the comparator ICI, and the other input terminal F connected to a DC reference voltage V r e f
is applied. In addition, the comparator ICI, J
C2 is a computer for emitter-coupled logic (ECL) circuit (e.g. A10685 manufactured by AMD, USA).
Alternatively, the circuit may be a line receiver for an ECL circuit (for example, FIDlo 0114 manufactured by Il. Hitachi, Ltd.), and basically it may be constructed of a differential amplifier followed by an open emitter output stage. Further, the constant current circuit CG may be a circuit consisting of an operational amplifier IC, an h-transistor Q, and a resistor R, as shown in FIG. , I o = (VcVEz) /R...
......It is given by (]).

Therefore, at least the output stage part of the comparator ICI (waveform shaping circuit), the differential amplifier part of the comparator IC2 (comparison circuit), the constant current source CG, and the capacitor C constitute the basic delay circuit UD. , which gives the trailing edge time of the input pulse.

Next, FIGS. 4 and 5 are explanatory diagrams of the above embodiment and other embodiments, and FIG. Figure 5 (
a) is a simplified block diagram of what gives a delay time to the same leading edge; The operation of this circuit will be explained below based on these figures. In addition, Fig. 4.

Comparator IC1 is shown in Figure 5 for ease of understanding.
, the propagation delay time inside IC2 is shown as 0.

In FIG. 4, when the human power pulse waveform IN is applied to the comparator ■C1, the output waveform on the positive output side is E
It becomes as shown in . In other words, at the rising edge of the input pulse (
(leading edge), the output stage transistor of comparator 1 is
The state becomes more conductive, and the output impedance decreases. In this case, the charging current to capacitor C is the power supply■
The output pulse is given from CC and rises rapidly. On the other hand, at the falling edge of the input pulse (trailing edge), the output stage transistor of the comparator C1 becomes increasingly non-conductive, resulting in a high output impedance. is approximately the constant current ID of the constant current source CG. Therefore, if the difference between one input voltage (reference voltage) VBf (voltage indicated by F in FIG. 4) of the comparator IC2 and the high-high level voltage VH of the other input E is ΔV, the delay time is Δt=C・ΔV/Io・・・・・・・・・・・・
...It is given by (2).

As is clear from the above description, the output waveform OUT of the comparator IC2 is delayed by the value shown in equation (2) above at the falling edge of the input pulse, as shown in FIG. 4(b).

Here, for example, the reference voltage V r e f is set as shown in Fig. 4(b).
When the output waveform OUT changes as shown by the broken line, the falling delay time of the output waveform OUT also changes as shown by the broken line. However, Fig. 4 (C) shows the situation when the constant current In is changed, and when the constant current ID is small, the fall time becomes slow as shown by the broken line, and this waveform and the other input waveform are Since these are compared by the converter IC 2, the output waveform OUT on the positive side is as shown in the figure.

In addition, the relationship with the capacitor C is that the steady flow ■ is 1 to Lo
If the range is t:n1A), then for a capacitor C of several pF, the delay circuit will be variable in the range from 11S to several ns:l, and for a capacitor C of about 1000pF', it will be a variable delay circuit of the order of μS. A variable delay circuit can be obtained.

In the above explanation, the basic circuit was explained, but in an actual circuit, in order to prevent oscillation or ringing, there are Alternatively, a resistor of several ohms to several hundred ohms may be inserted between the terminal of the capacitor C and the input terminal of the computer IC 2.

The embodiment shown in FIG. 5 is designed so that the delay time can be obtained at the leading edge, and is not the same type as the one shown in FIG. Since it is possible, its explanation will be omitted.

Furthermore, in the embodiments of FIGS. 4 and 5, even if the polarity of the input of comparator IC2 (either the positive side or the negative side) is reversed, if the polarity of its output is similarly reversed, the result will be exactly the same. As a result, the present invention also includes the above configuration.

Next, FIGS. 6 to 9 are explanatory diagrams of other embodiments of the delay circuit according to the present invention.

In the basic delay circuit described above, the delay time can be controlled only for the falling edge (ie, the trailing edge) and the rising edge (ie, the leading edge) of the input pulse. For example, as shown in FIG. 6, this basic circuit is connected between the positive output of the comparator ICI and the positive input of the comparator iC2, and between the negative output of the comparator IC2 and the negative input of the comparator IC3. Steady currents Ir, I- and capacitors C1 and C2 are provided, respectively, so that the elementary delay circuits are connected in cascade. In this case, the basic delay circuit shown in FIG. 4 is connected in cascade with the same circuit shown in FIG. 5.

As a result, as shown in the time chart of FIG. 6(b), the leading edge of the incoming signal can be independently controlled by the basic delay circuit in the subsequent stage, and the trailing edge can be controlled independently by the basic delay circuit in the previous stage. In the time chart of FIG. 6(b), the reference voltage Vr @
Although fl + V r e f2 is shown as being controlled, it is of course possible to control with constant currents Ir and I-. It is the same as above, so the explanation will be omitted, but Fig. 7,
Even with the connections shown in Figures 8 and 9, the leading edge of the 11 human-powered pulse,
The trailing edge delay time can be varied independently.

In this way, the delay time of the leading edge and trailing edge of the pulse waveform can be made independently variable, and the term that controls this variable time is the capacitance value (C), as shown in equation (2) above, There are three components: reference voltage (Vr@f) and constant current (Io), so for example, if the reference voltage V r e f is used for normal control,
The variable width of the delay time can be controlled by the constant current Ip. Therefore, a very large amount of delay can be obtained, and the delay time can be controlled with high precision where a small amount of delay is required. In addition, the voltage source for this control lightning is the normal voltage within the circuit power supply Vc c +Vag, so D/
It is very easy to match with the A converter. Furthermore, capacitor C
By increasing , it is possible to obtain a maximum variable delay time of the order of μS, and the maximum variable delay time of Equation 113 requires only a capacitance of 1, several CpF.
Comparators, constant current sources, and capacitors are all normal bipolar I
It can be manufactured using the C process and can also be made into a monolithic TC.

〔Effect of the invention〕

As described above in detail, according to the present invention, the control voltage can be reduced, the maximum variable delay time can be arbitrarily set, and the delay times of the leading edge and trailing edge of the incoming pulse waveform can be independently set. This type of variable delay circuit can be improved in performance and miniaturized.

A remarkable effect on quality stabilization can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a conventional delay circuit, FIG. 2 is a time chart thereof, FIG. 3 is a block diagram of an embodiment of a delay circuit according to the present invention, and FIG. 4 is an explanation thereof. figure,
FIG. 5 is an explanatory diagram of another embodiment, and FIGS. 6 to 9 are explanatory diagrams of each of the other embodiments. IC1, IC2, IC3..., Compan-Yu, CG...
・Constant current circuit, C...capacitor, UD...basic delay circuit. Agent Patent attorney Kosaku Fukuda (and 1 other person) Kaya 1st $29 al 71t No. 3 Mikya 4-Kut (ku (b) $4- mouth (C) Fig. 5 (ku) AI (shi) Kaya Prisoner (ku) A B (b) 7th mouth (ku) 8-B (b) Kaya 8 solid (bn Kayaq mouth (ku) 8 B (b) Continued from page 1 0 Inventor Shin Hayashi - Hitachi Electronics Engineering Co., Ltd., 30 Kusho, Nakai-machi, Ashigarakami-gun, Kanagawa Prefecture

Claims (1)

[Claims] 1. A waveform shaping circuit that has an open emitter output stage in which a constant current source and a capacitor are connected so that the waveform of either the leading edge or the trailing edge of the input pulse is gradually changed according to the desired delay time. and a comparison circuit that compares the output with a reference voltage corresponding to a desired delay time to obtain an output pulse with a desired delay time given to either the leading edge or the trailing edge. The leading edge or the trailing edge of the input pulse can be detected by a circuit with only one size or a circuit with multiple units of the same type connected in cascade, or a circuit with multiple units of different types connected in I'll A'A. A delay circuit configured to send out an output pulse giving a desired total delay time for either one or each of the leading and trailing edges independently.