JPS6010122Y2 - Switch simultaneous operation detection circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a simultaneous switch operation detection circuit.

In devices having multiple switches, it may be necessary to detect when multiple switches are operated simultaneously.

For example, in the case of simultaneous operations using this detection output, it is possible to disable all switch operations or enable only a specific switch operation.

The present invention proposes a circuit that reliably detects simultaneous operation of switches with a simple configuration.

A detailed description will be given below with reference to the drawings.

T is a switching transistor, Sl, S2 . S3 is a switch, RB is a base bias resistor, R engineering, R2, R
3 is a base bias resistor controlled in response to switches S and S3, and RE is an emitter resistor.

When switches S□ to S3 are operated individually,
The base bias of the switching transistor T is determined by the base bias resistor (resistance R1=one of R29R3) corresponding to the operated switch and the base bias resistor RB.

At this time, the switching transistor T is set to an off state, and its output (emitter) is at H level.

By the way, when a plurality of switches S1 to S3 are operated at the same time, bias resistors R1, R2, and R3 are connected in parallel, and the combined resistance value thereof is lower than that when only one resistor is used.

Therefore, the base potential of the switching transistor T decreases, and the transistor T is biased into the on state.

Therefore, its output (emitter) shifts to L level.

That is, the emitter output of the switching transistor T is the simultaneous operation detection output S of the switches.

becomes. This simultaneous operation detection output S.

By using, for example, all switch operations can be disabled when the switches are operated simultaneously.

That is, AND gate A1 corresponds to switches S, ~S3.
．． A2. Provide A3.

Simultaneous operation detection output S when any one of the switches S1 to S3 is operated.

Since is at H level, the gate signal Sc is input to the AND gates A1 to A3, resulting in an AND gate signal S corresponding to the operated switch.

The switch output is synchronized with the Switch S□～S
If two or more 3 are operated at the same time, the simultaneous operation detection output S is as described above.

Since is at L level, the gate signal S.

is not input to AND gates A1-A, and therefore no switch output is obtained.

According to the present invention described above, simultaneous switch operation detection output can be obtained with an extremely simple configuration. For example, this output can be used to disable all switch operations in a camp where simultaneous operations are performed. Useful.

[Brief explanation of drawings]

The figure is a diagram showing a simultaneous switch operation detection circuit according to the present invention. S□~S3 are switches, T is a switching transistor, RB is a bias resistor, R1-R3 are switches S□~S
Bias resistor responsive to 3.

Claims (1)

[Scope of utility model registration request] It consists of a plurality of switches, a switching transistor, and a bias resistor of the switching transistor whose resistance value is set in response to the number of operated switches, and there is a state in which two or more switches are operated and a state in which one switch is operated. A simultaneous operation detection circuit for switches configured to derive a simultaneous operation detection output from an output side of the switching transistor by controlling on/off the switching transistor in response to the operated state.