JPS5999812A - Preset device of synthesizer receiver - Google Patents
Preset device of synthesizer receiverInfo
- Publication number
- JPS5999812A JPS5999812A JP20851082A JP20851082A JPS5999812A JP S5999812 A JPS5999812 A JP S5999812A JP 20851082 A JP20851082 A JP 20851082A JP 20851082 A JP20851082 A JP 20851082A JP S5999812 A JPS5999812 A JP S5999812A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- preset
- frequency
- receiver
- battery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
- H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
- H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
- H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、受(8機の受信周波数をメモリ機能を有す
るマイコンの制御によって選択することができるシンセ
サイザー受信機にか〜わり、特に、そのプリセット装置
に関″f−るものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a synthesizer receiver in which eight reception frequencies can be selected by control of a microcomputer having a memory function, and in particular, This relates to a preset device.
受信機の選局回路に水晶発振器を基準信号とするP L
L (Phase −Locks+d Loop )
回路を使用しこのPLL回路から出力される周波数
を局部発振周波数とすると共に、この周波数に対応する
制御電圧で各種同調回路を制御するシンセサイザー受信
機は、PLL回路がデジタル信号で制御できるため、受
信チャンネルの選択及びプリセット等がボタンスイッチ
で簡単に行うことができ、きわめて操作性が優れたもの
になる。P L that uses a crystal oscillator as a reference signal in the receiver's tuning circuit
L (Phase-Locks+d Loop)
Synthesizer receivers use a circuit to set the frequency output from this PLL circuit as a local oscillation frequency and control various tuning circuits with control voltages corresponding to this frequency.Since the PLL circuit can be controlled by digital signals, the reception Channel selection, presetting, etc. can be easily performed using button switches, making it extremely easy to operate.
第1図はかNるシンセサイザー受信機の概要な示すブロ
ック図で、1は受信周波数を選択するフロントエンド、
2は中間周波増幅部、3は復調部。Figure 1 is a schematic block diagram of a synthesizer receiver, in which 1 is a front end that selects the receiving frequency;
2 is an intermediate frequency amplification section, and 3 is a demodulation section.
4は低周波増幅部を示す。なお、5は例えばAM放送波
を受信する別のフロントエンドの一部を示す。4 indicates a low frequency amplification section. Note that 5 indicates a part of another front end that receives, for example, AM broadcast waves.
6は周波数シンセサイザーを構成するPLL回路で、よ
く知られているように基準信号源、比較回路、プログラ
マブルデバイダ等から構成され、前記フロントエンド1
の周波数変換器1aに注入される局部発振器1b、及び
高周波増幅器1Cの同調周波声9等を制御計(るものr
J+る。Reference numeral 6 denotes a PLL circuit constituting a frequency synthesizer, which is composed of a reference signal source, a comparison circuit, a programmable divider, etc. as is well known, and is connected to the front end 1.
The local oscillator 1b injected into the frequency converter 1a and the tuning frequency voice 9 of the high frequency amplifier 1C are controlled by a control meter.
J+ru.
? f1マイ−1ン等゛τ・構成さt1前1iシP L
L回路6を制御ft1l−i’る制御回路な示1−5
この制御回路T1τは、その人力ポー1川−4’:FM
/’AMの選択スイッチ−お スキャー、/ニーソゲ周
波数な−lツブ、又はダ「′/ンさせるス・fツ寸、受
信−fN′ンーイルなメモリにセットさせるセラトス1
′ツ千、受信チャンネノ10周波数を書キ込み、ヌは読
ろ出−(−プリセットスイッチ等が設けてk)るキー下
・−ド8が接続さtlていZ)。? f1 my-1 etc.゛τ・configuration t1 before 1i P L
The control circuit that controls the L circuit 6 is shown in Fig. 1-5.
This control circuit T1τ is the human-powered port 1-4':FM
/'AM selection switch - Scan, /Nice frequency -L knob, or D'/'S selection switch, Receive - fN' set in memory.
10, write the reception channel number 10 frequency, and read it out (the preset switch etc. is provided).
又、mIj向1回路Tにはプリセットさハた′フ′−タ
ン記憶1−るプリセラ1メモリ10が併設さハ、7−ン
) −t、 :7ド1が選択している周波数の表示器9
<、駆動4−75ことができるものである。In addition, the mIj direction 1 circuit T is provided with a preset memory 10 that stores preset functions. Vessel 9
<, it is possible to drive 4-75.
したがつ”(、キーボード8の各種操作スイ二′チを操
作=Vることによって、ワンタラ手で所望のグヤンネ/
シを選択する・二とができる。、なお、オートチューニ
ングを行うために復調部3のピーク出力な0777回路
11を介して入力し、その点で受信状態に−fると共に
その時の制御信号をプリセットメモリ10忙A↓き込む
ことがで以上説明したよりな構成からなるシン十ザイザ
・受信機は、プリセットボタンに、1、ってブリ村ツ1
メ王す10内のデータをmlみ出し、自1−y罠受信状
態にすることができるが、この時、メリセツト7メモリ
101・て書冬込まれているデー、夕は受信機の電源が
オフとたつ−〔も消政し、ムいよ5に・ニ゛/り丁)ご
・′ス戒池ECバックアップさオビ℃いる。By operating the various operation switches 2' on the keyboard 8, you can manually select the desired number/
Able to select 1 and 2. In addition, in order to perform auto-tuning, the peak output of the demodulator 3 is inputted through the 0777 circuit 11, and at that point, the reception state is changed to -f, and the control signal at that time is written into the preset memory 10. The synthesizer/receiver with the more detailed configuration described above has a preset button with 1 and 1.
It is possible to extract the data in the memory 10 from the memory 10 and put it in the trap receiving state, but at this time, the data written in the memory 101 of the memory 7 and the receiver's power is turned off in the evening. When it's off, I'm backing up Kaiike EC.
しかし4、がら、工場等にふ9ける製造段階でけ0iJ
d[〕ハック;γツヅ電池Fは通常装備さiていないの
で、プリセットボタンでIAちに所望イる周波数の受信
状態に−(ることがで西ず、受ft’1機の各部の調整
は、通常のダイアル付受信機しCみらオlるよ5に、受
イ4周波数を表示器gをみながら測定器のチェック周波
数圧8′わ一!木、バラクタVCに供給される制御電圧
を調整し2て受信機の同調回路、1フツキング、セバン
ーション等を調整していた。However, at the manufacturing stage in factories etc.
d[]Hack: Since the gamma battery F is not normally equipped, you can use the preset button to immediately set the IA to the reception state of the desired frequency. is a normal receiver with a dial, and while looking at the display g, check the frequency pressure of the measuring device. I adjusted the voltage, the tuning circuit of the receiver, the footing, the severance, etc.
しかし、なから、このような調整作業は各受信バンド毎
に反復して行わtするので、その都度受信周波数を測定
器のチェック周波数に合わせるのけ向側であり、その調
整作業時間も長くなるという欠点があった。However, since such adjustment work is repeatedly performed for each receiving band, each time the receiving frequency must be adjusted to the check frequency of the measuring instrument, and the time required for the adjustment process is also long. There was a drawback.
、′、の発明は、か〜るシ/セザイザー受信機の特質を
利用し、て、その製造段階で行う調整作業及びメインテ
ナス時に行う調整作業がプリセットボタン圧よって簡単
に行わすするよ5にするものである。The invention of ,', takes advantage of the characteristics of the C/Size receiver, and makes it possible to easily perform the adjustment work at the manufacturing stage and the adjustment work at the time of maintenance by pressing a preset button.5. It is something.
この発明は、」二重の目的を達成するためにPLL回路
の制御回路に、ブリセラ1メモリをザボートとしている
バラフン−ツブ電池の有無を検出1′る4’(判定回路
を設け、この判定回路がバックアップ電池でブリセット
メ士りがザボー)・さtlてぃないと1M断(−2だ時
は、前dCプリセントメモリにに、らかしめ書き込ま1
1″Cいるチェック用の周波数がプリセット・ボタンに
よって読み出さハるように構成し、シンセーリ′イザー
受信機の調整作業が容易になるようにすると共に、バッ
クアンプ電池の消費を検知1−ることができるようにし
たものである。In order to achieve the dual purpose, the present invention provides a control circuit for a PLL circuit with a determination circuit (1') for detecting the presence or absence of a battery that uses the Bricella 1 memory as a base. If the backup battery is not used to reset the battery, the 1M disconnection (-2) will be written to the previous dC precent memory.
The configuration is such that the 1"C check frequency is read out using a preset button, making it easier to adjust the synthesizer receiver and also detecting the consumption of the backup amplifier battery. It has been made possible.
第2図はこの発明の一実施例を示−(シンセ→Jイザー
受信機の概要を示fノロツク図−(゛、第1図と同一機
能プロツクは同一の記号で示1.てあ、る。FIG. 2 shows an embodiment of the present invention (synthesizer → J-Izer receiver). The same functions as those in FIG. 1 are indicated by the same symbols. .
この発[、(IJのシンセザイザー受伯機では前記した
ズリセラlメモリIOICMASK ROM 等で構
成されている読み出し専用の固定メモリ20が併設さt
l、・4ツクγツブ笥、池Eのイj無の検出を行5判定
回路21が設けである。From this point on, (IJ's synthesizer machine is equipped with a read-only fixed memory 20 consisting of the above-mentioned serial memory IOIC MASK ROM, etc.).
A row 5 determination circuit 21 is provided to detect the presence or absence of the I, .
前記判定回路21はバンクアップ電池Eの電圧を検出−
(−るか、又は物理的に2・チック/ツブ電池Eの1無
を検出し、プリセットメモリ10がバンクアップ電池E
によってバンクアップされていないと判断さtiだ時は
、前記制御回路7しτイJ号が供給さす(ろ。The determination circuit 21 detects the voltage of the bank-up battery E.
(- or physically detects the presence of 2 ticks/tube batteries E, and the preset memory 10 stores the bank-up battery E.
When it is determined that the bank is not banked up by ti, the control circuit 7 supplies τiJ.
Tると、第3図のフ[j−千A′−1に示1ようにギー
ボー1−’ 8のプリセットボタンが押圧された時、固
定メモリ20に記憶さtlているデータが読み出される
ように制御さ11.このデータに対応イ゛るチェック周
波数で受<g状態にブムる1っ又、ブリセツtヘメモリ
10がバックアップ電池Eによってバックアップさハて
いる時は、そのプリセットメモリ1゜に記憶さnている
受14周波数のデータが読み出さtする。When the preset button 1-'8 is pressed as shown in FIG. 3, the data stored in the fixed memory 20 is read out. 11. When the memory 10 is backed up by the backup battery E, if the memory 10 is backed up by the backup battery E, the receiver stored in the preset memory 10 is Data of 14 frequencies is read out.
前記固定メモリ20jC記憶さねているデータは受信機
の調整に必要なチェック周波数に対応するもので、例え
ば6つの受信バンドを有する場合のチェック周波数の一
例を第1表に示¥。The data stored in the fixed memory 20jC corresponds to the check frequencies necessary for adjusting the receiver. For example, Table 1 shows an example of the check frequencies when there are six reception bands.
第 1 表
以」二説明したように、この元明のシンセサイザー受信
機は、バックアップ電池Eが付加されている時は通常の
シンセサイザー受信機六同様に動作し、キーボードのプ
リセットボタン(スイッチ)を抑圧(−だ時は、丁でに
プリセットメモリに記憶されている受信チャンネルのデ
ータが読み出されて、その受信チャンネルで受信状態に
なるが、・くツクアップ電池Eが無い時は、^IJ述し
たようにブリセラlボタンな押圧すると、前記第1表の
チェック周波数(このチェック周波数は通常放送電、波
がない周波数が選げハているンで受信状態になる。As explained in Table 1 onwards, this Genmei synthesizer receiver operates like a normal synthesizer receiver when the backup battery E is attached, suppressing the preset button (switch) on the keyboard. (When it is -, the data of the reception channel stored in the preset memory is read out, and the reception state is set on that reception channel. However, when there is no backup battery E, as mentioned above, When you press the Brisera l button, the check frequency shown in Table 1 above (this check frequency is a normal broadcast signal, and a frequency with no waves is selected) will enter the receiving state.
したがって、工場の製造段階でバックアップ電池Eが装
備さtlていない時、第1表の(−ニック周波数がj(
1次出力されろ測定製置を備えていtlば、この発明の
装置を備えている受信機は極めて簡単にドラッギング、
四偶等の調整が可能である。Therefore, when the backup battery E is not installed at the factory manufacturing stage, the (-nick frequency in Table 1 is j(
If equipped with a primary output measurement device, a receiver equipped with the device of the present invention can be dragged very easily.
Adjustments such as 4-even are possible.
なお、製造段階以外でも、例えば補修を行ったあとの再
謂整時にはバックアップ電池Eを除去するとヂエツク周
波数で受信状態になるので、再調整がやり易いという利
点があり、逆にバックアップ電池のチェックにも利用゛
することができる。In addition, even outside the manufacturing stage, for example, when re-adjusting after repairs, removing the backup battery E will return to the receiving state at the check frequency, which has the advantage of making readjustment easier. can also be used.
前記固定メ七り20は従来のプリセットメモリ(RAM
)の一部をMASKfることによって構成し、てもよく
、判定回路21も同−IC回路内に一体化して形成して
もよい。The fixed memory 20 is a conventional preset memory (RAM).
) may be constructed by performing MASKf, and the determination circuit 21 may also be formed integrally within the same IC circuit.
上述したように、この発明のシンセサイザー受信機はブ
リヒントメモリの一部、又はプリセットメモリと独立に
、チェック周波数が出力されるデわめて容易に行わtす
るという効果を奏すると共に、補修時の再調整も簡単に
なるという利点がある。As described above, the synthesizer receiver of the present invention has the effect that the check frequency can be outputted as a part of the preset memory or independently of the preset memory, and the check frequency can be outputted very easily. This has the advantage that readjustment becomes easy.
【図面の簡単な説明】
第1図はシンセサイザー受信機の概要を示すブロック図
、第2図はこの発明のシンセサイザー受信機のブロック
図、第3図は制御回路のフローチャートを示−1゜
図中、1はフロントエンド、6はPLL回路、1は制御
回路、8はキーボード、1oはブリセラトメ千り、20
は固定メモリ、21は判定回路を示1゜[Brief Description of the Drawings] Fig. 1 is a block diagram showing an overview of a synthesizer receiver, Fig. 2 is a block diagram of a synthesizer receiver of the present invention, and Fig. 3 is a flowchart of a control circuit. , 1 is the front end, 6 is the PLL circuit, 1 is the control circuit, 8 is the keyboard, 1o is Briceratome Senri, 20
21 indicates a fixed memory, and 1° indicates a judgment circuit.
Claims (1)
おいて、プリセットメモリに接続さ4ているバックアッ
プ電池の有無を検出する判定回路を設け、該判定回路が
電池によるバンクアンプがなされていないと判断した時
は、プリセットメモリに記憶されているチェック用の周
波数がプリセットボタンの操作で読み出されるように制
御されることを特徴とするシンセサイザー受信機のプリ
セット装置。A synthesizer receiver having a preset memory function is provided with a determination circuit that detects the presence or absence of a backup battery connected to the preset memory, and when the determination circuit determines that bank amplification by batteries is not performed, the preset memory is 1. A preset device for a synthesizer receiver, characterized in that a check frequency stored in the receiver is controlled to be read out by operating a preset button.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20851082A JPS5999812A (en) | 1982-11-30 | 1982-11-30 | Preset device of synthesizer receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20851082A JPS5999812A (en) | 1982-11-30 | 1982-11-30 | Preset device of synthesizer receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5999812A true JPS5999812A (en) | 1984-06-08 |
JPH0436484B2 JPH0436484B2 (en) | 1992-06-16 |
Family
ID=16557352
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20851082A Granted JPS5999812A (en) | 1982-11-30 | 1982-11-30 | Preset device of synthesizer receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5999812A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6218189A (en) * | 1985-07-16 | 1987-01-27 | Pioneer Electronic Corp | Terminal equipment in catv |
JPS62219812A (en) * | 1986-03-20 | 1987-09-28 | Matsushita Electric Ind Co Ltd | Satellite broadcast reception equipment |
EP0514265A2 (en) * | 1991-05-13 | 1992-11-19 | Sony Corporation | Device for displaying remaining electric energy of battery |
-
1982
- 1982-11-30 JP JP20851082A patent/JPS5999812A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6218189A (en) * | 1985-07-16 | 1987-01-27 | Pioneer Electronic Corp | Terminal equipment in catv |
JPH0771280B2 (en) * | 1985-07-16 | 1995-07-31 | パイオニア株式会社 | Terminal device in CATV |
JPS62219812A (en) * | 1986-03-20 | 1987-09-28 | Matsushita Electric Ind Co Ltd | Satellite broadcast reception equipment |
EP0514265A2 (en) * | 1991-05-13 | 1992-11-19 | Sony Corporation | Device for displaying remaining electric energy of battery |
Also Published As
Publication number | Publication date |
---|---|
JPH0436484B2 (en) | 1992-06-16 |
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