JPS5999582U - blanking circuit - Google Patents
blanking circuitInfo
- Publication number
- JPS5999582U JPS5999582U JP19450382U JP19450382U JPS5999582U JP S5999582 U JPS5999582 U JP S5999582U JP 19450382 U JP19450382 U JP 19450382U JP 19450382 U JP19450382 U JP 19450382U JP S5999582 U JPS5999582 U JP S5999582U
- Authority
- JP
- Japan
- Prior art keywords
- blanking
- circuit
- pulse
- horizontal deflection
- blanking circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のブランキング回路を示すブロックダイヤ
グラム、第2図は水平偏向回路の動作を説明する動作波
形図、第3図は第1図のブランキングパルスの発生過程
を示す動作波形、第4図はこの考案の一実施例によるブ
ランキング回路を示すブロックダイヤグラム、第5図は
第4図のブランキングパルスの発生過程を示す動作波形
図である。
図中、10は8字補正用コンデンサ、11はフライバッ
クトランス、18はブランキング幅制御回路、19はブ
ランキングパルス発生回路である。
なお、−中、同一符号は同一または相当部分を示す。
第2図Fig. 1 is a block diagram showing a conventional blanking circuit, Fig. 2 is an operating waveform diagram explaining the operation of the horizontal deflection circuit, Fig. 3 is an operating waveform diagram showing the blanking pulse generation process in Fig. FIG. 4 is a block diagram showing a blanking circuit according to an embodiment of the invention, and FIG. 5 is an operation waveform diagram showing the process of generating the blanking pulse in FIG. 4. In the figure, 10 is a figure-8 correction capacitor, 11 is a flyback transformer, 18 is a blanking width control circuit, and 19 is a blanking pulse generation circuit. Note that the same reference numerals in - indicate the same or equivalent parts. Figure 2
Claims (1)
クパルスを用いて行なうブランキング回路において、上
記フライバックパルスと上記水平偏向回路に設けられた
8字補正用コンデンサの両端電圧を合成すると共にこの
合成電圧を所定のレベルでスライス出力するブランキン
グ幅制御回路、およびこのスライス出力されたパルス幅
に応じてブランキングパルスを生成するブランキングパ
ルス発生回路を備えたことを特徴とするブランキング回
路。In a blanking circuit that performs blanking using the flyback pulse of the horizontal deflection circuit, the flyback pulse is combined with the voltage across the figure-8 correction capacitor provided in the horizontal deflection circuit, and this A blanking circuit comprising: a blanking width control circuit that slices and outputs a composite voltage at a predetermined level; and a blanking pulse generation circuit that generates a blanking pulse according to the sliced pulse width.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19450382U JPS5999582U (en) | 1982-12-22 | 1982-12-22 | blanking circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19450382U JPS5999582U (en) | 1982-12-22 | 1982-12-22 | blanking circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5999582U true JPS5999582U (en) | 1984-07-05 |
Family
ID=30418045
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19450382U Pending JPS5999582U (en) | 1982-12-22 | 1982-12-22 | blanking circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5999582U (en) |
-
1982
- 1982-12-22 JP JP19450382U patent/JPS5999582U/en active Pending
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