JPS59982B2 - charge transfer fixed memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer memory, and particularly to a fixed memory that has not been realized in the past.

A charge transfer device (CTD) injects minority carrier charges into a depletion layer formed near the semiconductor surface and controls the corresponding depth of the depletion layer by controlling the potential of an adjacent electrode. The basic idea is to transfer the injected charge. Since the depletion layer formed under the electrode is filled with minority carriers within a few milliseconds, it is essential to refresh the memory within this time in order to preserve the memory contents.

Therefore, a shift register type operation is performed, and new charges are injected again according to the value of "1" or "0" indicated by the output signal.As described above, the operating principle is short. Due to the volatility of the time constant, the use was mainly limited to dynamic shift registers, and fixed memory did not exist.This invention allows fixed memory, which could not be realized with conventional CTD, to be realized using conventional CTD manufacturing technology. The purpose is to realize this using

That is, the present invention provides a charge transfer array having a structure that gives unidirectionality to the flow of charges, and a structure that determines the region in which a depletion layer is formed in a multivalued manner for each bit according to information to be stored in a fixed manner. Furthermore, the fixed memory is provided with an injector for injecting charge into the channels of the charge transfer array.

゛゛An example of means for fixedly determining multiple values is when applied to a charge-coupled device (CCD), a fixed memory can be configured by changing the capacity of a potential well with a constant depth, for example by changing the area of a transfer electrode. can. The injector has a structure in which a conductive region opposite to that of the substrate is provided on the inner surface of a semiconductor substrate of one conductivity type, and a channel is formed along this region. The operating principle of this invention is to use a memory array in which the region forming the depletion layer is fixedly changed for each bit based on the information to be stored in a fixed manner. The amount of charge transferred to the next stage is controlled based on information to be stored in a fixed manner by selectively supplying a drive signal to the accessed electrodes, and the charge obtained as output. The purpose is to determine the contents of fixed memory according to the amount.

In order to achieve this operation, a first clock drive circuit (
TransferOdeclOckdriver) and a second clock drive circuit (AddressOdeclOckdriver) that selectively provides control signals only to the addressed electrodes.
eclOckdriver) is required.

Hereinafter, the principle of operation will be explained in detail regarding the embodiments using the drawings.

FIG. 1 shows the applied voltage V of CIl) with two different threshold values 6, 8.

The relationship between the surface potential Zs and the surface potential Zs is shown. 6 is, for example, the normal 100
The state of a cell having an oxide film layer of 0λ is shown, and 8 shows the state of a cell having an oxide film layer of 3000λ, for example.

That is, the surface potentials of 6 and 8 with respect to the applied voltage V1 are:
L2 and Ll are L4 for V2, and L5 and L4 are for L3 and 3, respectively. It is assumed that the relationship between the surface potentials of L1 to L5 is Li<Li+1 (where i=] to 4).

Practical applied voltage range, e.g. 1V3-Vll≦2
0V, 1, V2, V3 showing the relationship as shown in Figure 1.
It is generally possible to select 6 and 8 in Figure 1
There are many methods to achieve this state, such as ion implantation, polysilicon embedding, and double structure, in addition to using the difference in the thickness of the oxide film layer, but these are not the main purpose of the present invention, so we will not discuss them in detail. Omitted. FIG. 2 shows a configuration applied to a CCD, in which a transfer electrode 13 is provided on a semiconductor substrate 11 of one conductivity type with an insulating film 12 interposed therebetween, and the electrode 13 has a step that becomes lower in the charge transfer direction. That is, the thickness of the insulating film 12 is changed to form a step. FIG. 2 schematically shows the depth of the depletion layer when =1, -V2 is applied, in correspondence with the surface potential level of FIG. 1. FIG. 3 shows the basic principle of performing unidirectional charge transfer by utilizing the levels of these four depletion layers.

#1 to electrode 13. = V1 is applied, and V is applied to the #2 electrode.
When a potential of =V2 is applied, a step of depletion layer is formed from #1 to #2, and the charges existing in this region are accumulated sequentially from level L4. FIG. 4A shows the basic structure for storing fixed information of the present invention, which is fixedly stored by changing the area of the transfer electrode 13.
This is a specific example in which the length in the charge transfer direction is constant and the width in the vertical direction is varied.

As shown in FIG. B, a large number of transfer electrodes 13, for example 3
The insulating film 12 is placed on each electrode 13 #1, #2, #3 of the bit.
Since the transfer electrode 13 has a step in the thickness, all of the
They have 82 threshold values in the same way, and only #2 has a charge storage area that is halved. In other words, the fixed memory content is such that electrodes #1 and #3 correspond to information 1F'' and #2 corresponds to information ``0''. Such an electrode structure is shown in Figure 4A as shown in electrode #2. thicker in the recess, e.g. 10000
Various means are available, such as using an oxide film of λ, or making the electrodes partially smaller. Since this is also not the main purpose of the present invention, detailed explanation will be omitted. Although the three electrodes in FIG. 4A are shown as one body, they are separated from each other as shown in the cross-sectional view in FIG. 4B. FIG. 4B shows VOl=VO2=VO3 as the potential of electrode #i (hereinafter referred to as VGi).
This shows the depth of the depletion layer 14 when =V1.

C in the figure shows a case where VOl=V2, VO2=VO3=V1, and a deep depletion layer is generated under electrode #1.

Now, in the depletion layer formed under electrode #1, as shown in Figure E, the maximum charge stored in the depletion layer formed under electrode #2 when VOl = VG3 = 1, VG2 = V2. In order to accumulate twice the amount of
It is determined based on the characteristics of the figure. Therefore, C
In the depletion layer 14 under the electrode #1, there exists a charge equal to 1/2 of the total capacitance supplied from an injector provided on the inner surface of the semiconductor substrate 11 with a region of a conductivity type opposite to that of the substrate. This timing will be the start of the explanation. At the next timing, if 'VGl=02=2, VG3=V1, D
As shown in the figure, the charges are evenly distributed under the two electrodes #1 and #2, and the surface potential is stabilized in an equilibrium state.

#2 has a smaller area, so when compared to C, the surface potential of D will naturally be higher than when half of the total charge is stored under the electrode of #1. At the next timing, 01=03=1,V
When 02=V2, all charges are collected under the #2 electrode 13 as shown in FIG. 4E due to the stepped structure of the depletion layer 14 shown in FIG. 3, which exhibits unidirectional charge transfer. .

In this state, charges fill the depletion layer 14 formed here,
In addition, the starting charge amount must be set to an amount that does not overflow to both sides beyond the level L1 existing at the boundary between #1 and #2. This amount initially becomes the limit that determines the maximum value that can be accumulated under the #1 electrode in Figure C. At the next timing, when VGl=Vl and VO2=03=V2, charges are dispersed and stored as in the same figure D.

At the next timing, by setting VGl=VO2=1,03=V2, all the charges that were present under the #2 electrode at E are transferred and stored under the #3 electrode.

In this way, even an array with an electrode structure as shown in FIG. 4A can function as a normal CCD shift register by using Vl and V2 as VGi. In FIG. 4, a case is shown in which "1" and "0" are consecutive, but when "o" and "0" are consecutive, F and G in the figure change. Figure 5 shows an example in which "1", "O", and "0゛" are fixedly stored and the electrode structure is configured as shown in Figure 5A. F
．． (5G6 only, detailed explanation will be omitted. Figures 6 and 7)
The figure is a charge movement diagram for explaining the basic operation for reading fixed memory contents using a memory array having the above-described electrode rotation structure. The horizontal axis indicates the electrode number, and the vertical axis indicates the position on the array where the charge exists at the timing indicated. In both FIGS. 6 and 7, charges are transferred as shown in FIGS. 4 and 5.

Timings 1, 2... refer to C and E in Figures 4 and 5.
, G, it means a point in time when a charge exists only under one electrode 13. FIG. 6 shows that when the word accessed to read the fixed memory is i (hereinafter referred to as W=i), the fixed memory content is "O'", so the output stage is reached after n timings. A case is shown in which the charge injected under the first electrode 13 at timing 1 is transferred and outputted under the n-th electrode 13. Figure 7 shows W=
In the case of i, since its fixed memory content is "1",
At this point, the charge transfer is interrupted, and the injected charge does not appear at the output stage after n timings.

Charge transfer control based on the fixed memory contents is shown in FIG. 1 for the third voltage. It is an object of the present invention to perform reading using =3. This control will be explained in detail below using the drawings.

FIGS. 8, 9, and 10 are explanatory diagrams of transfer modes using the same arrays as in FIGS. 4 and 5.

However, after B in FIGS. 4 and 5, the difference in the storage charge capacity of the depletion layer 14 under each electrode 13 cannot be intuitively understood, so FIGS. 8, 9, and 10 For convenience, the length in the channel direction (charge transfer direction) is assumed to be 1/2 for the 1/2 capacity type (corresponding to the information "O").Therefore, the accumulated charge amount is as shown in the drawing. It can be expressed in direct proportion to the area.In the transfer mode, the continuous string of information can be expressed in 4 ways: "1゛→"1゛441赫→460赫, ≦≦o赫→6 cage Ri and 660 赫→"0'" There is.

In all this, correct transfer must be guaranteed. FIG. 8 shows the case where all electrodes #1, #2, and #3 are "1", that is, "11 → "1", and FIG. 9 shows #1 and #3.
3 is "1" and #2 is "0'", that is, "1" → ≦40
Akira and 440r≦1＼In Figure 9, #1 is 6≦pi and #2 and #3
indicates "0"', that is, "O" → "0".

The transfer operation is the same as in FIGS. 4 and 5, and the relationship between drawing numbers and timing is the same, so a detailed explanation of the operation will be omitted. As above, o-1.

=2 using an array that can perform normal charge transfer.

Reading as a fixed memory using three voltages will be described next. From FIG. 11 onwards, the case where W=i (the first electrode is accessed) is shown, and FIG. 11 shows the case where the fixed memory content is "1".

Up to Figure 10, it is known that the amount of charge normally transferred in the transfer mode is the same regardless of the contents of the fixed memory, so the previous bit can be treated as "1". From Figure 11 onwards, this content is treated as "1" unless otherwise specified. Until the charge is transferred under the electrode #(1-1), the first and second voltages V as described up to FIG.
1 and V3, the explanation will be omitted.

FIG. 11A is a diagram showing electrodes #(1-1), #i, #(1+1) and their fixed memory information, and FIG. 11B is a diagram showing #(
1-1) shows a state in which charges are transferred and stored under the electrode. At the next timing, the electrode of the accessed word, ie, the #i electrode.

Let i be i=3. At this time, the charge is #i as shown in C of the same figure.
flows under the electrode. However, level L4 is # (1-1)
and #i, so a portion also exists under the #(1-1) electrode. At the next timing, the potential of the #(1-1) electrode returns to V(.(1-1)-1), and as shown in FIG.

At the next timing, #(1+1) and VG(1+1)=V
2, and an empty depletion layer is prepared which transfers and accepts the charge stored in #i as shown in FIG.

However, since the area of #i is wide, the surface potential under #i is (
゜Because it is “1”) it does not exceed level L3. Therefore, as shown in Figure E, there is no movement of charge from directly under the #i electrode to the depletion layer directly under the #(1+1) electrode. V at the #(1+2) electrode at the next timing.

(1+2)=V2VC, and then V at the next timing.
(1+])=Return to V1. These two states are F and G in FIG. As a result, charge transfer is possible only after W = i, and the charge that has been injected and transferred to the #i electrode remains directly under the #i electrode. ing. This corresponds to the state of t≧i in FIG. 7, and no charge appears at #n, which is the output stage, at t=n.
Therefore, when the charge here is checked at t=n, and if it does not exist, it is found that the contents of the fixed memory of W-1 were "1".

The dotted line below the #(1+1) electrode in Figure 11 is
This is a case where the fixed memory content of the #(1+1) electrode is "0", but from the above explanation, if W = i and the fixed memory content there is "1", the fixed memory content of #(1+]) Since this is known to be unrelated, I have inserted a dotted line instead of a separate diagram.

From FIG. 12 onwards, the fixed memory content of W=i is "O".

Since the region where the depletion layer of #i is formed is small, the surface potential that changes due to the transferred and inflowing charges is higher than that of "1", exceeding the surface potential directly under the electrode of #(1+1) flows into the stage. This is the principle of reading out that the fixed memory content of the #i electrode is "0''".From this, it is obvious that the amount of charge that can be stored directly under the electrodes #(1+1) and #(1+2) and the amount of charge transferred There is an important relationship between the charge amount and the amount of charge.Therefore, in FIG. 12, the case where the #(1+1) electrode has "1" as fixed information is illustrated. Figure A shows electrodes #(1-1), #i, #(1+1).
) and its fixed information, and B-E in the same figure shows B- in FIG.
This corresponds to the timing of E. In E of the same figure, the charge is #i
and #(1+1), and the portion exceeding level L3 of #(1+1) flows into #(1+2) at the next timing. Therefore, the fixed information #(1+2) becomes a problem.

Fig. 13 shows the case where #(1+2) is "0", and Fig. 14 shows the case where #(1+2) is "1"", and the 3 after #i
The bit portion is shown in the figure. FIG. 13E shows the same timing as FIG. 12E.

At this next timing, VO (1+2) at #(1+2)
-V2, and as shown in F in the same figure, level L3 in E in the same figure.
All charges exceeding #(1+2) are stored under #(1+2).
In this case, the amount of charge stored directly under #i and #(1+1
) and the amount of charge stored under #(1+2) are equal. At the next timing, use #(1+]). (1+])
Returning to -V1, the charge there is transferred to below #(1+2) and stored as shown in G in the figure. At subsequent timings, the charges stored under this #(1+2) electrode are transferred and reach under the #n electrode at t=n. This is the operation shown in Figure 6, and if a charge exists at t-n under the #n electrode, it can be determined that the content of the fixed memory read out at W=i was "0"". .14th
In the figure, since the #(1+2) electrode is "1", the amount of charge stored directly under the #(1+2) electrode in the figure F is the 13th electrode.
Although it is the same as the figure, the surface potential is lower.

However, the amount of charge stored here at the next timing is
This is the same as in FIG. 13, and subsequent operations will be the same as in FIG. FIG. 15 differs from FIG. 12 in that #(1+1) is "0".

This is why the surface potential directly under the #1 and #(1+1) electrodes shown in FIG. 15E is higher than that in FIG. 12. However, the amount of charge present here is the same. According to the same principle as described above, two combinations exist depending on the fixed information content of the #(1+2) electrode. The case of "0" is shown in FIG. 16, and the case of "1" is shown in FIG. 17, limited to the 3 bits after the #i electrode.
+2) Since the amount of charge that can be stored in the electrode is small, the surface potential based on the stored charge in Figure E slightly exceeds level L3.

Therefore, when VG(1+1) rises toward V1 at the next timing, the level L in the area of #(1+1) electrode
A part of the material exceeding 3 also flows into the #i electrode,
In FIG. 16G, the ratio of the amount of charge stored in the #(1+2) and #i electrodes is 5:7 (41.7%:58.
3%). In FIG. 17, the ratio is 1:1 based on the same principle as in FIG. 14. As has been made clear from the above explanation, when reading, the W− of the accessed word is
Only the bit specified by 1.

i-V3, otherwise normal transfer control is performed between the voltages V1 and V2, and by checking the presence or absence of charge at t=n, the fixed information accessed for reading is
It can be determined whether it is "0" or "pi". As explained above, according to the present invention, fixed memory, which could not be achieved with conventional CTD, can be realized, which will lead to the development of a new field of CTD and the development of a new field of CTD, which was previously impossible to realize due to the high cost and economical reasons of fixed memory. A terminal device, for example, an input device equipped with a kanji pattern generator, can be put into practical use.

In the above embodiment, an example in which the present invention is applied to a CCD has been described, but it goes without saying that the present invention can also be applied to a CTD, for example, a BBD.

[Brief explanation of the drawing]

Fig. 1 is a characteristic curve diagram showing the depletion layer level with respect to the transfer electrode voltage when the thickness of the insulating film is changed to explain an embodiment of the memory of the present invention, and Fig. 2 is a characteristic curve diagram showing the depletion layer level with respect to the transfer electrode voltage when the thickness of the insulating film is changed. A schematic diagram, FIG. 3 is a staircase distribution diagram of a potential well for transferring charge in one direction according to the characteristics shown in FIG. 1, and FIGS. Figure 6 and Figure 7 are Figure 4 A and Figure 5 A.
Basic operation explanatory diagram for reading fixed memory of
10 to 10 are diagrams for explaining the charge transfer operation in FIGS. 4 and 5, and FIGS. 11 to 17 are diagrams for explaining the readout operation in FIGS. 4 and 5. Referring to the figure 11... One conductivity type semiconductor substrate, 12...
- Insulating film, 13... Transfer electrode, 14... Depletion layer.

Claims (1)

[Claims] 1 Transfer electrodes having a structure that gives unidirectionality to the flow of charge are arranged, and each piece of information to be fixedly stored is associated with each of the transfer electrodes on a one-to-one basis, and the areas of the transfer electrodes are arranged in a one-to-one manner. In the charge transfer array, the charge transfer array differs according to the content of fixed information, the charge transfer array includes means for injecting a certain amount of charge from one end of the channel of the charge transfer array, and a first channel for transferring the charge injected by the means. and means for sequentially applying a second voltage to the transfer electrodes; and means for applying a third voltage higher than the first and second voltages for transfer only to the transfer electrodes corresponding to the fixed information to be read. , means for detecting whether or not the injected charge has been transferred at the other end of the channel of the charge transfer array.