JPS599758A - Microprogram control data processing device - Google Patents

Abstract

PURPOSE:To reduce the number of times of read-out of a useless micro-instruction even if a control storage is one module, by providing a means for designating address from which a micro-instruction is read out at the time of branch of a condition. CONSTITUTION:When executing a condition branch instruction, if values of a branch condition signal (a) and a branch forecasting signal (b) are same, forecasting is considered to be right, by which the same signal is selected by a selector 3 and 4, and a read-out micro-instruction becomes a micro-instruction to be executed in the next time. If the values of the branch condition signal (a) and the branch forecasting signal (b) are different from each other, the forecasting is considered to be wrong, and a correct address is inputted to a micro-instruction address register 7, but it is discriminated that the micro-instruction read out of a control storing circuit 1 is not the micro-instruction to be executed in the next time. In this way, the condition branch instruction can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a microprogram control device in data processing equipment. In particular, it relates to speeding up branch control methods.

[Description of prior art]

Conventionally, in this type of data processing device, when determining the address of the microinstruction to be read next, the control memory was accessed after waiting for the branch condition to be determined. It may not be possible to read the data.

This is because the control memory read time occupies a large proportion of the clock time, and the next microinstruction address must be determined early within the clock time, making it time consuming to determine branch conditions in data processing devices. This is because the determination of the microinstruction address becomes slow.

Conventionally, in such cases, one of the branch conditions is fixedly selected and read without waiting for the decision of the branch condition, and the determined branch condition matches the read microinstruction. If a match does not match, execution of the read microinstruction is inhibited, and the microinstruction is read at an address based on the established branch condition.

For example, in a two-way conditional branch where the condition is met or not, the microinstruction is always read at the address on the side where the condition is met, and if the condition is not met, the microinstruction is read out at the address on the side where the condition is not met at the next clock. This is a method of reading instructions. In this method, when the condition is not satisfied, the microinstruction on the side where the condition is true is read out, so this microinstruction is read out unnecessarily, and no microinstruction is executed within this clock time, resulting in the performance of the data processing device. There are bases where there is a decline.

Another conventional method is to configure the control memory with a plurality of modules, and to assign addresses so that the branch destination address in a conditional branch is always in a different module. This is because when making a conditional branch, multiple branch destinations are in different modules, so all of these microinstructions are read out from the control memory at the same time, and one of them is selected with the established branch condition and placed in the microinstruction register. .

This method has the disadvantage that it is necessary to always prepare as many modules in the control memory as the number of conditional branch destinations, and that the address allocation of underground microinstructions is also restricted.

[Detailed description of the invention]

The present invention improves this point by providing means for specifying which address microinstruction is to be read at the time of conditional branching, thereby eliminating unnecessary reading of microinstructions even if the control memory is in one module. The object of the present invention is to provide a device that can safely perform high-speed data processing by reducing the number of times the data is processed. [Summary of the Invention] The present invention provides a control storage circuit that stores a plurality of microinstructions, a microinstruction register that holds the microinstructions read out from the control storage circuit, and a control device for determining a branch condition in a conditional branch microinstruction. means for specifying which one of the branch destination addresses is to be selected as the read address of the control storage circuit without waiting for the branch destination; If the selected f address matches the branch condition, the read microinstruction is executed, and if it does not match, it is held in the microinstruction address register. A microinstruction is read from the control storage circuit at an address.

[Explanation based on examples]

An embodiment of the Ann invention will be described based on the drawings.

The figure is a block diagram of main parts of an embodiment of the present invention. The contents of a control storage circuit 1 that stores a plurality of microinstructions are led to a microinstruction register 2, and the outputs of the address section of and are led to selectors 3 and 4.

Further, the output of the selector 4 is guided to the control storage circuit 1 and the plus-1 adder 5. The output of this plus-one adder 5 is led to an increment register 6, and this output is led to the selectors 3 and 4. The output of selector 3 is very large,
□, and output this output to the selector 4. lead to.

Further, the output of the microinstruction section of the my-redirect-instruction register 2 is led to the decoder 8, and the output is led to the reset terminal and set terminal of the branch prediction flip-flop 9, respectively. Further, 10 is an arithmetic circuit, the output of which is led to one input terminal of the exclusive OR circuit 11, and the output of the branch prediction flip-flop 9 is led to the other input terminal. The output of this exclusive OR circuit 11 is led to the cent terminal of an execution inhibiting flip-flop 12. 1, the output of the arithmetic circuit 10 is guided to the control of selector 3, and
The above flip-flop (9, 12) (7
) lead output.

With such a circuit configuration, the microinstruction to be executed is read from the control storage circuit l from the address specified via the output line 20 of the selector 4 and stored in the microinstruction register 2.
is stored in Output line 20 of selector 4 is positive 1
It is also connected to an adder 5, where 1 is added to the address and stored in the increment register 6.

The output line 21 of the address part signal of the microinstruction stored in the microinstruction register 2 and the output 2-in 22 of the increment register 6 are selected by the selector 3, and the qualifier a is used in the microinstruction address register 7. The output line 21 of the address crystal signal of the microinstruction stored in the microinstruction register 2, the output line 22 of the increment register 6, and the output line 23 of the microinstruction address register 7 are selected by the selector 4 and output on the output line 20. becomes. For selection by the selector 4, a branch prediction signal and an execution inhibition signal C are used.

A part of the microinstructions stored in the microinstruction register 2 is decoded by the decoder 8.

When the decoder 8 decodes the microcode that sets the branch prediction flip-flop 9 to 1, the output line 2
4 becomes 1, and 1 is set in the branch prediction flip-flop 9. For other microcodes, the output line 24 of the decoder 8 is 0. When the decoder 8 decodes the microcode that resets the branch prediction flip-flop 9 to 0, the output line 25 of the decoder 8 becomes 1 and the branch prediction flip-flop 9 is set to 0. For other microcodes, the output line 25 of the decoder 8 is 0.

In other words, when creating a microprogram, which microinstruction is executed before the conditional branch instruction is executed, which has a higher probability of the condition being met or not as a result of the conditional branch, or which one do you want to speed up? etc., the branch prediction flip-flop 9 is set to 1t.
Or set it to 0.

Further, the branch condition signal a generated and selected by the arithmetic circuit 10 is subjected to an exclusive OR in the branch prediction signal 11 which is the output of the branch prediction flip-flop 9. Here, as a branch condition, for example, the arithmetic circuit I
There are register values, operation result values, carries, overflows, etc. in O, and one of these is selected depending on which condition the conditional branch microinstruction takes and becomes the branch condition signal a.

If the values of this branch condition signal a and the branch prediction signal 1 are different, the execution inhibition set signal d becomes 1, and the execution inhibition flip-flop 12 is set to 1. The execution inhibition flip-flop 12 is set only when a conditional branch microinstruction is being executed and the execution inhibition set signal d is 1, and is reset at the next clock. The execution inhibiting signal C, which is the output signal of the execution inhibiting flip-flop 12, is used as a selection signal for the selector 4, and at the same time inhibits the execution of microinstructions stored in the microinstruction register 2, although not shown in the figure. It is also used for

When the execution inhibition signal C is 1, the increment register 6,
The microinstruction address register 7 and branch prediction flip-flop 9 are not updated.

Now, to explain the operation when executing a conditional branch instruction, when the branch condition is satisfied, the branch condition signal a becomes 1, and the address part signal of the microinstruction output line 21 becomes the address of the next microinstruction to be executed.

When the branch condition is not satisfied, the branch condition signal a 73f O
The output line 22 of the increment register 6, which holds the value obtained by adding 1 to the address of the microinstruction currently being executed, becomes the address of the microinstruction to be executed next.

Since this branch condition signal a passes through many stages of gates, selectors, etc., it is slow to be finalized and cannot be used as a selection signal for the selector 4 that selects the address of the control storage circuit 1;
It is used to select the output 2-in 21 of the address part signal of the microinstruction when the branch condition is met, and to select the output line 22 of the increment register 6 when the branch condition is not met.

Further, when the execution inhibit signal C is 0, the selector 4 selects the output line 21 of the address part signal of the microinstruction when the branch prediction signal S is 1, and when the branch prediction signal S is 0, the output line 21 of the address part signal of the microinstruction is selected. Select line 22. When the execution inhibit signal C is 1, the output line 23 of the microinstruction address register 7 is always output regardless of the value of the branch prediction signal S.
Select.

That is, when a conditional branch instruction is executed, if the values of branch condition signal a and branch prediction signal S are the same, the prediction is correct, and selectors 3 and 4 select the same signal, and the read micro The instruction becomes the next microinstruction to be executed. At this time, the execution inhibiting flip-flop 12 is set.

If the values of the branch condition signal a and the branch prediction signal S are different, the prediction is incorrect, and the correct address is entered in the microinstruction address register 7, but the microinstruction read from the control storage circuit 1 is not executed next. It's not a microinstruction that should be done. At this time, the execution inhibiting flip-flop 12 is set to inhibit execution of the next microinstruction, and at the same time, the next microinstruction to be executed is read at the address stored in the microinstruction address register 7. .

In the above embodiment, the case of conditional branching in two directions has been described, but by increasing the number of branch prediction flip-flops, prediction in conditional branching in more directions can be performed.

[Detailed description of the invention]

As explained above, according to the present invention, there is provided means for predicting and specifying which branch direction microinstructions are to be read from the control storage circuit prior to execution of a conditional branch instruction. Therefore, since the control storage circuit is a single module, it is possible to reduce the number of times that a monolithic microinstruction is read out, and to speed up the execution of a conditional branch instruction.

[Brief explanation of drawings]

The figure is a block diagram of main parts of an embodiment of the present invention. ■... Control storage circuit, 2... Micro instruction register, 3.4... Selector, 5... Plus 1 adder, 6
- Increment register, 7... Micro instruction address register, 8... Decoder, 9... Branch prediction flip-flop, 10... Arithmetic circuit, 11...
Exclusive OR circuit, 12...execution inhibit flip-flop.

Claims (1)

[Claims] (1) A control memory circuit that stores a plurality of microinstructions, and a microinstruction register that holds the contents of the microinstructions read from the control storage circuit, and the contents of the address field of the microinstruction register are In a microprogram control data processing device controlled to specify an address in the control storage circuit of a microinstruction to be executed, a circuit for predicting whether or not a condition is met by a microinstruction prior to a conditional branch microinstruction; an arithmetic circuit that outputs whether a branch condition is met or not; and an arithmetic circuit that outputs the branch address in the microinstruction register and an address incremented by 1 to the address in the control storage circuit from which the microinstruction currently being executed is read. When the selected and stored microinstruction address register matches the output of the prediction circuit and the arithmetic circuit, the branch address of the microinstruction register or the address incremented by 1 is used as the next microinstruction to be executed. A microprogram characterized by comprising means for setting the contents of the microinstruction address register as a read address, and setting the contents of the microinstruction address register as the address of the next microinstruction to be executed when the outputs of the prediction circuit and the arithmetic circuit do not match. Control data processing device.