JPS5997256A - Connecting system of line connecting device - Google Patents

Abstract

PURPOSE:To reduce the number of cables between a communication controller and a line connecting device by assigning the same control timing to a line scanning section while shifting the phase by one. CONSTITUTION:An address forming circuit ADG10 of a line scanning section CS1 forms an address by the leading of a control clock C1 and transmits it to an address bus control circuit ADBC of a line scanning common section CSC. Similarly, a scanning section CS2 forms an address from a clock C2 and transmits the address. The line connecting device 1 sets the address transmitted through an address bus to an address buffer register LADR17 by the trailing of the control clock C1. The line connected by the address set to an LADR17 is scanned to set the data from the line to an input data buffer register LIDR18.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a communication control device that connects a plurality of line connection devices, and in particular to a connection method for line connection devices that reduces the number of cables between the devices. (b) Prior art and problems in general K The 3H2r feed control device seven-way connection device is housed in separate housings to facilitate system purchase changes, as shown in Section 1. The two are connected via cables, but the cable used inside the case and the cable between devices are connected via cables. ．． Since the 1st category is different, it is normal to provide a terminal board for cable conversion on the housing.On the other hand, the number of lines that a communication control device can control depends on the time it takes for the line scanning unit to scan one line and the number of lines to be controlled. Determined by communication speed. This is because all lines must be scanned within one bit data time. Therefore, in order to increase the number of lines to be controlled, assuming that the time to scan one line is constant, it is essential to increase the number of line scanning units in the communication control device.

At this time, in the conventional connection method, the line scanning section and the line connecting device P1. As shown in FIG. 2, if the lines are connected on a one-to-one basis, the number of cables from the communication control device to the line connection device increases. However, as the number of cables increases, the number of cables increases, and the casing also has to be made larger.

(c) Purpose of the Invention It is an object of the present invention to solve the above points 18i2 and to reduce the number of cables between the communication control device and the line connection device.

2) Disadvantages of the Invention 1/7- In order to achieve the above object, the present invention has a connection with a communication line (=
7. In a communication control device that performs data: 1B+ transmission, in its own communication control device corresponding to the above-mentioned line connection device, If a plurality of line scanning sections are created and configured to perform different operations at the same timing, one line scanning section can be created between the above number of line scanning sections and the first V line connection device. The present invention is characterized in that the interface line H is also configured to be divided and shared.

(E)≧゛, Bright Embodiment FIG. 3 is a block diagram of one embodiment of the present invention, and FIG. 4 is a time chart of this embodiment. In Figure 3, 1 is the communication control unit (CCU), 2 is the line running common section (C8C),
3 to 6 are line scanning units 1 to 4 (C81 to 4), 7 is a timing generation circuit (TMG), 8 is an address bus fit control circuit (ADBC), and 9 is an output data bus control circuit (O
DBC), 101-Yo address creation circuit (A, DC),
11 is the output data holding register (IDR), 12 is the output data holding register (ODR), 13 to 16 ('':J
', rotational attachment J1. : Devices 1 to 4 (LUTs 1 to 4
), 17 is an address buffer register (LADR), 1
8 is an input data buffer register (LIDR), t 9
is the human data path obtained lm11 circuit (I D l')C-
), 20 is an output data buffer register (LODR).

The present invention will be explained with reference to FIGS. 3 and 4.

Timing generation circuit (TM) of line running common section (CSC)
The control timings (TC1-4) and control clocks (C1-4) created in step G) are sent to each line scanning section (C8-4). Note that the control clocks (C1-4) are also sent to each line connection device (LUTt-4).

In C8I, the section 1 timing TCI is the address sending timing, TC2 is the data input timing, TC3 is the data modification timing, and TC4 is the data sending timing. In C82, TC2 is address sending timing, TC
3 is the data input timing, TCA is the data modification timing, and TCl is the data sending timing. Similarly C
83 is TC3 as address sending timing, C84 is TC
The control timing is shifted by one phase and assigned, such as 4 as the address sending timing.

In the C8I, an address is created in the seat address creation circuit (ADG) at the rising edge of the braking clock CI and sent to the address bus control circuit (ADBC) of the line scanning co-tracing section (CSC). Similarly, in C82, C8
3T and C34T create addresses in ADG and send them to ADBC, respectively.

In ADBC, the address from C8I is set at control timing TCI, the address from C82 is set at TC2, and the address from C82 is set at control timing TCI.
When it is TC3, the address from C83 is sent, and when it is TC4, the address from C84 is sent to I and UT through the address bus (ADH), respectively.

At LUTI, the address transferred through dADB is set in the address buffer register (LADR) at the falling edge of the control clock C1. Next, the connected line is scanned according to the address set in LADR, and the address transferred from the line is At the rising edge of the control clock C2, the data is set in the input data buffer register (LIDR) and transferred to the input data bus control m11 circuit (IDBC).Similarly, in LUT2, the LAD
Set the R head address to Sera 1-Lf, set the data from the line to LIDR with C3, set it to LADR with C3 in LUT3, set it to LI-DR with C4, and set LUT4 with L at C4.
Set to ADR, set to LIDR with CI.

The human data bus control circuit (IDBC) of LUT1 transfers data to the address bus (IDBC) at the rising edge of the control clock C2.
IDB) to C8, and the data transmission is stopped at the rising edge of the control clock C3. Similarly LLIT2
IDBC is sent by C3, stopped by C4, LUT
3 sends at C4, stops at C1, sends at 01 at LUT4,
Stop at C2.

In C8I, data transferred through the entire IDB is taken in at control timing TC2, set in the input data holding register (IDR) at the rising edge of control clock C3, and data comparison/modification etc. is performed at control timing TC3. and send the data to the line ft1ll ff
41 At the rising edge of clock C4, the output data holding register (
ODR). The data sent to ODR is sent to the output data bus control circuit (C8C) of the line scanning common section (C8C).
ODBC).

Similarly, in the C82, the input data is ID by the control clock C4.
R to sec, output data is C1 to ODR), C8
3, input data is set to IDR at C1, output data is set to ODR at C2, and in C84, manual data is set to IDR at C2, and output data is set to ODR at C3.0 In 0DBC, at control timing TC4, C81 Yo)
When TCl, the output data from C82, when Te3, the output data from C83, and when Ta2, the output data from C84 are sent to the LUT through the output data bus (ODB). .

In LUT1, the output data transferred through ODB is set to the output data bannofer register (LODR) at the fall of the control clock C4. Similarly, LUT2 is controlled by the control clock C1, LUT3 is controlled by C2, and LUT3 is controlled by the control clock C1.
The UT4 sets the output data to the LODR in response to the C3.

As described above, by assigning the same control timing to each C8 with a one-phase shift, one set of interface buses (address bus, input data bus, and output data bus) can be used for up to four Can be used with C8.

In Figure 4, cable length 30m1 cable delay 200m
The time is calculated as na, which is 0. Effects of the Invention As described above, according to the present invention, since a set of interface lines can be shared by a plurality of C8s, the CCU and LU
The number of cables between Ts is reduced, and the CCU housing can be made smaller.

In addition, since C8s can be easily expanded, even if the CCU has sufficient processing capacity, even in systems where the number of connections is limited due to the C8's scanning capacity, it is possible to connect lines up to the limit of processing capacity. It becomes like this.

[Brief explanation of the drawing]

11th! @l is a diagram showing a general mode when a communication control device and a line connection device are connected, and FIG. 2 is a diagram showing a conventional method when multiple line connection devices are connected to a communication control device. , FIG. 3 is a block diagram of an embodiment according to the present invention, and FIG. 4 is a diagram showing a time chart of the embodiment. In FIG. 3, 1 is a communication control device, 2 is a line scanning common section, 3 to 6 are line scanning sections, and 13 to 16 are line connection devices 2.
It's good.

Claims (2)

[Claims] (1) In a communication control device that performs data communication by beaming a plurality of line connection devices connected to a communication line in close proximity, line scanning is performed in which particles are created in the communication control device corresponding to the line connection devices mentioned above. By configuring the units to perform different operations at the same timing H, 1', a set of interfaces can be created between the plurality of line scans v, 11 and the line connection device at the end. A connection method for a line connection device characterized in that the line is configured to perform time-division sharing control. (2) 1 [
ω The current set meal time is determined by the timing of executing the address sending operation, the timing of executing the data reading operation, the timing of executing the data modification operation, and the timing of executing the data sending operation, and the line scanning unit and an address line created between the circuit connection device,
Claim (1) wherein one set of interface lines consisting of an output data line and an input data line is configured to be shared by up to four sets of line scanning units and line connecting devices.
Connection method of line connection device described in section.