JPS5994298A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a memory device having a high working speed by adding a circuit to a power supply circuit to feed a large current in case the voltage level is low on a bit line. CONSTITUTION:A memory transistor TRQ1 is turned off when signals Y and X' are changed to a high level with a signal X changed to a low level respectively. Then the voltage of a bit line 1 begins to rise up. In accordance with the increment of voltage of the line 1, the voltage rises up at a node N2. Then a TRQ3 is turned on to reduce the voltage level at a node N3, and therefore a TRQ5 is turned off. The charging current to the line 1 is reduced, and the voltage of the line 1 approximates to a fixed level. At the same time, the voltage of the N1 rises up more and is set at a fixed level. When the level of the voltage at the N1 exceeds the reference voltage Vref, a sense circuit detects that 0 is stored in the TRQ1'.

Description

[Detailed description of the invention] Pillow Arashi! The present invention relates to semiconductor memory devices such as ROM (Read Only Memory).

PRIOR ART An example of a conventional ROM is shown in FIG. 1. Ql and Ql are NMO8I-transistors as memory transistors,
Output signals X, The output signal Y of the decoder is applied. Q3. Q4
and Q5 are transistors that constitute a circuit to keep the voltage of bit line 1 stable, and are depletion type NMO transistors.
8) Short-circuit the drain of transistor Q4 (the type is indicated only for depletion type, and not for enhancement type) to the high voltage power supply Vcc, and short the gate and source of transistor Q4 to NMO8.
) drain of transistor Q3 and NMO5) transistor Q
The transistor Q2 is connected to the gate of the transistor q3 and the source of the transistor Q5.
The drain of is connected. The source of transistor q3 is grounded, and the drain of transistor Q5 is connected to power supply Vcc through a power supply circuit including transistors Q6 and Q7.
It is connected to the. In the power supply circuit, the gate and drain of NMO3) transistor q7 are connected to power supply Vcc, and the source of transistor Q7 is connected to depletion type NMOS transistor Q7.
The drain of the MOS transistor Q6 is connected, and the gate and source of the transistor Q6 are short-circuited and connected to the drain of the transistor Q5. The sense circuit is connected to the connection point (node) Nl between transistors Q5 and 96.
It is connected to the. Cs is the stray capacitance of the bit line.

In this memory circuit, the memory transistor Q1 turns on (conducts) when the decoder output signal X becomes high level, that is, 1 is stored, and the transistor Q1 marked with an If transistor Q1 is selected, it remains off (non-conducting), that is, 0 is stored, and transistor Q6 . A current is supplied from the power supply circuit of Q7 to charge the stray capacitance Cs, and if the potential of the node N1 is selected to be lower than the reference voltage of the sense circuit, the potential of the node N1 becomes higher than the reference voltage. O is detected.

However, the drain current ID and drain voltage VD of the depletion type NMO8) transistor Q6 are
-VD characteristics, as shown in Figure 2, ID tends to saturate as VD increases. There is a problem in that it takes a relatively long time to select the memory transistor that is currently in use and to raise the voltage level of node N1 to the level detected by the sense circuit, thereby reducing the operating speed of the memory device.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and provide a memory device that can supply power to a bit line at a high speed and therefore operate at a high speed.

composition Examples will be described in detail below.

FIG. 3 shows an embodiment, in which a circuit consisting of an NMO transistor Q8 is added in parallel to a series circuit of transistors Q6 and 97 as a power supply circuit to the conventional memory device of FIG.

That is, the drain and gate of transistor Q8 are connected to power supply Vcc, and the source is connected to node N1, and the other configurations are exactly the same as in FIG. 1. Here, the ratio W7. of the channel width W to the channel length of the transistor Q8. is designed to be smaller than that of transistor Q7. Now, the decoder outputs the output signal Y
When and X are at high level and X is at low level, memory transistor Q1 is selected and Ql is unselected. At this time, the transistors Ql and Q2 are turned on, and current flows from the power supply Vcc through the circuit of the transistors q7 and Q6, the circuit of the transistor q8, and the transistor Q5. However, since the maximum current value flowing through memory transistor Q1 is limited (for example, 100 to 150 μA), the voltage level of bit line 1 is stabilized at a constant voltage as shown in the period 0 to t1 in FIG. Further, the voltage at the node N1 is also a constant voltage, which is a voltage that is lower than Vcc by the threshold voltage VTR of the transistor Q7 and the drain-source voltage VDS of the transistor Q6. The voltage at this node N1 is lower than the reference voltage Vref, so the sense circuit detects 1.

Next, if the signals Y and X change to a high level and X changes to a low level, the memory transistor Q1 turns off, and since ql remains off, the voltage on the bit line 1 begins to rise. When the voltage at node N2 increases as the voltage at bit line 1 increases, transistor Q3
begins to turn on, the voltage at node N3 begins to drop, and transistor Q5 begins to turn off. Therefore, as shown in the period [1 to [3] in Fig. 4, the charging current to the bit line 1 decreases and the voltage of the bit line 1 approaches a constant value, and the voltage of the node N1 increases further. It will eventually reach a constant value. When the voltage level of node N1 exceeds reference voltage Vref, the sense circuit detects that 0 has been stored in memory transistor Ql. Power supply current is supplied to the bit line in parallel through the circuit of transistors Q7 and Q6 and the circuit of transistor Q8.
There is no large difference in the VDS of Q8, and in this switching of memory transistor selection, the power supply current supplied to the bit line is small, so more current flows through the transistor Q7, which has a large buttock.

However, in the event that the bit line voltage has fallen to ground level, rapid supply current is provided through transistor Q8, as will be discussed in detail in the next embodiment.

FIG. 5 shows a second embodiment, which differs from the embodiment of FIG. 3 in the arrangement of memory transistors. This embodiment has memory transistors Qll and QII, and a bit line 11 selected by a transistor Q2 whose gate signal is a decoder output signal Y, and a memory transistor Q
12 and Q12, and is selected by a transistor Q2 whose gate signal is the decoder output signal Y.
The memory transistor Qll of the bit line 11 and the memory transistor Q12 of the bit line 12 are selected by the same decoder output signal X, and the memory transistor Qll of the bit line 11 and the memory transistor Q12 of the bit line 12 are the same. It is connected to be selected by the decoder output signal X. Here, it is assumed that d is stored in the memory transistor Q12 and 1 is stored in the other memory transistors.

Now, the decoder output signals X and Y are selected at high level,
Assume that and Y are at low level and unselected.

At this time, transistors Q2, Qll, and Q12 are turned on and the other transistors are turned off, so that the bit line 11 is supplied with power and becomes a low level as shown in the periods O to Q in FIG. 6, and as described above. When the voltage level of node N1 becomes lower than the reference voltage, the sense circuit detects that 1 is stored in memory transistor Qll. Further, the bit line 12 is not supplied with power and is at ground level.

Next, it is assumed that the decoder output signal changes to select X and Y and non-select X and Y. Bit line 1 selected at this time
2 was at ground level, the level of node N1 temporarily decreased (Fig. 6 (period 4 to [5)), but since both memory transistors Q12 and Q12 were off, the supplied power supply current begins to charge the stray capacitance C5, and the levels of the bit line 12 and node N1 begin to rise.Here, the ID-VD characteristic of the depletion type NMOS transistor Q6 changes as the VD increases, as shown in FIG. [) tended to be saturated, whereas NMO
5) As shown in Figure 7, the -VD characteristics of transistor Q8 are such that I
D increases rapidly. Therefore, when the level of the no-lock 1 drops during the period from t4 to [5 in Fig. 6], as is clear from comparing Fig. 2 and Fig. 7, a large power supply current is supplied mainly through the transistor q8. , the bit line 12 and the level of the node \ will rise rapidly.

Thereafter, as the bit line 12 is charged and the voltage level of the node N1 increases in the order of ■1→■→as shown in FIG. 6, the drain-source voltage VD of the transistor Q8 increases.
S is (Vcc −Vl)−+ (Vcc −■2)−(
Vcc -V3), and as shown in FIG. 7, the current flowing through the transistor Q8 also decreases from IDI→ID2→O. In addition, as described above, when the transistor Q5 is turned off, the current in the transistor Q6 also stops flowing, and both the bit line 12 and the node N1 become stable at their respective constant levels (see FIG. 6 [6 and later)]. Node N
When the level of 1 exceeds the reference voltage Vref during the stabilization stage, the sense circuit detects a high level and detects that 0 is stored in the memory transistor Q12.

In the above embodiment, a circuit such as NMO5) transistor Q8 is added in parallel to the power supply circuit, so when the level of node N1 is higher than Vcc - VTH (v'm is the threshold voltage of transistor Q8), transistor Q8
No current flows through the node N1, and the level of the node N1 becomes Vcc −V.
If it is lower than TR but still relatively high, more current will flow through transistor Q7 which has a larger value of 4 than transistor Q8, and if the level of node N1 decreases, a large current will flow through transistor Q8 and the node The operation is such as to quickly raise the level of N1 and the bit line.

In yet another embodiment, a depletion type NMO8) transistor can be similarly connected and used in place of the NMO5I transistor Q8 as a transistor in this additional circuit of the power supply circuit.

In that case, the threshold voltage of this additional circuit no longer exists, and even when the voltage level at node N1 is high, current flows through that depletion type transistor in parallel with transistor Q7, and when the level at node N1 drops, the above As in the embodiment, a large current is supplied from the depletion type transistor.

Effects As described above, the present invention adds a circuit that can supply a large current when the voltage level of the bit line is low to the power supply circuit of the semiconductor memory device. Since the rising speed from the level becomes faster, and therefore the process from selecting the memory transistor to detection by the sense circuit can be carried out in a short time, it is possible to realize a memory device with high operating speed.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional memory device, and Figure 2 is a depletion type transistor q in the power supply circuit in the same circuit.
FIG. 3 is a circuit diagram showing an embodiment of the present invention. FIG. 4 is a diagram showing the voltage levels of the node N1 and the bit line in FIG. 3. FIG. FIG. 6 is a diagram showing the voltage levels of the node N1 and the bit line in FIG. 5, and FIG. 7 is a diagram showing the voltage levels of the node N1 and the bit line in FIG. 5. - It is a diagram showing the operating characteristics of transistor q8. Star, Q6. Q7...Transistor forming the power supply circuit, Q8...Transistor of a circuit added to the power supply circuit, 1, 11.12...Bit line. Patent applicant Ricoh Co., Ltd.

Claims (1)

[Claims] (1) In a semiconductor memory device that supplies power to the bit line of a selected memory transistor to detect the storage state of the memory transistor, the power supply circuit operates to supply a large current when the voltage level of the bit line is low. A semiconductor memory circuit characterized by adding a circuit that can be supplied.