JPS5993150U - リ−ドフレ−ム保護シ−ト - Google Patents

リ−ドフレ−ム保護シ−ト

Info

Publication number
JPS5993150U
JPS5993150U JP1982189525U JP18952582U JPS5993150U JP S5993150 U JPS5993150 U JP S5993150U JP 1982189525 U JP1982189525 U JP 1982189525U JP 18952582 U JP18952582 U JP 18952582U JP S5993150 U JPS5993150 U JP S5993150U
Authority
JP
Japan
Prior art keywords
lead frame
protection sheet
frame protection
sheet
length direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982189525U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0132365Y2 (enrdf_load_stackoverflow
Inventor
俊雄 井上
Original Assignee
新潟化工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新潟化工株式会社 filed Critical 新潟化工株式会社
Priority to JP1982189525U priority Critical patent/JPS5993150U/ja
Publication of JPS5993150U publication Critical patent/JPS5993150U/ja
Application granted granted Critical
Publication of JPH0132365Y2 publication Critical patent/JPH0132365Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
JP1982189525U 1982-12-15 1982-12-15 リ−ドフレ−ム保護シ−ト Granted JPS5993150U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982189525U JPS5993150U (ja) 1982-12-15 1982-12-15 リ−ドフレ−ム保護シ−ト

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982189525U JPS5993150U (ja) 1982-12-15 1982-12-15 リ−ドフレ−ム保護シ−ト

Publications (2)

Publication Number Publication Date
JPS5993150U true JPS5993150U (ja) 1984-06-25
JPH0132365Y2 JPH0132365Y2 (enrdf_load_stackoverflow) 1989-10-03

Family

ID=30408596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982189525U Granted JPS5993150U (ja) 1982-12-15 1982-12-15 リ−ドフレ−ム保護シ−ト

Country Status (1)

Country Link
JP (1) JPS5993150U (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57158220U (enrdf_load_stackoverflow) * 1981-03-31 1982-10-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57158220U (enrdf_load_stackoverflow) * 1981-03-31 1982-10-05

Also Published As

Publication number Publication date
JPH0132365Y2 (enrdf_load_stackoverflow) 1989-10-03

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