JPS5992730A - Charge control circuit - Google Patents
Charge control circuitInfo
- Publication number
- JPS5992730A JPS5992730A JP20115082A JP20115082A JPS5992730A JP S5992730 A JPS5992730 A JP S5992730A JP 20115082 A JP20115082 A JP 20115082A JP 20115082 A JP20115082 A JP 20115082A JP S5992730 A JPS5992730 A JP S5992730A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- timer
- output
- charging
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は充電制御回Ml−係り、特にシエバー等の蓄
電池の光磁検知手段として蓄電池の充電電圧を比較検出
する回路とタイマー回路とを併用することにより、蓄電
池の光磁時間を最適の長さに設定することが出来ると共
(二線回路に表革用ランプを柩付けること(二より任意
の時間長だけフラッシング等の溌報装装置を取付けるこ
とが出来る廉?ニした充電制御回路に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a charging control circuit Ml-, and in particular uses a circuit for comparing and detecting the charging voltage of a storage battery and a timer circuit as a magneto-optical detection means for a storage battery such as a Siever. By this, it is possible to set the opto-magnetic time of the storage battery to the optimal length (by attaching a leather lamp to the two-wire circuit (secondly, it is possible to set the optical magnetic time of the storage battery to the optimum length), and to use a flashing or other reporting device for an arbitrary length of time. Concerning an inexpensive charging control circuit that can be installed.
第1図は従来例に係る充電制御回路を示すものでこの回
路の構成は次の砿にlっている。FIG. 1 shows a conventional charging control circuit, and the configuration of this circuit is shown in the following diagram.
すなわち第1図(二おいて″電池5の答藏が苓である場
合を考えてみると、電源ONと同時にタイマー7はリセ
ットされ、トランジスタ6はOFFとなる一方、交流入
力端より入力された交流嘔力は半導体整流素子lによシ
平滑され、発振器(インバータ)2に加えられる。発振
器2の出力はトランス3を介して出力され半導体整流素
子4によ多直流(二変換され電池5(二充′屯が行われ
る。一方タイマー7は一定時間経過するとタイムアツプ
出力を出す。このことによシトランジスタロは導通し発
振回路2をOFF’とする。このこと(こよりトランス
3からの出力は0となり、蓄′電池5への充電を中止す
る。この充電器の充電時間はタイマー7の設定時間によ
シ調整されている。In other words, in Figure 1 (see Figure 2), if we consider the case where the battery 5 is connected, the timer 7 is reset as soon as the power is turned on, and the transistor 6 is turned off, while the AC input from the AC input terminal is reset. The AC power is smoothed by a semiconductor rectifying element 1 and applied to an oscillator (inverter) 2.The output of the oscillator 2 is outputted via a transformer 3, and is converted into a DC current by a semiconductor rectifying element 4 and converted into a battery 5 ( A second charge is performed.Meanwhile, the timer 7 outputs a time-up output after a certain period of time has elapsed.This makes the transistor conductive and turns the oscillation circuit 2 OFF'.Thus, the output from the transformer 3 0, and charging of the storage battery 5 is stopped.The charging time of this charger is adjusted by the set time of the timer 7.
上l己の様な光重方式にあっては蓄゛市池の充一時間は
一伽的(−決定されてしまう。従がって、充電中に停電
等充電が一時中断した様な場合、タイマー7は再び最初
から動作を始めることになシ過充電となる。あるいは長
時間タイマーが動1作することになるので省エネルギー
という点からも間j坦があった。In a light-duty system like the one above, the charging time of the storage pond is determined by the time it takes. Therefore, if there is a temporary interruption in charging due to a power outage while charging, etc. , the timer 7 would have to start operating from the beginning again, resulting in overcharging.Also, the timer would have to operate once for a long time, so there was a problem from the point of view of energy conservation.
て発明の目的〕
この発ゆjは上記欠点を解決するために成されたもので
、その目的とすることは、充電中(=停電等の一時中断
があった場合やユーザが過って充′亀完了後再び充電を
行っても、電池の過充電を避けると共(二、省エネルギ
ー効果をあげうる丸亀制御回路を提供するものである。[Purpose of the Invention] This invention was made to solve the above-mentioned drawbacks. 2. To provide a Marugame control circuit that can avoid overcharging of the battery even if the battery is charged again after completion of charging (2) and can save energy.
すなわちこの発明は従来のタイマー付の充電回路に、さ
ら(ニラッチ回路8、丞4磁圧発生器20、コンパレー
タ10及びゲート回路としてのトランジスタ9とを付加
してなることを%徴としている。That is, the present invention is characterized by adding a Niratch circuit 8, a magnetic pressure generator 20, a comparator 10, and a transistor 9 as a gate circuit to the conventional charging circuit with a timer.
この発明(二よれば蓄゛電池の容1が少ない時すなわち
初期の充電は蓄゛市亀低圧と卆′$電圧発生器と比較器
及びゲート回路と(二よって、蓄″電池への充電量が圧
右され、蓄電池の容量が規定値(二速した以後は、タイ
マー回路によって袖充磁及び表示用ランプ等(V報用)
のフジッシング動作が規足さ、れる、充゛−制呻回路で
ある。According to this invention (2), when the capacity of the storage battery is small, i.e., initial charging is performed, the amount of charge to the storage battery is is dominated, and the capacity of the storage battery is set to the specified value (after 2nd speed, the timer circuit charges the sleeve and displays the display lamp, etc. (for V report).
This is a filling-suppressing circuit that regulates the fujishing operation.
この発明は蓄電池の充′屯に除し充電動作そのものがダ
ブル構成となっていて、初期動作で規定充電を確保し、
2着目の動作で印慧時間だけ補充電を行うと共に、警報
装叙を備えつけることができる、又タイマー動作後は充
−回路はOFFとなる寺、省エネルギー効果、過充電防
止効果等がある。In this invention, the charging operation itself has a double structure depending on the charging period of the storage battery, and the specified charging is ensured in the initial operation,
In the second operation, supplementary charging is performed for the time required, and an alarm device can be installed, and the charging circuit is turned off after the timer operates, which has an energy saving effect and an overcharging prevention effect.
以下図面を呑照して、この発明の詳細な説明する。第2
図は、この発明(二係る充電制御111回路の一実施例
を示す構成図である。The present invention will be described in detail below with reference to the drawings. Second
The figure is a configuration diagram showing an embodiment of the charging control 111 circuit according to the present invention (2).
市原が投入されると同時にタイマー7はリセットされゲ
ート回路(トランジスタ)6はOFF状態を保持する。At the same time as Ichihara is turned on, the timer 7 is reset and the gate circuit (transistor) 6 is kept in the OFF state.
一方比較器10に入力される屯池電圧は粘準低圧発生器
加からの基準電圧よシも低いため、比較器10からの出
力はLowとなっている、この為ゲート回路を構成する
トランジスタ9はOFFとなっている。On the other hand, the voltage input to the comparator 10 is lower than the reference voltage from the viscous low voltage generator, so the output from the comparator 10 is Low. Therefore, the transistor 9 forming the gate circuit is OFF.
従って元逅詣2(二は正規のバイアスがかかυ発・1辰
器2は正常に11・9作する。従がって蓄電池5には充
′屯がなされる。Therefore, the main power supply 2 (2 is normally biased and the 1st power supply 2 is normally operated at 11.9. Therefore, the storage battery 5 is charged.
蓄−a池5に規定容皿充゛也されると、端子磁圧が基準
′低圧兄生器廁の基準電圧よシも高くなるため、比較器
用の出力がHighとなりトランジスタ9はONとなる
従って発振器21−は正規のバイアスがかからなくなり
、発振がとまる、・庇って蓄電池5への充電は中止され
る。When the storage battery 5 is filled with the specified capacity, the terminal magnetic voltage becomes higher than the reference voltage of the reference low-voltage generator, so the output for the comparator becomes High and the transistor 9 is turned on. Therefore, the normal bias is no longer applied to the oscillator 21-, and the oscillation stops, and the charging of the storage battery 5 is stopped.
一方比較器10の出力がHighとなることによシラツ
テ回路8がラッチされタイマー7がタイマー動作(二人
る。(ここで基準電圧発生器かは績準低圧として2つの
モードをとり、充fL中の基準電圧と放電中の基皐′シ
圧が異る、いわゆる、ヒステリシス特性をもつ電圧ヴ6
生器で充+fl中の重圧が放磁中の磁圧(充電が中止さ
れているときの′低圧)よシ葡い基準電圧を発生する。On the other hand, when the output of the comparator 10 becomes High, the output circuit 8 is latched and the timer 7 is operated (two modes). The voltage voltage V6 has so-called hysteresis characteristics, in which the reference voltage during discharge is different from the base voltage during discharge.
In the generator, the heavy pressure during charging generates a reference voltage that is higher than the magnetic pressure during discharge (low voltage when charging is stopped).
)
一方規定容量(−達した蓄電池5は充電が中止されるた
め(二、蓄I冠池5は放磁を開始する。蓄電池5の重圧
が基準電圧発生器10の基準゛重圧(1よいの重圧)(
二速すると、+1)び1民池は光重され、以説前述の動
作を;諜返す。一方タイマー7は一定時間経過するとタ
イムアツプ信号を出力する。このこと(二よシゲート回
路(トランジスタ6)6はONとなる。ここでトランジ
スタ9とトランジスタ6はOR回路を形成しているため
、−力のトランジスタがONすると以後はONしたトラ
ンジスタ(二圧右される。従って、発掘器2には正規の
バイアスがかからなくなシ、以後充電は中止される。以
上の動作(二よシ過光磁及び省エネルギー効果を生じさ
せることができる充゛屯制御回路を構成することがでさ
る。) On the other hand, charging of the storage battery 5 that has reached the specified capacity (-) is stopped (2. The storage battery 5 starts demagnetizing. pressure)(
When moving to second gear, +1) and 1 Minike are light weighted, and the above-mentioned movement is repeated. On the other hand, the timer 7 outputs a time-up signal after a certain period of time has elapsed. This (two-voltage gate circuit (transistor 6) 6 is turned on. Here, transistor 9 and transistor 6 form an OR circuit, so when the negative transistor turns on, the turned-on transistor (two-voltage right Therefore, the normal bias is no longer applied to the excavator 2, and charging is stopped from now on. Able to construct circuits.
第1図は従来レリ(−係る冗屯+ii制御回路の構成図
、第2図はこの発明(−係る光重1till +1回路
の一実施例を示゛ツtみ成図゛Cあ@。
1・・・半畳i4−搬01シ素子、2・・・発振器、3
・・・トランス、 5・・・′「1池、6.19
・・・トランジスタ、FIG. 1 is a block diagram of a conventional redundant +II control circuit, and FIG. 2 is a block diagram of an embodiment of a light weight +1 circuit according to the present invention. ...Half-tatami i4-carrier 01shi element, 2...Oscillator, 3
...Trance, 5...''1 Pond, 6.19
...transistor,
Claims (2)
圧とを比較する比較器と、該比較器の出力を受けて蓄′
屯池の光「Uを制御する第1のゲート回路と、該比較器
の出力を受けてラッチ動作を行うラッチ回路と、ラッチ
回路の出力を受けるタイマー回路と、タイマーからの出
力を支ける第2のゲー・ト回路と、弔lのゲート回路の
一部と第2のゲート回路の一部とを共通にしてOR回路
とをJ成することC二より蓄電時間を制御することを特
徴とする充電制御回路。(1) A comparator that compares the terminal voltage of the answering pond with the reference magnetic voltage of the reference voltage generator, and a
A first gate circuit that controls the light U, a latch circuit that receives the output of the comparator and performs a latch operation, a timer circuit that receives the output of the latch circuit, and a second gate circuit that supports the output from the timer. The second gate circuit, a part of the first gate circuit, and a part of the second gate circuit are used in common to form an OR circuit, and the battery storage time is controlled by C2. charging control circuit.
項の比較器の出力によって動作するラッチ回路の出力を
受けて、タイマー動作(二人ることを特徴とする特許6
N求の範囲第IJjJ、nピ械の充電制御回路。(2) The timer circuit and circuit in item (1) above are the same as in item (1) above.
Patent No. 6, which is characterized in that the timer operates (two people) in response to the output of the latch circuit that operates according to the output of the comparator.
Charging control circuit for the Nth range IJjJ, N pi machine.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20115082A JPS5992730A (en) | 1982-11-18 | 1982-11-18 | Charge control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20115082A JPS5992730A (en) | 1982-11-18 | 1982-11-18 | Charge control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5992730A true JPS5992730A (en) | 1984-05-29 |
Family
ID=16436211
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20115082A Pending JPS5992730A (en) | 1982-11-18 | 1982-11-18 | Charge control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5992730A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59207971A (en) * | 1983-05-09 | 1984-11-26 | パ−カ−・ケミカル・カンパニ− | Metal surface treatment with aqueous solution |
-
1982
- 1982-11-18 JP JP20115082A patent/JPS5992730A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59207971A (en) * | 1983-05-09 | 1984-11-26 | パ−カ−・ケミカル・カンパニ− | Metal surface treatment with aqueous solution |
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