JPS5992690A - Degaussing circuit - Google Patents

Degaussing circuit

Info

Publication number
JPS5992690A
JPS5992690A JP20329382A JP20329382A JPS5992690A JP S5992690 A JPS5992690 A JP S5992690A JP 20329382 A JP20329382 A JP 20329382A JP 20329382 A JP20329382 A JP 20329382A JP S5992690 A JPS5992690 A JP S5992690A
Authority
JP
Japan
Prior art keywords
triac
voltage
gate
circuit
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20329382A
Other languages
Japanese (ja)
Inventor
Susumu Ohashi
進 大橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP20329382A priority Critical patent/JPS5992690A/en
Publication of JPS5992690A publication Critical patent/JPS5992690A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/12Picture reproducers
    • H04N9/16Picture reproducers using cathode ray tubes
    • H04N9/29Picture reproducers using cathode ray tubes using demagnetisation or compensation of external magnetic fields

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Video Image Reproduction Devices For Color Tv Systems (AREA)

Abstract

PURPOSE:To eliminate contacts of the switch part of a degaussing circuit and to reduce the cost of the switch part greatly by connecting a posistor, degaussing coil, and triac in series between a power supply path and the ground. CONSTITUTION:One terminal of the serial circuit of the posistor 4 and demagnetizing coil 5 is connected to the current supply path 2 and the triac 20 is connected to the other terminal. The gate of the triac 20 is triggered by the voltage obtained by rectifying and smoothing pulses from the teriary winding of a flyback transformer 21. When a power source switch 8 is turned on at this time, the terminal voltage across a capacitor 24 rises excessively and the triac 20 turns on possibly in its rising; a means 25 of supplying a trigger to the gate of the triac 20 after the potential at a point A rises up to a specific value is provided for the prevention.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明に少なくとも一部分が地磁気などの影響によυ不
所望に着磁さル本米の動作に悪影響を与える虞れのある
機器において該不都合Y払拭するべく電源スイツチオン
と同眸に消磁を行なう必−〇ある電気機器、例えばテレ
ビジョン受像機等の消磁回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention is applicable to devices where at least a portion of the device may be undesirably magnetized due to the influence of earth's magnetism, etc., which may adversely affect the operation of the device. The present invention relates to a degaussing circuit for electrical equipment, such as a television receiver, which needs to be degaussed at the same time as a power switch in order to eliminate inconveniences.

(ロ) 従来技術 第1図に示すように従来にソケット(1)に接続さj、
た電源供給路(2)とアース間に電磁リレー(3)とポ
ジスタ(4)、消磁コイル(5)?順次接続し、且つ直
流電源(十B)とアース間にリレーコイル(6)と駆動
トランジスタi71 k M続し、テレビジョン受像機
の電源スィッチ(8)ヲ瞬時オンすることによってマイ
クロコンピュータ(9)の出力端子■O1tハイレベル
状態になし、このハイレベル電圧?抵抗ullu2で分
圧して駆動トランジスタ(7)のベースに加えて駆動ト
ランジスタ[7)tオンし、電磁リレー(3)?オンし
て電源供給路(2)から電磁リレースイッチUとポジス
タ14)、消磁コイル15)の直列路に変流′鑞流馨流
して消磁を行なうようになっている。ポジスタ+4+r
t。
(b) Prior Art As shown in Fig. 1, conventionally the socket (1) is connected to the
An electromagnetic relay (3), a POSISTOR (4), and a degaussing coil (5) between the power supply path (2) and ground? Connect the relay coil (6) and drive transistor i71kM between the DC power supply (10B) and the ground, and turn on the television receiver's power switch (8) instantly to connect the microcomputer (9). Output terminal ■O1t is not in high level state, is this high level voltage? The voltage is divided by the resistor ullu2 and added to the base of the drive transistor (7), and the drive transistor [7]t is turned on, and the electromagnetic relay (3)? When turned on, a transformer current flows from the power supply path (2) to the series path of the electromagnetic relay switch U, POSISTOR 14), and degaussing coil 15) to perform demagnetization. POSISTOR+4+r
t.

そこ?流れる電流による発熱で瞬時にして、その抵抗値
が増大し、電流?減衰せしめる。
There? The heat generated by the flowing current instantly increases the resistance value, and the current... attenuate it.

尚、第1図において、 (141はマイクロコンピュー
タ(9)の出力端子1101に発生する電圧によって制
菌されるスイッチ回路であシ、スイッチ[51とトラン
ジスタ(16Iと?備えていてオン状態のとき負荷面に
100vの直流電圧を供給する。0&(lαri電源供
給路(2)から与えらルるAc10[IVY整流する整
流ダイオードと平滑コンデンサである。
In FIG. 1, 141 is a switch circuit that is sterilized by the voltage generated at the output terminal 1101 of the microcomputer (9), and is equipped with a switch 51 and a transistor (16I), and when in the on state. A DC voltage of 100V is supplied to the load surface.A rectifier diode and a smoothing capacitor for AC10[IVY rectification are provided from the 0&(lαri power supply path (2)).

(ハ)本発明の目的 上記従来の消磁回路は機械的スイッチとしての電磁リレ
ー乞使用しているため大型でコスト高になると共に長期
の使用による信頼性の低下という問題が生じつる。
(c) Purpose of the Invention The conventional degaussing circuit described above uses an electromagnetic relay as a mechanical switch, resulting in a large size and high cost, and a problem of reduced reliability due to long-term use.

本発明d斯る点に鑑み電磁リレーを使用しない有効な消
磁回路を提案するものである。
In view of this point, the present invention proposes an effective degaussing circuit that does not use an electromagnetic relay.

に)本発明の構成 電源供給路とアース間にポジスタ、消磁コイル、トライ
アックを直列に接続し、電気機器内で生じる正の直流電
圧2所足の大きさになってから又は前記血流電圧の立ち
上り時間を短縮してトライブックのゲートに印カ目する
ようにした。
2) Configuration of the present invention A POSISTOR, a degaussing coil, and a TRIAC are connected in series between the power supply path and the ground, and after the positive DC voltage generated in the electrical equipment reaches the magnitude of two, or the blood flow voltage is Shortened the rise time and made the mark appear on the gate of the try book.

(ホ)本発明の実施例 本発明?実施した第2図以下において第1図と同一のも
のにつAては同一の記号?付して説明?省略する。
(e) Examples of the present invention Is this invention? Is the symbol A the same as that in Figure 1 in Figure 2 and below? Add and explain? Omitted.

本発明では第2図に示すように電流供給路(2)にポジ
スタ(4)と消磁コイル(5)の直列回路の一端?接続
すると共に、その直列回路の他@tトライアックf2P
a:’弁してアースに結合している。そして、該トライ
アック爆のゲートトリガはテレビ回路としての負荷α7
)においてフライバックトランス(ZD)6次巻線翰か
ら得ら7するパルス音ダイオード(ホ)で整流しコンデ
ンサ(財)(500μF程度の大きさ)で平滑してi6
vの直流電圧を発生する電源からの電圧で行なり。前記
16vの電源による直流電圧に負荷(In内のIC用電
源として用いらしているものでもある。尚、このような
負荷[171から得ら几る正の直流電圧を印加してゲー
トトリガーする場合、次のような問題が生じる。
In the present invention, as shown in FIG. 2, the current supply path (2) is connected to one end of a series circuit of a POSISTOR (4) and a degaussing coil (5). In addition to connecting the series circuit @t triac f2P
a: 'Valve connected to ground. And the gate trigger of the triac explosion is the load α7 as a TV circuit.
), the pulse sound obtained from the sixth winding of the flyback transformer (ZD) is rectified by a diode (e), smoothed by a capacitor (about 500 μF), and the i6
This is done using a voltage from a power supply that generates a DC voltage of v. The DC voltage from the 16V power supply is used as a power supply for the IC in the load (In).In addition, when applying a positive DC voltage obtained from such a load [171] to trigger the gate. , the following problems arise.

即ち、トライアックはゲートに正の直流電圧?加えてト
リガーする場合、トリガー電流の小さいときに第1、第
2電極間にかかるAC電圧の正部分のみ又Fi負部分の
みでしかオンしないという欠点があるが、このような事
態は電源スィッチ(8)ヲオンしてから16vの所定値
に達するまでコンデンサ(財)の両端電圧が過渡的に上
昇することから、その立ち上シ時に生じ易い。従って、
このような問題?克服するため第2図でtf(A1点の
電位が一足値に上ってから前記トライアック翰のゲート
にトリガーを与える手段に)?設けている。尚、トライ
アック□□□は負の直流電圧でゲートトリガーする場合
には上述の問題は生じないが、その代り、負の直流電圧
?形成する回路tわざわざ設けなければならない。
In other words, does the triac have a positive DC voltage on its gate? In addition, when triggering, there is a drawback that when the trigger current is small, only the positive part of the AC voltage applied between the first and second electrodes or only the negative part of Fi turns on. 8) Since the voltage across the capacitor rises transiently after it is turned on until it reaches the predetermined value of 16V, it tends to occur during startup. Therefore,
A problem like this? In order to overcome this problem, see tf in Figure 2 (after the potential at point A1 rises to a certain value, the means for giving a trigger to the gate of the triac wire)? It is set up. Note that the above-mentioned problem does not occur when the triac □□□ triggers the gate with a negative DC voltage. The circuit to be formed must be specially provided.

第6図は第2図の手段Of9?具体化した回路を示して
おシ、ここでは第2図の(A)点に結合するライン翰と
アース間に分圧抵抗(R1)(R2)Y接続すると共に
、それと並列にNPN)ランジスタ(TR1)のコレク
タ、エミツタ路及び抵抗(R3)y接続し、且つNT’
lJ トランジスタ(TR1)のベースを分圧抵抗(R
+)(R2)の接続中点(イ)圧結合している。尚、ト
ライアックノ0)のゲー)UNPN)ランジスタ(TR
I)のエミッタに汲続されている。
Is Fig. 6 the means Of9 in Fig. 2? A concrete example of the circuit is shown.Here, voltage dividing resistors (R1) (R2) are Y-connected between the line wire connected to point (A) in Fig. 2 and the ground, and an NPN) transistor ( TR1) collector, emitter path and resistor (R3) y are connected, and NT'
lJ The base of the transistor (TR1) is connected to the voltage dividing resistor (R
+) (R2) connection middle point (a) Pressure connected. In addition, triac no 0) game) UNPN) transistor (TR
It is connected to the emitter of I).

第6図において、ライン(4)の電位が所定電位に達す
るまで、接続中点(イ)の電位1jNPN)ランジスタ
(TR1,)7オンさせず、前記ラインの電位が所定電
位に達するとNPN)ランジスタ(TR1)Yオンさせ
る。従ってトライアック(4)に小さなゲート電流でト
リガーされることにないので第1、第2′at極間に加
わる交流の正負いず肚か一万のみでしか導通しないとい
うことが生じない。
In FIG. 6, the potential at the connection center point (A) 1jNPN) is not turned on until the potential of the line (4) reaches a predetermined potential, and when the potential of the line reaches the predetermined potential, the NPN) Turn on transistor (TR1) Y. Therefore, since the triac (4) is not triggered by a small gate current, it does not occur that the triac (4) conducts only at the positive and negative sides of the alternating current applied between the first and second poles.

叙上の通シ第2図、第6図ではトライアック■のゲート
に加わる小さ功直流電圧範囲ではトライアック圓のゲー
ト) IJガをかけないようにして上述の不都合を回避
しているが、前記直流電圧の立ち上シ時間を早くして、
小さなトリガー電圧がトライアックのゲートに加わる時
間を短かくしても前述の不都合を実質的に回避できる。
In the above-mentioned diagrams (Figures 2 and 6), the above-mentioned inconvenience is avoided by not applying IJ (in the range of the small DC voltage applied to the gate of the triac). Speed up the voltage rise time,
The aforementioned disadvantages can also be substantially avoided by reducing the time during which a small trigger voltage is applied to the gate of the triac.

このような発想から第4図でに第2図の(A)点に結合
する端子翰とアース間に抵抗(R4)とコンデンサ(c
l)を接続し、そのコンデンサ(C1)のホラ) 91
1に生じる電圧?トライアックCαのゲートにかけるよ
うにしている。例えばコンデンサ(C1)に100μF
1抵抗(R4)に1000程度とし、その光電時定数ン
小さくする。(M点の電位がOから16Vに立ち上がる
までに約1秒かかるのに対し、コンデンサ(C1)のホ
ット側の′電圧がOvから所定電圧(トライブックに上
記不都合の生じさぞない電圧)に立ち上がるまでには遥
かに短かい時間で済む。
Based on this idea, in Figure 4, a resistor (R4) and a capacitor (c) are connected between the terminal wire connected to point (A) in Figure 2 and the ground.
Connect l) and connect the capacitor (C1)) 91
Voltage generated at 1? I am trying to apply it to the gate of triac Cα. For example, 100μF for capacitor (C1)
Each resistor (R4) is set to about 1000, and its photoelectric time constant is made smaller. (While it takes about 1 second for the potential at point M to rise from O to 16V, the voltage on the hot side of the capacitor (C1) rises from Ov to a predetermined voltage (a voltage that does not cause the above problems in the trybook). It will take much less time.

第5図は消磁゛が終了した後はトライアック乞完全にオ
フにして残留消磁電流?零にするように構□成されてい
る。即ち、第5図でに第2図の(A)点に結合される端
子(財)とアース間に分圧抵抗(R5)(R1)Y接続
すると共にそれに並夕1jにノ(イアス抵抗(R7)、
PNP)ランジスタ(TR2)のx ミツl 、コレク
タ路及ヒ第1 :l ンf7す(C1)乞直列接続し、
更に抵抗(R6)と並列に第2コンデンサ(C2)、抵
抗(R5)と並列に第2コンデンサ(C2)の放電用ダ
イオード(Dl)乞接続し、前記PNPトランジスタ(
TR2)のベース乞a2コンデンサ(02)のホット側
に生じる電圧が印加されるように接続し、−万トライア
ツク(20)のゲートには第1コンデンサ(C1)のホ
ット側に生じる電圧を印加する様に構成している。
Figure 5 shows that after demagnetization is complete, the TRIAC is completely turned off and there is no residual demagnetization current. It is configured to make it zero. That is, in FIG. 5, a voltage dividing resistor (R5) (R1) is connected between the terminal connected to point (A) in FIG. R7),
PNP) transistor (TR2) x, collector path and first:l nf7 (C1) are connected in series,
Further, a second capacitor (C2) is connected in parallel with the resistor (R6), a discharging diode (Dl) of the second capacitor (C2) is connected in parallel with the resistor (R5), and the PNP transistor (
The base of TR2) is connected so that the voltage generated on the hot side of the A2 capacitor (02) is applied, and the voltage generated on the hot side of the first capacitor (C1) is applied to the gate of the TRIACK (20). It is configured like this.

斯る第5図の回路によれば端子(イ)の電圧が所定の値
に上昇するまで1PNP)ランジスタ(TR2)はオン
し、第1コンデンサ(、c+)y光電する。このとき抵
抗(R7)と第1コンデンサ(C1)の時定数により第
4図と同様の効果が生じる。
According to the circuit shown in FIG. 5, the transistor (1PNP) (TR2) is turned on until the voltage at the terminal (a) rises to a predetermined value, and the first capacitor (,c+)y is photoelectrically charged. At this time, the same effect as shown in FIG. 4 occurs due to the time constant of the resistor (R7) and the first capacitor (C1).

トライアック圓が導通して消磁動作が行なわれる。The triac circle becomes conductive and a demagnetizing operation is performed.

斯る状態で端子(イ)の電位が所定の値に達するとPN
P)ランジスタ(TR2)riオフになる。従って第1
コンデンサ(C1)の充電は行なわれず、残存する第1
コンデンサ(C1)の電荷がゲートトリガ電流として消
費されることによりトライアック(20)はオフに固定
される。このように第5図では消磁動作が行なわれた後
にトライアックにオフになるので残留消磁電流が流れる
ことがなく有効である。尚、PNP)ランジスタ(TR
2)のオフffl、第1コンデンサ(C1)の放電Y早
めるべく第1コンデンサ(C1)と並列に抵抗?接続し
てモJ: < 、1a2コンデンサ(C2)のホット側
に側副電極が接続され九NPN)ランジスタ?第1コン
デンサ(C1)と並列に接続【7てもよい。
In such a state, when the potential of terminal (A) reaches a predetermined value, PN
P) Transistor (TR2)ri turns off. Therefore, the first
The capacitor (C1) is not charged and the remaining first
The triac (20) is fixed off by consuming the charge of the capacitor (C1) as a gate trigger current. In this manner, in FIG. 5, the triac is turned off after the demagnetization operation is performed, so that no residual demagnetization current flows, which is effective. In addition, PNP) transistor (TR
2) Off ffl, resistor in parallel with the first capacitor (C1) to accelerate the discharge Y of the first capacitor (C1)? Connect MoJ: <, 9NPN) transistor with a collateral electrode connected to the hot side of the 1A2 capacitor (C2)? It may be connected in parallel with the first capacitor (C1) [7].

(へ)本発明の効果 本発明でに電磁リレーよシも安価で小型なトライアック
を用いるので消磁回路のスイッチ部のコストが大幅に減
少し、スイッチの無赫点化によシ信頼性も同上する。、
更に電磁リレーの、Lうな不快音が発生しないので殆ん
ど電子スイッチ化されているカラーテレビジョン受像機
等の機器のイメージ向とにも役立つ。ま友、本発明では
トライブック2用いる場合に生じる虞れのある動作上の
不都合Y、そ几に加えるゲートトIJガー信号系に手当
Y施して回避するようにしているのでトライアックによ
る極めて好適な消磁電流制卸が実現できるという効果が
ある。
(f) Effects of the present invention In the present invention, since an inexpensive and small triac is used for the electromagnetic relay, the cost of the switch part of the degaussing circuit is greatly reduced, and the reliability is also improved by making the switch non-dischargeable. do. ,
Furthermore, since electromagnetic relays do not produce unpleasant noises, they are useful for improving the image of equipment such as color television receivers, which are almost entirely electronically switched. Friend, in the present invention, the operational disadvantages that may occur when using the TRIAC 2 are avoided by taking additional measures to the gated IJ signal system, so the extremely suitable demagnetization by the TRIAC is achieved. This has the effect of realizing current control wholesale.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の消磁回路?示す回路図である。 第2図は本発明?実施した消磁回路の回路図であシ、第
6図はその要部を具体的に示す図である。 第4図は本発明の他の実施例の回路図である。第5図は
本発明の更に他の実施例の回路図である。 (2)・・・電源供i@路、(4)・・・ポジスタ、(
5)・・・消磁コイル、(8)・・・電源スィッチ、■
・・・トライブック、(ハ)用電圧が所定の大きさにな
ってから印加する手段、(C1)・・・電圧の立ち上が
り短縮用のコンデンサ。 駁 Oり 一艷 区 1か
Is Figure 1 a conventional degaussing circuit? FIG. Is Figure 2 the invention? FIG. 6 is a circuit diagram of the implemented degaussing circuit, and is a diagram specifically showing the main part thereof. FIG. 4 is a circuit diagram of another embodiment of the present invention. FIG. 5 is a circuit diagram of still another embodiment of the present invention. (2)...Power supply i@path, (4)...POSISTOR, (
5)... Degaussing coil, (8)... Power switch, ■
...Trybook, (C) Means for applying the voltage after it reaches a predetermined level, (C1)...Capacitor for shortening the voltage rise. Is it 1?

Claims (1)

【特許請求の範囲】 11)電気機器の電源供給路にポジスタと消磁コイルの
直列回路の一端を接続すると共に、その直列回路の他端
?トライアックを介してアースに結合し、前記電気機器
の電源スイッチ?オンしたときに前記電気機器内で生じ
る正の電圧を所定の大きさになってから若しくぼその電
圧の立ち上り時間を短縮して前記トライアックのゲート
に印加する手段を設けたことを特徴とする消磁回路。 121 11!気機器の電源供給路にポジスタと消磁1
ゴイルの直列回路の一端ン接続すると共に、その直列回
路の他端tトライアックを介してアースに結合し、前記
電気機器の電源スイッチ音オンしたときに前記電気機器
内で生じる正の電圧を前記トライアックのゲートに印加
すると共にその後、自動的に前記電圧を前記ゲートに対
し連断する手段を設けたことを特徴とする消磁回路。
[Claims] 11) Connecting one end of a series circuit of a POSISTOR and a degaussing coil to the power supply path of an electrical device, and the other end of the series circuit? 2. Power switch of electrical equipment coupled to ground via triac? The triac is characterized by being provided with means for applying the positive voltage generated in the electric device when it is turned on to the gate of the triac after it reaches a predetermined level or after shortening the rise time of the voltage. Degaussing circuit. 121 11! Posistor and demagnetizer 1 in the power supply path of the equipment
One end of the series circuit is connected to the other end of the series circuit, and the other end of the series circuit is connected to ground via a triac, and the positive voltage generated in the electrical equipment when the power switch of the electrical equipment is turned on is connected to the triac. 1. A degaussing circuit comprising means for applying the voltage to the gate of the circuit and then automatically connecting or disconnecting the voltage to the gate.
JP20329382A 1982-11-18 1982-11-18 Degaussing circuit Pending JPS5992690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20329382A JPS5992690A (en) 1982-11-18 1982-11-18 Degaussing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20329382A JPS5992690A (en) 1982-11-18 1982-11-18 Degaussing circuit

Publications (1)

Publication Number Publication Date
JPS5992690A true JPS5992690A (en) 1984-05-28

Family

ID=16471634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20329382A Pending JPS5992690A (en) 1982-11-18 1982-11-18 Degaussing circuit

Country Status (1)

Country Link
JP (1) JPS5992690A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825604A (en) * 1994-08-24 1998-10-20 Murata Manufacturing Co., Ltd. Demagnetization circuit
US6091198A (en) * 1997-08-29 2000-07-18 Stmicroelectronics S.R.L. Demagnetization circuit for cathode-ray tube video device
JP2008084371A (en) * 2006-09-26 2008-04-10 Nanayama Michishi Magnetic data erasing device
JP2009004022A (en) * 2007-06-21 2009-01-08 Nanayama Michishi Magnetic data erasing device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5284919A (en) * 1976-01-07 1977-07-14 Sanyo Electric Co Ltd Magnetic eraser circuit
JPS5431232A (en) * 1977-08-15 1979-03-08 Hitachi Ltd Magnetic eraser circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5284919A (en) * 1976-01-07 1977-07-14 Sanyo Electric Co Ltd Magnetic eraser circuit
JPS5431232A (en) * 1977-08-15 1979-03-08 Hitachi Ltd Magnetic eraser circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825604A (en) * 1994-08-24 1998-10-20 Murata Manufacturing Co., Ltd. Demagnetization circuit
US6091198A (en) * 1997-08-29 2000-07-18 Stmicroelectronics S.R.L. Demagnetization circuit for cathode-ray tube video device
JP2008084371A (en) * 2006-09-26 2008-04-10 Nanayama Michishi Magnetic data erasing device
JP2009004022A (en) * 2007-06-21 2009-01-08 Nanayama Michishi Magnetic data erasing device

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