JPS5990107A - Accelerating and decelerating circuit - Google Patents

Accelerating and decelerating circuit

Info

Publication number
JPS5990107A
JPS5990107A JP19923482A JP19923482A JPS5990107A JP S5990107 A JPS5990107 A JP S5990107A JP 19923482 A JP19923482 A JP 19923482A JP 19923482 A JP19923482 A JP 19923482A JP S5990107 A JPS5990107 A JP S5990107A
Authority
JP
Japan
Prior art keywords
acceleration
deceleration
circuit
result
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19923482A
Other languages
Japanese (ja)
Inventor
Hideaki Kawamura
川村 英昭
Takao Sasaki
隆夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP19923482A priority Critical patent/JPS5990107A/en
Publication of JPS5990107A publication Critical patent/JPS5990107A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/18Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
    • G05B19/416Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control of velocity, acceleration or deceleration

Abstract

PURPOSE:To reduce the route error by accelerating the feed speed up to an indicated level with drive of the mobile part of a machine tool or a robot hand, etc. and then performing the acceleration/deceleration control to decelerate the feed speed compared with the indicated speed in a fixed time and regardless of the speed change. CONSTITUTION:Shift registers 4a-4n are connected in series to each other, and the contents are shifted successively to the following registers by a shift pulse gamma. A rough interpolation device 301 delivers the shift amount component DELTAXn to the register 4a for each sampling. When the contents of registers 4a- 4n are referred to as A-N, the addition result XT of an adder 6 is obtained as shown in an equation I from results of multiplications of multipliers 5a-5n. The result XT is divided by a divider 7 to obtain a division result XD as shown by an equation II. The result XD is fed to a distributor 303 which functions as a fine interpolation device. Then an accelerated/decelerated distribution pulse XCP is delivered.

Description

【発明の詳細な説明】 本発明は、送り速度を指令速度まで加速し更に指令速度
から減速する加減速回路に関し、特に工作pA檄の可動
部やロボットのノ・ンドなどの駆動に好適な任意の加減
速特性が得られる加減速回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an acceleration/deceleration circuit that accelerates the feed speed to a command speed and then decelerates it from the command speed, and is particularly suitable for driving moving parts of work machines, robot nodes, etc. The present invention relates to an acceleration/deceleration circuit that provides acceleration/deceleration characteristics.

工作機械、ロボット等軸移動の制御を行なう制御装置に
かいては、一般に軸移動の開始時および減速時に機椋系
にショックや撮動を与えないようにするために加速、減
速がおこなわれる。か\る加減速方式としては以下に述
べる2つの方式がある。伺、以下X、Y2軸の直線補間
の場合について述べるが、それ以上の軸の場合あるいは
円弧補間等の場合についても全く同様である。又、サン
プリング周期をT1与えられた送り速度をFXX軸の移
動量をX、  Y軸の移動量をY1接線方向の移動量を
5(−V電■]=い−)とする。
In a control device that controls axial movement of machine tools, robots, etc., acceleration and deceleration are generally performed at the start and deceleration of axial movement in order to avoid applying shock or imaging to the machine system. There are two methods of acceleration/deceleration as described below. In the following, the case of linear interpolation for two axes, X and Y, will be described, but the same applies to cases of more axes, circular interpolation, etc. Further, the feed rate given the sampling period T1, the amount of movement on the FXX axis is X, the amount of movement on the Y axis is Y1, and the amount of movement in the tangential direction is 5 (-V electric) = Y-).

第1の加減速方式は粗補間器において、サンプリング周
期T毎にΔS=F・Tの演算を行なって接線方向の微小
な移動量成分ΔSを求め、ΔSから次式によりX勅、Y
軸方向の移動量成分ΔX、ΔYを求め、 ΔY−ΔS・□ v’¥’+y” とのΔX、ΔYに対して各軸独立に遅れを持たせて相補
間及び加減速を行なう方法である。第1図はか\る第1
の加減速方式を適用した制御装置のブロック図であり、
粗補間器101は送シ速度F、 X軸及びY軸の移動量
X、  Yを用いて(IL (21式から各骨の相補間
データΔX、ΔYを演算し、それぞれパルス分配器10
2X、  102Yに入力する。粗補間器としてのパル
ス分配器102X、  102Yは相補間データΔX、
ΔYに基いてパルス分配演算を行なって1サンプリング
時間の間にΔX、ΔYに相当する数の分配パルスXP、
YPを発生しそれぞれ加減速回路103X、103Yに
入力する。各加減速回路10!IX。
In the first acceleration/deceleration method, a coarse interpolator calculates ΔS=F・T every sampling period T to obtain a minute movement component ΔS in the tangential direction, and from ΔS, use the following equation to calculate
This method calculates the axial movement amount components ΔX and ΔY, and performs complementary interpolation and acceleration/deceleration by adding a delay to each axis independently for ΔX and ΔY of ΔY−ΔS・□v'¥'+y'' .Figure 1 is the first
It is a block diagram of a control device applying the acceleration/deceleration method of
The coarse interpolator 101 calculates complementary interpolation data ΔX and ΔY for each bone using the feed speed F and the travel amounts X and Y of the X and Y axes (IL
Input to 2X, 102Y. Pulse distributors 102X and 102Y as coarse interpolators receive complementary data ΔX,
A pulse distribution calculation is performed based on ΔY, and a number of distribution pulses XP corresponding to ΔX and ΔY are generated during one sampling time.
YP is generated and input to acceleration/deceleration circuits 103X and 103Y, respectively. Each acceleration/deceleration circuit 10! IX.

103Yは立上り時、立下シ時共に第2図に示すように
指数関数形で速度を加減速するものとすれば、第3図に
示す構成を有する。尚、第3図において3aはパルス分
配器102X(102Y)から出力される分配パ/l/
スXP (YP) c’:加減速回路103X (10
3Y)の出力パルスXCP (YCP )とを合成する
合成回路、3bは合成回路3aから出力されるパルスを
累積するレジスタ 3cはアキュームレータ、6dはレ
ジスタ3bの内容Eとアキュームレータ3Cの内容を一
定速度FcのパルスPが発生する毎に加算しその加算結
果をアキュームレータ3Cにセットする加算器である。
103Y has the configuration shown in FIG. 3, assuming that the speed is accelerated or decelerated in an exponential function manner at both rise and fall times as shown in FIG. 2. In addition, in FIG. 3, 3a is the distribution power /l/ output from the pulse distributor 102X (102Y).
SXP (YP) c': Acceleration/deceleration circuit 103X (10
3B is a register that accumulates the pulses output from the synthesis circuit 3a. 3c is an accumulator. 6d is a combination circuit that combines the contents E of register 3b and the contents of accumulator 3C at a constant speed Fc. This is an adder that adds up each pulse P every time it occurs and sets the addition result in the accumulator 3C.

今、分配パルスxPの速度をF、出カッゝルスXCPの
速度をF。とすれば次式が成立する。
Now, the speed of the distribution pulse xP is F, and the speed of the output pulse XCP is F. Then, the following formula holds true.

po−□・k!、(4J n 但し、アキュームレータ3cのビット数はnである。さ
て、上式において、(6)式はレジスタ3bの単位時間
当りの増分であり、(4)式はアキュームレータ3cか
ら単位時間当りに出力される桁上げパルス(出力パルス
°xcp )の数である。この(3)。
po-□・k! , (4J n However, the number of bits of the accumulator 3c is n. Now, in the above equation, equation (6) is the increment per unit time of the register 3b, and equation (4) is the increment per unit time from the accumulator 3c. This is the number of carry pulses (output pulses °xcp) to be output.This (3).

(4)式より、出力パルスF。を求めれば、Fo=F 
(1−exp(−kt))     (5)但し、k=
定数 となり、出力パルス速度F。は起動時指数関数的に加速
され、停止時指数関数的に減速される。
From equation (4), the output pulse F. If we find, Fo=F
(1-exp(-kt)) (5) However, k=
It becomes a constant and the output pulse speed F. accelerates exponentially when starting, and decelerates exponentially when stopping.

第1図に戻って加減速回路103X、 103Yにより
指数関数的に加減速された出力パルスXCP、 YCP
はサーボ回路104X、 104Yに入力され、それぞ
れサーボモータ105X、 105Yを駆動する。第4
図は粗補間器101による相補間の状態を示す説明図で
ある。
Returning to FIG. 1, the output pulses XCP and YCP are exponentially accelerated and decelerated by the acceleration/deceleration circuits 103X and 103Y.
are input to servo circuits 104X and 104Y, which drive servo motors 105X and 105Y, respectively. Fourth
The figure is an explanatory diagram showing the state of complementary interpolation by the coarse interpolator 101.

一方、第2の加減速方法は捕間器に入力する送り速度そ
のものに加減速をかけて、加減速を行なう方法である。
On the other hand, the second acceleration/deceleration method is a method of accelerating/decelerating by applying acceleration/deceleration to the feed rate itself input to the intersealer.

第5図は第2の加減速方法を実現するブロック図、第6
図は移動状態を説明する説明図である。第5図1・てお
いて、加減速回路201は第6図とほぼ同一構成を有し
、送り速度Fの立上り時、立下り時において出力パルス
Fjを指数関数的に加速及び減速させる。岡、減速は送
り速度Fのパルスが到来しなくなれば自動的に行われる
Figure 5 is a block diagram for realizing the second acceleration/deceleration method;
The figure is an explanatory diagram illustrating the moving state. In FIG. 51, the acceleration/deceleration circuit 201 has almost the same configuration as that in FIG. 6, and exponentially accelerates and decelerates the output pulse Fj when the feed rate F rises and falls. However, deceleration is automatically performed when pulses of feed rate F no longer arrive.

そして、減速を開始するタイミング(送り速度Fのパル
ス入力を停止するタイミング)は送り速度Fに応じた減
速距離(既知)が残移動量と等しくなったときである。
Then, the timing to start deceleration (timing to stop pulse input of feed rate F) is when the deceleration distance (known) according to feed rate F becomes equal to the remaining movement amount.

補間器202は加減速回路201から出力パルスFjが
発生する毎に移動量データX、  Yに基いてパルス分
配演算を行ない分配パルスXP、YPを発生し、サーボ
回路104X、 104Yヲ介してサーボモータ105
X、 105’l’を駆動する。この結果、第6図に示
すように起動時及び停止時において補間器202の出力
速度(1サンプリング時間における移動量)は漸増及び
漸減する。
The interpolator 202 performs pulse distribution calculation based on the movement amount data X, Y every time the output pulse Fj is generated from the acceleration/deceleration circuit 201, generates distribution pulses XP, YP, and outputs the pulses to the servo motor via the servo circuits 104X, 104Y. 105
X, drives 105'l'. As a result, as shown in FIG. 6, the output speed (the amount of movement in one sampling time) of the interpolator 202 gradually increases and decreases when starting and stopping.

以上のように、従来上記第1、第2の加減速方法が行わ
れている。このうち、第1の方法においては加減速制御
を補間と全く無関係に行なえばよく、単に補間を開始す
れば加速がか\す、補間を終了すれば減速がか\ること
になり、補間器や加減速回路自体の構成が簡単になると
いう利点を持っている。しかし、第1の方法は各軸に同
一の遅れを持たせることは難しく、独立な遅れを持って
いるため円弧補間の場合にはどうしても第7図に示すよ
うに加減速後の経路について誤差を生じる欠点を有して
いる。賞、第7図における半径誤差ΔRは、半径をR1
時定数をτ、指令速度をFとすれば近似的に となる。
As described above, the first and second acceleration/deceleration methods described above have been conventionally performed. In the first method, acceleration/deceleration control can be performed completely independently of interpolation; simply starting interpolation will cause acceleration, and ending interpolation will cause deceleration. This has the advantage of simplifying the configuration of the acceleration/deceleration circuit itself. However, in the first method, it is difficult to provide the same delay for each axis, and since each axis has independent delays, in the case of circular interpolation, it is inevitable to introduce errors in the path after acceleration and deceleration, as shown in Figure 7. It has its drawbacks. The radius error ΔR in Figure 7 is the radius R1.
If the time constant is τ and the command speed is F, then approximately.

一方、第2の加減速方法においては加減速制御により径
路の誤差を生ずるということは全くないという利点はあ
るけれども、特に減速に関して与えられた移動の終点で
正確に減速を終了させるためには、与えられた送シ速度
Fにオーバライドがかけられる等の送り速度の変更があ
ることを考慮して、時々刻々の送シ速度に従った必要な
減速距離および移動の終点までの残距離を常時把握して
おかなければならず、複雑な計算を必要とし、補間器お
よび加減速回路が非常に複雑と々るという欠点を持って
いる。
On the other hand, although the second acceleration/deceleration method has the advantage of not causing any path errors due to acceleration/deceleration control, in particular, in order to accurately terminate deceleration at the end point of a given movement, Considering that there may be changes in the feed speed such as an override being applied to the given feed speed F, the necessary deceleration distance according to the momentary feed speed and the remaining distance to the end point of movement are always known. It has the drawback that it requires complicated calculations and the interpolator and acceleration/deceleration circuit are extremely complicated.

以上から、本発明は径路誤差を小にすることができると
共に、加減速制御を簡単な回路構成で実現できしかも任
意の加減速特性が得られる新規な加減速回路を提供する
ことを目的とする。
From the above, it is an object of the present invention to provide a novel acceleration/deceleration circuit that can reduce path errors, realize acceleration/deceleration control with a simple circuit configuration, and obtain arbitrary acceleration/deceleration characteristics. .

以下、本発明の実施例を図面に従って詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.

第8図は本発明の実施例ブロック図(X軸につ  −い
てのみ詳細に示している)である。図中、301は粗補
間器であり、、 (1]、 fa式の演算を行なって1
サンプリング毎に各軸の相補間データ(移動量成分)Δ
Xn、ΔYnを発生し、加減速回路に入力する。
FIG. 8 is a block diagram of an embodiment of the present invention (only the X axis is shown in detail). In the figure, 301 is a coarse interpolator, which calculates 1 by calculating the formula (1) and fa.
Complementary interpolation data (travel component) Δ of each axis for each sampling
Generates Xn and ΔYn and inputs them to the acceleration/deceleration circuit.

4a、4b・・・4nはシフトレジスタであシ、各々移
動量成分ΔXnを記憶し、シフトパルスτにより順次後
段のシフトレジスタに移動量成分をシフトさせるもの、
5a・・・5nは各々乗算器であり、乗算器5a〜5n
はシフトレジスタ4a〜4nの記憶内容に、各々設定さ
れた係数に□〜knを乗算するものである。
4a, 4b, . . . , 4n are shift registers, each of which stores a movement amount component ΔXn, and sequentially shifts the movement amount component to a subsequent shift register by a shift pulse τ;
5a...5n are multipliers, and the multipliers 5a to 5n
is to multiply the stored contents of the shift registers 4a to 4n by respective set coefficients by □ to kn.

6は加算器であり、各乗算器5a〜5nの乗算結果を加
算するもの、7は除算器であり、加算器乙の加算結果を
、各乗算器5a〜5nに設定された係数に0〜knの和
で除算するもの、303はX軸のパルス分配器であり、
除算器7の除算結果に対応する数の分配パルスを出力す
るものである。
6 is an adder which adds the multiplication results of each multiplier 5a to 5n, and 7 is a divider which divides the addition result of adder B into the coefficient set in each multiplier 5a to 5n from 0 to 5n. The one that divides by the sum of kn, 303 is an X-axis pulse distributor,
It outputs the number of distribution pulses corresponding to the division result of the divider 7.

次に第8図の実施例構成の動作を第9図の動作説明図に
より説明する。
Next, the operation of the embodiment shown in FIG. 8 will be explained with reference to the operation diagram shown in FIG. 9.

各シフトレジスタ4a〜4nけ直列的に接続されており
、シフトパルスτにより順次次段のシフトレジスタに内
容がシフトされ、粗補間器301がらは1サンプリング
毎に最新の移動量成分ΔXnが出力され、シフトレジス
タ4aに入力される。従って、各シフトレジスタ4a〜
4nの内容をA−nとすると、粗補間器301から移動
量成分ΔXrhの出力されたサンプリング時点における
各乗算器5a〜5nは各々A−に、〜N−knとなる。
The shift registers 4a to 4n are connected in series, and the contents are sequentially shifted to the next stage shift register by a shift pulse τ, and the coarse interpolator 301 outputs the latest movement amount component ΔXn every sampling. , are input to the shift register 4a. Therefore, each shift register 4a~
When the content of 4n is A-n, each of the multipliers 5a to 5n at the time of sampling when the movement amount component ΔXrh is output from the coarse interpolator 301 becomes A- and ~N-kn.

これKより加算器乙の加算結果XTは次式の如くなる。From this K, the addition result XT of adder B becomes as shown in the following equation.

XT =A −k、+B−に2+・= 十N −kn 
   −(7)この加算結果XTを除算器7で次式の如
く除算され、除算結果XDを得る。
XT = A −k, +B− to 2+・= 1N −kn
-(7) This addition result XT is divided by the divider 7 as shown in the following equation to obtain the division result XD.

XD = XT/kT           (81こ
の除算結果XDは、精補間器として機能するパルス分配
器306に入力され、加減速制御された分配パルスXC
Pが出力される。
XD = XT/kT (81 This division result XD is input to the pulse distributor 306 which functions as a fine interpolator, and the distribution pulse XC which is acceleration/deceleration controlled is
P is output.

シフトパルスτが到来すると、各段のシフトレジスタの
内容は後段のシフトレジスタにシフトされる。
When the shift pulse τ arrives, the contents of the shift register at each stage are shifted to the shift register at the subsequent stage.

この加算器6、除算器7の演算は各サンプリング毎に実
行される。
The operations of the adder 6 and divider 7 are executed for each sampling.

この刃口減速回路の加速時間、減速時間はソフトレジス
タの数とシフトパルスτの周期によって定まり、シフト
パルスτの周期はサンプリングパルスの周期に等しいか
それ以下である。
The acceleration time and deceleration time of this cutting edge deceleration circuit are determined by the number of soft registers and the period of the shift pulse τ, and the period of the shift pulse τ is equal to or less than the period of the sampling pulse.

前述の乗算器5a〜5n1加算器6、除算器7は演算回
路を構成しているが、単一の演算手段、例えばマイクロ
プロセッサによっても構成できる。
Although the aforementioned multipliers 5a to 5n1, adder 6, and divider 7 constitute an arithmetic circuit, it can also be constituted by a single arithmetic means, for example, a microprocessor.

又、シフトレジスタの順次シフトに関して、演算時間上
の問題があれば、バッファレジスタで構成し、A−Nを
とり出すべきバッファがどれであるか、及びΔXnを格
納すべきバッファがどれであるかを示すポインタを設け
ることによってシフト動作を除去することができる。又
、第8図では図示してないが、除算器7で除算すると余
りが生じることを考慮して、アキュームレータと加算器
とを別途設け、各サンプリング周期での余りを加算して
7キユームレータに累積し、アキュームレータの内容が
kTを越えたとき除g器出力値に1を加算して送り出す
という方法をとれば精度の高い加減速が行なえる。
Also, if there is a problem in calculation time regarding sequential shifting of shift registers, it is necessary to determine which buffer should be configured with buffer registers to take out A-N and which buffer should store ΔXn. The shift operation can be eliminated by providing a pointer that indicates . Also, although not shown in FIG. 8, in consideration of the fact that a remainder is generated when dividing by the divider 7, an accumulator and an adder are separately provided, and the remainders at each sampling period are added and accumulated in the 7-accumulator. However, if the method of adding 1 to the output value of the divider and sending it out when the contents of the accumulator exceeds kT, highly accurate acceleration/deceleration can be performed.

次に第10図を参照しつつ本発明の具体例を示す。尚、
加速時定数を40m5eC,サンプリング周期Tをam
secとする。従って、シフトレジスタは5個(=40
/8 )である。又、加減速回路への入力ΔXnを10
とし、シフトレジスタ41〜45の初期値を零とする。
Next, a specific example of the present invention will be described with reference to FIG. still,
Acceleration time constant is 40m5eC, sampling period T is am
sec. Therefore, there are 5 shift registers (=40
/8). Also, the input ΔXn to the acceleration/deceleration circuit is 10
The initial values of the shift registers 41 to 45 are set to zero.

先づ、各乗算器51〜55の係数を全て〃1〃とすると
、第1サンプリング時刻に2いては(7)式の演算結果
XTはp、= 1 o、 B−N=0であるから10と
なり、よって除算器8の出力は2となる。
First, if the coefficients of each multiplier 51 to 55 are all 1, then at the first sampling time 2, the calculation result XT of equation (7) is p, = 1 o, BN = 0. Therefore, the output of the divider 8 becomes 2.

第2サンプリング時刻においては(7)式の演算結果X
Tは、A、B=lO1C−N=0であるから20となり
、よって除算器8の出力は4となる。
At the second sampling time, the calculation result of equation (7)
Since A, B=lO1C-N=0, T becomes 20, so the output of the divider 8 becomes 4.

以下、同様に徐算器出力は6.8.10と増大し、時定
数である40m5ec経過後に加減速回路への入力ΔX
n (−i 0 )と加減速回路出力が一致し、以後Δ
Xnが到来しなくなる迄、該加減速回路から一定の数値
10が出力される。そして、ΔXnの到来が終了すると
、(7)式の演算結〜stは、A=0、B〜N−10で
あるから40となり、除算器8の出力(は8となる。以
後、同様に徐算器出力は6,4゜2.0と減小し、時定
数40m5ec経過後に零となる。
Thereafter, the divider output similarly increases to 6.8.10, and after the time constant of 40m5ec has elapsed, the input ΔX to the acceleration/deceleration circuit
n (-i 0 ) and the acceleration/deceleration circuit output match, and from then on Δ
A constant value of 10 is output from the acceleration/deceleration circuit until Xn no longer arrives. Then, when the arrival of ΔXn ends, the calculation result ~st of equation (7) becomes 40 since A=0 and B~N-10, and the output of the divider 8 ( becomes 8. Thereafter, similarly The output of the divider decreases to 6.4°2.0 and becomes zero after a time constant of 40 m5ec has elapsed.

従って、第9図(Blの如くの加減速出力XDが得られ
、速度変化の大小を問わず時定数の時間をもって直綜加
速成いは減速が可能となる。
Therefore, an acceleration/deceleration output XD as shown in FIG. 9 (Bl) is obtained, and straight helix acceleration or deceleration is possible within the time constant regardless of the magnitude of the speed change.

一方、前述の例では、各係数を同一の値としたが、各係
数の値を変えると異なる加減速特性が得られる。例えば
前述の例において、係数k。y k4を0.5、k□r
 k3を1.0Xk2を2.0とすると、第9図(C1
の如く加減速出力が得られる。
On the other hand, in the above example, each coefficient was set to the same value, but different acceleration/deceleration characteristics can be obtained by changing the value of each coefficient. For example, in the example above, the coefficient k. y k4 is 0.5, k□r
If k3 is 1.0Xk2 is 2.0, then Figure 9 (C1
Acceleration/deceleration output can be obtained as shown below.

これらは、サーボ回路やサーボモータの特性によって任
意に設定出来、しかも係数の設定のみによって容易に達
成できる。
These can be set arbitrarily depending on the characteristics of the servo circuit and servo motor, and can be easily achieved only by setting coefficients.

以上説明した様に、本発明によれば、各軸方向の移動量
成分をnサンプリング分記憶する記憶部と、これら移動
量成分に所定の係数を乗算し、この乗算結果を係数の和
によって除算する演算回路とを有するので、加減速時間
は、速度変化の大小を問わず一定の時間で加速成いは減
速できるので、各軸の遅れの相違は生ぜず、補間された
通路の誤差が生じないという効果を奏する他に、任意の
加減速特性を得られるので、サーボ系の特性に合わせた
最適な特性を設定出来、高速位置決めや高速切削も可能
となるという優れプζ効果も奏する。更にこの加減速特
性の設定も乗算係数の変更のみで極めて容易に達成出来
るという効果を奏し、又構成も複雑化せず簡単であると
いう効果も奏する。
As explained above, according to the present invention, there is provided a storage section that stores n samplings of movement amount components in each axis direction, a storage section that multiplies these movement amount components by a predetermined coefficient, and divides this multiplication result by the sum of the coefficients. Since the acceleration/deceleration time can be accelerated or decelerated in a constant time regardless of the magnitude of the speed change, there is no difference in the delay of each axis, and there is no error in the interpolated path. In addition to the effect that there is no acceleration or deceleration, arbitrary acceleration/deceleration characteristics can be obtained, so the optimum characteristics can be set according to the characteristics of the servo system, and high-speed positioning and high-speed cutting are also possible. Further, the setting of the acceleration/deceleration characteristics can be achieved extremely easily by simply changing the multiplication coefficient, and the configuration is also simple without becoming complicated.

伺、本発明を一実施例により説明したが、本発明はこの
実施例に限られず、本発明の主旨の範囲内で種々の変形
が可能であり、本発明の範囲からこれらを排除するもの
ではない。
Although the present invention has been described with reference to one embodiment, the present invention is not limited to this embodiment, and various modifications can be made within the scope of the gist of the present invention, and these are not excluded from the scope of the present invention. do not have.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の第1の加減速方式を適用したブロック図
、第2図は第1図における指数関数形加減速の説明図、
第6図は第1図に用いられる指数形加減速回路のブロッ
ク図、第4図は第1の加減速方式の説明図、第5図は従
来の第2の加減速方式を通用したブロック図、第6図は
従来の第2の加減速方式の説明図、第7図は従来の第1
の加減速力式による径路誤差説明図、第8図は本発明の
実施例ブロック図、第9図は本発明の説明図である。 図中、501・・・粗補間器、303・・・パルス分配
器、4a〜4n・・・シフトレジスタ、5a〜5n・・
・乗IE器、6・・・加算器、7・・・除算器 特許出願人 ファナソク株式会社
Fig. 1 is a block diagram applying the conventional first acceleration/deceleration method, Fig. 2 is an explanatory diagram of exponential function type acceleration/deceleration in Fig. 1,
Fig. 6 is a block diagram of the exponential acceleration/deceleration circuit used in Fig. 1, Fig. 4 is an explanatory diagram of the first acceleration/deceleration method, and Fig. 5 is a block diagram of the conventional second acceleration/deceleration method. , Fig. 6 is an explanatory diagram of the conventional second acceleration/deceleration method, and Fig. 7 is an explanatory diagram of the conventional first acceleration/deceleration method.
FIG. 8 is a block diagram of an embodiment of the present invention, and FIG. 9 is an explanatory diagram of the present invention. In the figure, 501... coarse interpolator, 303... pulse distributor, 4a to 4n... shift register, 5a to 5n...
・Multiplier IE, 6... Adder, 7... Divider Patent applicant Fanasoku Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] (1)送り速度を指令速度まで加速し或いは減速する加
減速回路において、サンプリング周期α)毎に各軸方向
の移動量を演算する手段と、各軸方向の移動量成分をn
サンプリング分記憶する記憶部と、該記憶部に記憶され
るnサンプリング分の移動量成分の各々に、各々に対応
して設定された係数を乗算し、且つ各乗算結果を加算し
た後、加算結果を該係数の和によって除算する演算回路
とを有することを特徴とする加減速回路。
(1) In an acceleration/deceleration circuit that accelerates or decelerates the feed speed to a command speed, there is a means for calculating the amount of movement in each axis direction at every sampling period α), and a means for calculating the amount of movement in each axis direction by n.
After multiplying each of the movement amount components for n samplings stored in the storage unit by a coefficient set correspondingly to each of the storage unit that stores the number of samplings and adding the respective multiplication results, the addition result is calculated. An acceleration/deceleration circuit comprising: an arithmetic circuit that divides the sum of the coefficients by the sum of the coefficients.
(2)前記記憶部が各々移動量成分を記憶するnヶのシ
フトレジスタで構成されたことを特徴とする特許請求の
範囲第(1)項記載の加減速回路。
(2) The acceleration/deceleration circuit according to claim (1), wherein the storage section is composed of n shift registers each storing a movement amount component.
(3)前記演算部は、前記シフトレジスタに対応して設
けられ、前記係数を乗算するnヶの乗算器を含むことを
特徴とする特許請求の範囲第(22項記載の加減速回路
(3) The acceleration/deceleration circuit according to claim 22, wherein the arithmetic unit is provided corresponding to the shift register and includes n multipliers that multiply the coefficients.
(4)前記演算部は、更に最前段のシフトレジスタに入
力される移動量成分に前記係数を乗算する乗算器を更に
含むことを特徴とする特許請求の範囲第(3)項記載の
加減速回路。
(4) The acceleration/deceleration according to claim (3), wherein the calculation unit further includes a multiplier that multiplies the movement amount component inputted to the shift register at the frontmost stage by the coefficient. circuit.
JP19923482A 1982-11-13 1982-11-13 Accelerating and decelerating circuit Pending JPS5990107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19923482A JPS5990107A (en) 1982-11-13 1982-11-13 Accelerating and decelerating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19923482A JPS5990107A (en) 1982-11-13 1982-11-13 Accelerating and decelerating circuit

Publications (1)

Publication Number Publication Date
JPS5990107A true JPS5990107A (en) 1984-05-24

Family

ID=16404383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19923482A Pending JPS5990107A (en) 1982-11-13 1982-11-13 Accelerating and decelerating circuit

Country Status (1)

Country Link
JP (1) JPS5990107A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114604A (en) * 1982-12-22 1984-07-02 Yaskawa Electric Mfg Co Ltd Acceleration and deceleration controlling system of industrial robot
JPS6142008A (en) * 1984-08-03 1986-02-28 Sankyo Seiki Mfg Co Ltd Robot course controller
JPS61245209A (en) * 1985-04-23 1986-10-31 Fanuc Ltd Acceleration and deceleration control system
JPS61249119A (en) * 1985-04-26 1986-11-06 San Esu Shoko Co Ltd Servo control method
EP0264453A1 (en) * 1986-03-20 1988-04-27 Fanuc Ltd. Injection molding machine capable of changing the acceleration/deceleration time for injection speed
JPS63146105A (en) * 1986-12-10 1988-06-18 Mitsubishi Electric Corp Locus controller
JPS63273107A (en) * 1987-04-30 1988-11-10 Fanuc Ltd Robot controller
JPH11102215A (en) * 1997-09-26 1999-04-13 Matsushita Electric Ind Co Ltd Unit and method for control, and device and method for filtering
JP2011224694A (en) * 2010-04-19 2011-11-10 Panasonic Corp Method for generating speed command profile of multi-joint robot

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5014101A (en) * 1973-06-11 1975-02-14
JPS5059680A (en) * 1973-09-27 1975-05-23
JPS5633703A (en) * 1979-08-25 1981-04-04 Fanuc Ltd Signal converting circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5014101A (en) * 1973-06-11 1975-02-14
JPS5059680A (en) * 1973-09-27 1975-05-23
JPS5633703A (en) * 1979-08-25 1981-04-04 Fanuc Ltd Signal converting circuit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114604A (en) * 1982-12-22 1984-07-02 Yaskawa Electric Mfg Co Ltd Acceleration and deceleration controlling system of industrial robot
JPH0561650B2 (en) * 1982-12-22 1993-09-06 Yaskawa Electric Corp
JPS6142008A (en) * 1984-08-03 1986-02-28 Sankyo Seiki Mfg Co Ltd Robot course controller
JPS61245209A (en) * 1985-04-23 1986-10-31 Fanuc Ltd Acceleration and deceleration control system
JPS61249119A (en) * 1985-04-26 1986-11-06 San Esu Shoko Co Ltd Servo control method
EP0264453A1 (en) * 1986-03-20 1988-04-27 Fanuc Ltd. Injection molding machine capable of changing the acceleration/deceleration time for injection speed
JPS63146105A (en) * 1986-12-10 1988-06-18 Mitsubishi Electric Corp Locus controller
JPS63273107A (en) * 1987-04-30 1988-11-10 Fanuc Ltd Robot controller
JPH11102215A (en) * 1997-09-26 1999-04-13 Matsushita Electric Ind Co Ltd Unit and method for control, and device and method for filtering
JP2011224694A (en) * 2010-04-19 2011-11-10 Panasonic Corp Method for generating speed command profile of multi-joint robot

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