JPS5988865A - Method of producing charge storage region of semiconductor substrate - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION This invention relates to the field of integrated circuit devices and, more particularly, to a manufacturing process for highly backed memory cell capacitance devices for highly integrated dynamic RAM. The present invention relates to the method and resulting structure.

Today, dynamic random access memory (RAM)
The device has thousands of individual memory cells, each containing a transistor and a capacitor.

A capacitor can hold a bit of information by being in a charged or uncharged state, and a transistor connects the capacitor to the rest of the RAM device so that information can be read from or written to the capacitor. Acts as a switch to electrically connect.

Ideally, memory cell capacitors should have large capacitance per unit area. This allows the capacitor to be densely packed to allow very high concentrations of semiconductor substrates without having to increase the sensitivity of the sense amplifier that would read the amount of charge stored on the capacitor. Can be made physically smaller to be backed up. As a result of efforts to achieve high capacity per unit area memory cell, "ENCHANCFD
C△PACITORFOR0NE-TRANSTS
TORMEMORY CELL,”IEEETRAN
S, ELECTRON DEVICES, VOL, E
D-23, ρI), 1187-1189.0ctobe
R 1976 by C, Q, 3odin 1 and T, I, Kamins discloses a ``++-c'' RAM memory cell and also A, F.

TASCH,ET AL,,”THE I”l-C
RAM CELL C0NCEPT,”IEEET
RANS, ELECTRON DEVICES.

VOL, ED-25, No, 1.1) Fl, 33-4
A RAM memory cell extended by 1°JanLIaryl 978 was obtained.

This concept involves implanting an impulse impurity layer onto a second impurity layer of the other polarity of the semiconductor substrate. A capacitor oxide layer is formed on the substrate and a conductive layer is formed on top of the oxide layer to form a capacitor device. This structure has increased capacitance because there is a two-component capacitor.

The first is the oxide capacitance, which is the capacitance between the conductive layer overlying the gate oxide and the substrate below the gate oxide, and the second is the depletion layer capacitance;
It is formed by the juxtaposition of two implanted dopant layers of opposite polarity. This structure is contrasted with the standard structure of Dyminac RAM cell capacitors, which have only oxide capacitance. The new structure has a very large capacity per unit area.

The present invention is a method of manufacturing H+-C memory cell capacitor devices, whereby such capacitors are backed together to the greatest extent possible for a particular processing technology and resulting device structure. . In this invention, each of the capacitor devices is well defined with respect to each other so that each capacitor remains electrically isolated from the others to preserve its electrical integrity. Space savings achieved in semiconductor substrates17
- and the overall RAM integration is increased.

SUMMARY OF THE INVENTION One embodiment of the present invention is a method for manufacturing a charge storage region in a semiconductor substray 1, which includes the steps of forming an insulating layer on the substray 1, and forming a mask layer over the insulating layer. step and add a small amount to the mask layer (
forming one aperture with each other;
The aperture defines a charge storage region in the semiconductor substrate and provides a first charge storage region for diffusion through the substrate.
implanting a dopant region of polarity through the aperture; and implanting dopant ions of a second polarity through the aperture to diffuse through the substrate to a lesser extent than the first polarity dopant diffusion, thereby implanting a second polarity dopant region through the aperture. forming a P-N junction substantially aligned with an edge of the opening in the mask layer such that the diffusion of the first polar dopant defines a periphery of the charge storage region with respect to the diffusion of the polar dopant.

One method of diffusing the second polarity dopant to a lesser extent than the primary polarity dopant in the substrate is to select a first polarity dopant that has a greater diffusivity than the second polarity dopant. Examples of such first and second polar dobans 1- are boron and arsenic, respectively.

Another way to achieve the desired diffusion of the first polarity dopant 1~ with respect to the second polarity dopant +- is to select two polarity dopant 1- with approximately equal diffusivities and the second polarity dopant to the semiconductor substrate. Diffusion of the first polarity dopant before implantation. The first J3 and second polar dopants with approximately equal diffusivities are boron and phosphorus, respectively.

Yet another method of forming a plurality of charge storage regions in a semiconductor substrate includes forming a first insulating layer over the Zabus 1-rate and forming a first masking layer over the first insulating layer. the first step on the substrate.
forming an aperture in the first mask layer to define a region; implanting ions of a first polarity Dovan l- through the aperture to a predetermined concentration in the substrate; forming a second mask layer on the first insulating layer;
forming a plurality of apertures in the second mask layer, each of the apertures being disposed to substantially cover the first region; each second mask layer such that the concentration of the second polarity dopant defines the periphery of the charge storage region with respect to the concentration of the first polarity dopant. forming a P-N junction substantially aligned with an edge of the vertices of the method.

Various I'l fabrication methods result in semiconductor device structures having a plurality of adjacent capacitive devices that define a charge storage region and have a second capacitor on the surface of the semiconductor substrate.
a plurality of regions each having a dopant of polarity and extending to one knob straight, each having a dopant of the same first polarity and extending to the substrate and each having a dopant of a second polarity at the surface; a plurality of regions disposed between the second polarity dopant regions to form a P-N junction at the interface between the first and second polarity dopant regions for electrically dividing the regions;
an insulating layer covering the first and second polar regions (the thickness of the insulating layer covering the first polar region is 1000 angstroms or less); and a conductive layer covering the insulating layer, thereby forming a conductive layer and a charge storage region. and a portion of the insulating layer above the charge storage region forms a capacitive element.

detailed description FIG. 1 shows a circuit diagram of a +-+;-C memory cell.

The memory cell has an access transistor 13, which
- one terminal of the transistor is connected to the pit line 11 and the other terminal to the charge storage capacitor 17; This capacitor 17 has two components: an oxidation capacitance and a depletion layer capacitance.

In FIG. 1, the oxidation capacitance is represented by another capacitor 15, and the depletion layer capacitance is represented by capacitor 21-16. One plate of the capacitor 15 is grounded and the other plate 1- of the capacitor 16 of the depletion layer is at the voltage Vaa, which is the backgate generated in the bulk to the semiconductor substrate 1;
or subs 1-rate bias. The gate 14 of the 1-heran jitter 13 is connected to the word line 12. The signal on word line 12 turns on transistor 13 so that the contents of the storage capacitor are electrically accessible to bit line 11.

FIG. 2A is a top view of a pair of adjacent memory cells, each of which has a lightly P-doped silicon rib straight 1
0 and corresponds to the circuit diagram shown in FIG. This pair represents thousands of memory cells in one RAM device. The dotted and dashed lines indicate some of the divine masks used to form the memory cells on the sub-stray 1 by conventional processes, which include the lines 25 to separate each memory cell from the others.
A source/drain mass 22- is used. Point 11i 123 represents a condenser mask that covers the portion of the substrate outside the capacitor region during the dual implantation of P and N type dopants. A polysilicon 7 screen is shown bounded by a dashed line 26, which connects the capacitor 17 to the field play 1 27 and the goo 1 electrode 14 for the access l-run raster 13 of each memory cell. stipulates.

The first factor line 12 for each of the memory cells of FIG. 2A.
The physical word line indicated by is Darashico line 2
Extending perpendicularly to the bit lines 11 over an insulating layer of silicon dioxide overlying the polysilicon layer as defined by the mask outlined at 6. Each word line is absolutely perfect! Through the aperture in the I layer, each access 1 to the transistor 13 (to the electrode 14 of the X'' mark shown) is contacted.

Neither the word line nor the silicon dioxide insulating layer is shown.

A cross-sectional view of one of the memory cells of FIG. 2A taken along line A--A is shown in FIG. 2B. Substray 1-1
0 is covered by a field oxide layer 31 in the 74-field regions of the substratum t-1 note 10, i.e., these regions are Substrate 1
3 outside the active area of substrays 1-10 to prevent floating channels from forming between the active areas of substrays 1-10.
A field implant 30 of type dopants underlies the field oxide layer 31. Pit 1 to line 11 is Tonneau (N
+) heavily doped fnVj with impurities. Bit line 11 is also connected to each access 1
3, which has a polysilicon layer -1-14 and another source/drain region Vi21, which is also an N'' region. A capacitor for each memory hill is connected to the first part of the acceptor impurity (P+). A charge storage region of the substrate is thus formed by the injection layer 24 and the second injection layer 23 of N+ impurity. In Figure 1, this offset is not shown as C8. There is an oxide layer 28 and at its L a polysilicon layer 27 forming the field plate of the capacitor. is applied to the capacitor 16. In FIG.
It is denoted as o, ,.

Figures 3A, 3B and 3C are one or three views showing portions of conventional processing techniques used to form the slope of a capacitor device; It is a sectional view of cut 1).

The conventional process is N+R23 and P+If2
Using the insulating field oxide layer as a mask to form the double-implanted charge storage region at 4 and at the same time point!
A capacitor mask, indicated at 23, prevents implantation outside these areas.

Field infusion 31 is formed from an initial silicon oxide layer 22 several hundred angstroms thick covering substrays 1-10. A silicon nitride layer 29 in accordance with the well-known A-trisograno technique is defined over the barrier oxide layer 22 by a source/train mask delimited by the dotted line 25 in FIG. 2A. However, a photolithographic mask of NoA abrasive is also used for field implantation into the fR region 30A of Substray 1 before the NoA t-Resist 1 is removed. The substrate is then heated in an oxidizing environment, thereby leaving the nitride layer 29 exposed7. :1122 is covered with a suitable field oxide layer (approximately 10,000 onguest [1
- the initial implant region 30Δ extends into the field implant region 30 disposed below. Nitride layer 29
The portion of barrier oxide 822 under is masked, so
These parts do not grow. Oxide attack, nitride 1!29 and thin barrier oxide story 22 are removed. FIG. 3B shows the state of the rib straight at this stage.

It should be noted that the two drawings here are representative and do not ensure true scale, and the field oxide 31 in Fig. 3B and the field oxide 31 in Fig. 3A.
A comparison of the thickness of barrier oxide layer 22 in the figure illustrates this point.

The downward arrow shown in FIG. 3B indicates a double implant of P and N type dopanes 1 to 1, with mask field oxide 31 and photoresist capacitor mask 2A.
It is defined by line 23 in the figure. FIG. 3C shows the completed "densor", each of which has 1) + and N4 layers 2
3 and 24, respectively, and a field injection region 30 in sub-rates 1-10.

Capacitor oxide 28 is regrown over the charge storage region and polysilicon field plays 1-27 are formed over the now fully isolated sub-layers 1-10.

Upon closer examination of Figures 2A, 3A, 3B and 3C, some of the deficiencies of the conventional process can be seen. For a given photolithography process, there is a maximum resolution that can be achieved. For today's projection alignment techniques that use light-C, the maximum resolution of the mask for the FTREGIS1~MATERIAL appears to be about 2 microns. The above conventional process requires photoresist nitride layer 29 over the charge storage region to define the nitride mask for the field oxide layer. 2 microns (in situations where the condenser is used to define the separation between capacitors for a photomask) 1st - more photoresist than the lithographically defined aperture is necessarily removed, 2 or 2.
It has been found that 5 microns gives the actual separation distance of the Photolgis 1-14 material.

Additionally, the underlying nitride layer 29 that is exposed between the charge storage regions must be etched and removed. This further increases the separation distance.

This is because more than the exposed nitride layer 29 is removed by undercutting into the nitride layer below the photoresist 1.

This is a natural result of Etzings' development.

Thus, the actual MS shown in FIG.
: greater than the specified separation of 2 microns imposed.

Still other drawbacks of the conventional process are apparent.

With each capacitor having a width W, the nitride layer 29 separates S and J to define the charge storage area of each capacitor.
: Formed by two mask nitride layers with a width W. After the thick field oxide 31 is formed, the field oxide 3
1 has a taper in thickness so that over the charge storage region of the substrate 10 it is capacitor oxide 1128
It can be seen that it is entering inside. This means that the oxide thickness just outside the charge storage region is equal to the gate oxide thickness.
It appears to be essential in structures with a ratio of 0:1 or higher. As a rough rule of thumb, this intrusion by field oxide 31 into goo 1-1 oxide 28 is approximately the thickness of the field oxide. Reduces the total capacitance of the device.Assuming a capacitor aW with the dimensions given above and in a typical 29-type of 6 microns, the actual width is reduced to 4 microns.A corresponding severe reduction in capacitance To compensate for this loss, the capacitor width W may be increased. However, such an increase increases the sum of the capacitor pitch widths W, J, and the separation S. The width is increased to take up more space, which reduces the back density of the memory cell.Similarly, if the length of each capacitor were instead increased, the same undesirable result would occur.Memory cells today R of
Since AM is copied thousands of times, this compensation is
This has an immediate negative impact on the back density and bump size of the M element.

On the other hand, the invention may take all the advantages of a particular photolithography technique.

The ridged photolithographic mask of this invention is outlined 1) in FIG. The invention begins with a light (doped acceptor concentration of about 5 x 10"/C1) on a silicon substrate 10, and a barrier oxide H4,2 of a few hundred to approximately 1000 angstroms to a loam thickness of 500 ng/cm. A layer of silicon nitride is formed over the silicon dioxide to a thickness of about 1000 angstroms. Portions of the nitride layer are then , removed to form a source/drain mask contoured by dashed lines 45. With a silicon nitride layer formed over the active area of the substrate, field implantation of acceptor impurity ions is then performed. to the field area to the sub-storey 1 as described in 1. Then, using silicon nitride as a mask, the exposed barrier oxide layer is etched by about 1000 nm to form the field oxide 31.
It is grown to a thickness of 0:4 angstroms. In this regard, field oxide does not appear between adjacent charge storage regions to any significant extent. The source/drain mask bounded by line 45 in FIG. 4 is different from the source/drain mask in FIG. 2A.

The remaining nitride and barrier oxide layer below the nitride layer is removed by a simple etching technique.

Subsequently, the second oxide layer 52 has a thickness of 100': 30
The substrate is grown over the exposed active areas of substrays 1-10 to a thickness in the range of 0 Angstroms (200 Angstroms 1-Roam is optimal). A capacitor mask of photoresist material 49 is formed that at least partially delineates the charge storage area and is delineated by dashed line 43 . Nootregis 1 - material and thick field oxide 31 , i.e. ion implantation of Zabus 1 - rate 10 boron through an aperture defined by the area bounded by dotted and solid lines 43 and 45 to form a pre-implanted layer. Create a size of 53△. After this, an arsenic implant is performed to create preliminary layer 54A.

The amount of boron (P41 is 10 in substrate 10)
10+9 ions/C1 at 0 KeV, and arsenic (N
+) is 10'4 ions/am2 at 100 KeV. The exposed portions of thin oxide layer 52 are then etched away and photoresist 49 is stripped.

What remains is the exposed surface of the substrate surrounded by dotted lines 43 and an approximately 200 angstrom thick oxide layer 52 between adjacent charge storage regions. Due to the oxidation step, the exposed Zabus 1-Rate 10 has an oxide layer regrown thereon to a thickness of 300 to 500 Å, i.e., a capacitor oxide region 58, between the charge storage regions. Region 51 is thinned to 450 to 650 angstroms. It has been found that a capacitor oxide thickness of 400 Angstroms and a thickness of 550 Angstroms to Rohm for the oxide not covering the charge storage regions are very effective oxide layer dimensions. Thus, an oxide thickness ratio of 2:1 or less is created compared to conventional process structures. In fact, the photoresist 49 is first stripped, the thin oxide layer 52 is completely removed, and then the substrate 10 is removed.
By growing the oxide layer over again, the capacitor oxide region 52 and the isolation oxide region 51 can have the same thickness, ie, a 1:1 ratio 33-. Such a structure is also effective. l-) A common feature of the small process and its variations is that the thickness of the oxide region 51 is much smaller than the typical field oxide of ROHM, and the thickness of the oxide region 51 is much smaller than the typical field oxide of ROHM, and the thickness of the small grain, 1000 Å [ This means that it is below J-m. The benefits of this are discussed below.

With the substrate oxidized, a polysilicon layer is formed over the substrate 1- to a thickness of approximately 3000 Å 1-Roam, and is indicated by dashed line 46, as shown in FIG. 2A. With the same polysilicon mask on, field play 1- is formed over the charge storage region.

The same polysilicon layer also forms the Goo1-T1 poles 44 over the Access1 transistor.

Following the formation of the capacitor field blank 47 and the access transistor electrode 44, a source/drain implant of arsenic is performed to dope these portions of the polysilicon layer 41 and to fill the access transistor and Form N+34- source and drain regions of Pit 1-line 11.

Finally, the substrate is placed in an oxidizing environment and
A "drive-in step" is performed at a temperature of 00°C or higher. A typical set of parameters for such a step is 1030° C. for 70 minutes. One of the effects of this step is that the arsenic and boron impurity implants diffuse differentially through the substrate 10. With the large difference in diffusivity of boron and arsenic, for example, boron is approximately 2X10-"Cm2/
sec, and arsenic has a diffusivity of lX1 at 1000°C.
0- ''' with a diffusivity of c1/sec, the P-N junctions are connected to a mask photoform 1 which defines a charge storage region with respect to each other.
Formed substantially below the edges of the heresist layer.

Figures 5A, 5B and 5C illustrate this point. These drawings are cross-sectional views taken along line CC in FIG. 4. FIG. 5A shows a substrate mask with a capacitor mask of Photo-Dis 1-Material 49 over a thin oxide layer 52 to define the charge storage region of each Z+-C memory cell. Using the same design dimensions as in conventional processes, each aperture defined by mask layer 49 is of width W and separates adjacent charge storage regions by Is.

Boron and arsenic ions are implanted through each aperture. Figure 5B shows the stages of the process. Two preliminary dopant regions 53A and 54A are shown as separate layers, and the implant energies of the two impurities may be set to mix the boron and arsenic impurities.

Photoresist layer 49 is retained as a mask and exposed portions of thin oxide layer 52 are removed over the charge storage regions. Photoresist layer 49 is then removed and another oxidation step is performed to re-grow capacitor oxide 58 and thicken oxide layer 51 between the charge storage regions. Figure 5C shows this structure, which also covers polysilicon field plates l! to complete each capacitor structure. It has 147.

Figure 5C further shows that after the drive-in step, the boron of the P-type dopane 1- diffused much more extensively than the N-type arsenic. The diffused boron layer 54 has expanded greatly from the initially implanted layer 54A. In contrast, the diffused arsenic layer 53 remains relatively stationary.

Thus, boron diffuses before arsenic to effectively isolate N+ layer 53 from adjacent charge storage regions.

A PN junction formed by a layer of arsenic 53 and a layer of boron 54 at the surface of substrate 10 lies substantially below the periphery of the capacitor mask aperture.

Note that in the process described above, photoresist 21-layers 49 are left over the regions of substrate 10 that separate the capacitors, in contrast to conventional processes. Excess removal of photoresist material beyond that defined by the photomask is advantageous for the novel process described above. At the same high lithography speed of 2 micron resolution, the photolithographic layer 49 used to separate the charge storage area by 1.5 to 2 microns actually increases the capacitor area. changes up to.

Furthermore, the separation method of the present invention does not use any nitride layer and avoids nitride undercutting in conventional processes.

Finally, no capacitor oxide ingress occurs either, due to the lack of thickness of the oxide region 51 compared to conventional processes and structures. Capacitor oxide layer 58 is still thinner in these peripheral regions, so that a capacitor of width W is formed. No compensation is required by widening the capacitor to maintain the capacitance of each memory cell.

Further investigation of differential diffusion reveals that a portion of the photoresist 1-mask layer 49 used to define the two adjacent charge storage regions shown above and an implant near the surface of the substrate after diffusion. The corresponding lateral dopant profiles for boron and arsenic are shown. However, it should be noted that the dopant profiles are drawn to show how separation of the charge storage regions is achieved, and not to show exact doping profiles. I want to be noticed. The exact doping profile may be calculated from the well-known misfunctioning lateral diffusion structure of dopants from the mask edges of the semiconductor substrate.

Prior to diffusion, all of the implanted dopants remain in regions of the substrate not covered by layer 49, ie, charge storage regions. During diffusion, the more mobile boron moves laterally into the region between the two charge storage regions compared to the arsenic dopant. the two doping contours intersect below and are substantially aligned with the edges of the layer 49, -
Figure 3 shows a switch in overall concentration from a universal type of dopant to an other polar type of dopant, ie, a P-N junction.

The regions of the surface of the substrate between the charge storage regions and the regions near the surface are thus P-doped, and the charge storage regions are N-doped.

The exact placement of the junction is dependent on processing variations and is not exactly under the edge of layer 49, so the junction can be moved from the edge of nitride layer 29 defining the charge storage region to the capacitor by conventional processes. It remains closer to the photoresist edge than the edge of the field oxide that goes into the oxide.

The resulting capacitor isolation structure consists of two backside n+ p+ diodes with an overlying grounded capacitor field plate separated from the diodes by a relatively thin oxide layer. This isolation structure may be thought of as a MOS transistor with the field plate as the gate. As in conventional MOS transistors, the new isolation structure exhibits a threshold voltage defined by the field plate voltage, above which the capacitor current flows for a given capacitor bias, e.g. . For the device discussed here, the threshold m? 11
The pressure is in the range of 1.5 to 2.0 volts. Therefore, in new isolation structures, the field plate needs to be grounded to isolate each capacitor from each other.

Similarly, in a conventional MOSFE''r, the threshold voltage is the channel, i.e., P in the region between the charge storage regions.
It increases as the amount of type dopant is increased. Therefore, a higher threshold voltage isolation structure can be obtained by implanting a large amount of P+ dopant into region 54A of FIG. 5B.

This also causes an increase in the depletion capacitance portion of the storage capacitance. However, for larger P+ dopant concentrations, the N''-P+ diode avalanche breakdown voltage is reduced. With typical design margins, e.g., 7 volts maximum supply voltage and -4V maximum substrate reverse bias. For a working memory chip, N+-P+'j ear F-do G, t7V+4
V, or must withstand 11 volts. The structure with the particular dopant concentration described herein is optimized to use the highest P'' implant dose and to have an avalanche break-town voltage greater than 11 volts.

Alternatives to implanted dopants of approximately equal diffusivity are also available. For example, once the capacitor mask is formed by photoresist layer 49, boron can be implanted into the charge storage regions as described above. A diffusion, or drive-in step, is performed such that the lateral doping profile of boron is similar to that in FIG.

Next, an N-type dopant such as phosphorus, which has approximately the same diffusivity as boron, is diffused through the same aperture. A diffusion step for the phosphorus is also performed, but the boron, which has already been diffused laterally into the areas between the charge storage regions, is
Effectively, the N4 layer 53 of each capacitor is separated.

Yet another embodiment of the invention, which takes advantage of the new separation method, consists of injecting only the N+ dont through the mask aperture illustrated by line 43 in FIG. A P+ dopant, such as boron, is implanted using an additional mask that creates an aperture with the same contour as the field plate depicted by dashed line 46.

Basically, this mask allows P+ dopanes 42-1 to be introduced into the region between the charge storage region and the charge storage gA region, but this mask blocks the dopants from other regions. This embodiment does not rely on lateral diffusion of the P4 dopant into the intercapacitor regions, as the boron is intentionally implanted into the separation regions between the charge storage regions at the expense of an additional mask step. do not have. This isolation structure has the advantage of charge storage of the isolation method, since the amount of boron in the isolation region is so high that both P and N type Doban 1 are implanted through the same mask and gives excellent isolation properties. . As explained earlier, a higher boron concentration results in a larger threshold voltage for the N"P"-N"MO3FFF formed by adjacent the N+ region and the capacitor field play 1. .

These alternative embodiments reduce the area 5 of the gate oxide layer so as to avoid the incorporation of field oxide into the capacitor oxide area, a drawback of conventional processes.
8, the characteristics of the region 51 of the relatively thin acid-1 arsenic layer are retained. In general, other advantages of the invention described above are still applicable to these embodiments.

Therefore, while this invention has been particularly shown and described with reference to preferred embodiments, it will be appreciated by those skilled in the art that modifications in form and detail may be made without departing from the spirit of the invention. It will be. Hence,
It is intended that the invention be limited only by the scope of the claims appended hereto.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a ++-C memory cell. FIG. 2A is a diagram of the physical layout of a t-+i-CmeC memory cell on a semiconductor structure. FIG. 2B is a cross-sectional view of the memory cell of FIG. 2A taken along line A--A. 3A, 3B, and 3C are cross-sectional views taken along line B-8 of FIG. 2A, and are conventional process steps used to fabricate a ++-C capacitor device. FIG. 4 shows an Hl-C memory cell according to the invention. 5A, 5B, and 5C illustrate the manufacturing process according to the present invention, and are cross-sectional views taken along line CC in FIG. 4. FIG. 6 shows the concentrations of two implanted dopants with respect to the mask layer and shows how charge storage regions are defined in the semiconductor substrate according to the invention. In the figure, 10 is the substrate, 11 is the bit line, 31 is the field oxide, 45 is the source/drain mask, 49 is the photoresist, 47 is the capacitor field plate, and 44 is the transistor group 1-! The i-pole, 52, represents an oxide layer. Patent Applicant: Advanced Micro F-Evices Incoho 45- rfl document of drawings (no change in content) F/Cr, 2A FacT, 2B F/(,, Z, C ” FIQ, 4 lqC Procedural amendment (method) December 1987 Co/Japan Patent Application No. 198798 2 Title of the invention Method for manufacturing a charge storage region of a semiconductor substrate 3 Relationship to the case of the person making the amendment Patent applicant address California, United States of America State, Sanii Bail P.O. Box 453, Thompson Brace, 901 Name: Advanced Micro Devices, Inc. Representative: Staifen Zelencik 4, Agent Address: Yachiyo, 2-3-9 Tenjinbashi, Kita-ku, Osaka 1st Building voluntary correction 6, drawing subject to correction 7, and drawing drawn in dark ink with correction content will be supplemented as shown in the attached sheet. There are no changes to the content. Above 2-

Claims (1)

[Scope of Claims] (1) A method for manufacturing a charge storage region of a semiconductor substrate, comprising: forming an insulating layer on the substrate; forming a mask layer covering the insulating layer; and forming a mask layer on the mask layer. at least 1
forming an aperture at least partially defining a charge storage region of the semiconductor substrate; implanting ions of a dopant of a first polarity through the aperture for diffusion through the substrate; ,
and implanting a dopant of a second polarity through the aperture to diffuse through the substrate to a lesser extent than dopant diffusion of the first polarity, thereby increasing the diffusion of the dopant of the second polarity. A method of manufacturing a charge storage region, wherein diffusion of a dopant of a first polarity forms a substantially aligned P-N junction under an edge of an aperture in the mask layer to define a periphery of the charge storage region. 2. The method of claim 1, wherein said first polar dopant 1 has a greater diffusivity than said second polar ion. (3) The first polarity dopant 1~ has a diffusion rate approximately equal to the diffusion rate for the second polarity dopant 1-,
2. The method of claim 1, wherein the first polarity dopant is diffused before the second polarity dopant is implanted. (4) A method for fabricating a silicon substrate 1-rate charge storage region for a memory cell, comprising: forming a first silicon dioxide layer on the substrate; forming a photoresist layer for a mask, forming at least one aperture in the mask layer at least partially defining the charge storage region of the substrate i, through which a dopant of a first polarity is exposed; implanting ions, the first polarity dopant having a predetermined diffusion rate into the substrate, and implanting ions of a second polarity dopant through the aperture, the second polarity dopant having a predetermined diffusion rate into the substrate; a predetermined diffusivity of the substrate that is less than a diffusivity for a dopant of the substrate such that diffusion of the first polarity dopant with respect to the second polarity dopant defines a periphery of the charge storage region. A method of forming a P-N junction substantially aligned with an edge of a mask layer. (5) The method according to claim 4, wherein the first polar dopant 1- contains boron and the second polar dopant contains arsenic. (6) the first portion exposed by the aperture;
removing at least a portion of the silicon dioxide layer and the mask layer, forming a second silicon dioxide layer on the substrate, and forming a poly91112 layer on the second silicon dioxide layer, thereby 6. The method of claim 5, wherein the second silicon dioxide layer, the polysilicon layer and the charge storage region are high capacitance capacitors. (7) A method of manufacturing a highly integrated capacitive device, comprising: forming a first insulating layer over a semiconductor substrate; forming a mask layer on the first insulating layer; forming a plurality of apertures, each aperture exposing a portion of the first insulating layer, implanting ions of a first polarity dopant through the aperture to a predetermined concentration in the substrate; The first polar dopant 1~ has a predetermined diffusivity in the substrate, and the ions A of the second polarity dopant 1~ are injected into the substrate through the aperture to a predetermined concentration. The bipolar dopant has a predetermined diffusivity in the substrate that is less than the diffusivity for the first polar ions, such that the diffusion and concentration of the first polarity dopant is charge related to the diffusion and concentration of the second polarity dopant. I”- substantially aligned with the edges of the openings in each mask layer to define the periphery of the storage region;
forming an N-junction; removing at least the exposed portions of the mask layer and the first insulating layer; forming a second insulating layer over the substrate; and forming a conductive layer over the second insulating layer. forming a charge storage region therein, wherein each charge storage region, said second insulating layer and said conductive layer form a capacitor element. (8) The method according to claim 7, wherein the first polar dopant 1 to and the second polar dopant each contain boron and arsenic. (9) The step of removing the mask H and at least the exposed portion of the first insulating layer further comprises: removing the exposed portion of the first insulating layer and then removing the mask layer; 9. The method of claim 8, including the step of forming said second insulating layer in part by an unremoved portion of said first insulating layer. (10) The first insulating layer covers the substrate by 10
and the second insulating layer is formed by oxidizing the substrate and the unremoved portions of the first insulating layer, thereby forming the charge storage region. the thickness of the second insulating layer covering the first insulating layer is in the range of 300 to 500 angstroms;
10. The method of claim 9, wherein the thickness of the second insulating layer, including the portion of the insulating layer that is not removed, is in the range of 450 to 650 Angstroms. (11) The step of removing at least the exposed portions of the mask layer and the first insulating layer further includes removing the first two mask layers, completely removing the first insulating layer, and removing the charges by twisting. 9. The method of claim 8, including the step of providing a uniform thickness of the second insulating layer covering the storage region and the region between the charge regions. (12) A method for manufacturing a highly integrated capacitor device, comprising: forming a first insulating layer on a semiconductor substrate; forming a mask layer covering the first insulating layer; a plurality of apertures are formed in close proximity to each other in a masking layer, each aperture exposing a portion of the insulating layer, and directing ions of a first polarity dopant through the aperture V- to a predetermined portion of the substrate. implanting the first polarity dopant to a concentration, the first polarity dopant having a predetermined diffusion rate of the substray i~, diffusing the first polarity dopant through the substray 1-, and introducing ions of a second polarity dopant into the aperture. to a predetermined concentration via the second polarity dopant, the second polarity dopant having a predetermined diffusivity approximately equal to the diffusion coefficient of the first polarity dopant i~, such that the second polarity dopant i~ has a predetermined diffusivity approximately equal to that of the first polarity dopant i~; - the concentration and diffusion of said first polarity dopant are substantially aligned with the edges of the apertures of each mask layer to define the perimeter of the charge storage region with respect to the perimeter of adjacent charge storage regions; “)−
forming an N-junction, removing the exposed portion of the insulating layer, removing the mask layer, forming a second insulating layer over the substrate, and forming a conductive layer over the second insulating layer. wherein each charge storage region, the second insulating layer and the conductive layer thereon form a capacitive device. (13) Semiconductor substray 1~ contains silicon,
The first and second insulating layers include silicon dioxide,
13. The method of claim 12, and wherein the N-conducting layer comprises polysilicon. (14) The method of claim 13, wherein the first polarity dopant and the second polarity dopant each include boron and phosphorus. (15) The first insulating layer includes the nubs 1 to 1 to
is formed by oxidizing the substrate to a thickness in the range of 100 to 300 angstroms, and the second insulating layer oxidizes the unremoved portions of the substrate and the first insulating layer, thereby covering the charge storage region. The thickness of the second insulating layer is in the range of 300 to 500 angstroms, and the thickness of the second insulating layer including the unremoved portion of the first insulating layer is in the range of 450 to 65 angstroms.
15. The method of claim 14, wherein the method is formed by forming a 0 angstrom range. (16) A method for manufacturing a highly integrated device, comprising: forming a first insulating layer covering a semiconductor substrate; and forming a first insulating layer on the first insulating layer. forming a mask layer and forming an aperture in the first mask layer, the aperture defining a first region over the substrate, and directing ions of a dopant of a first polarity through the aperture onto the substrate; implanting to a predetermined concentration; removing the first mask layer; forming a second mask layer on the first insulation layer;
forming a plurality of apertures in the mask layer, each aperture disposed substantially over the first region and exposing a portion of the first insulating layer; and a second polarity dopant being applied through the aperture. of each second polarity dopant to a predetermined concentration of the substrate, such that a concentration of the second polarity dopant 10- with respect to the concentration of the first polarity dopant defines a periphery of a charge storage region.
forming a P-N junction substantially aligned with an edge of an aperture of a mask layer; removing at least the exposed portions of the second master and the first insulating layer; forming a second insulating layer over the second insulating layer; forming a conductive layer over the second insulating layer; each charge storage region, the second insulating layer and the conductive NW# overlying the second insulating layer forming a capacitor device; <17) The first polar Doban] contains boron,
17. The method of claim 16, wherein the second polar dopant comprises arsenic. (18) The step of removing at least the exposed portions of the second mask N and the first insulating layer further comprises: removing the exposed portions of the first insulating layer, and then removing the exposed portions of the second mask N and the first insulating layer. 18. The method of claim 17, further comprising the step of removing, whereby the second insulating layer is partially formed by unremoved portions of the first insulating layer. (19) the first insulating layer is formed by oxidizing the above Nobbs 1-rate to a thickness in the range of 100 to 300:4 ng 1-Rohm;
an insulating layer is formed by oxidizing portions of the substrate and the first insulating layer that are not removed;
Therefore, the thickness of the second insulating layer covering the charge storage region is in the range of 300 to 500 Å, and the thickness of the second insulating layer including the portion of the first insulating layer that is not removed is 450 Å. 19. The method of claim 18, in the range -650 angstroms. (20) Said second? The step of removing at least the exposed portions of the masking layer and the insulating layer further includes removing the second masking layer and completely removing the first insulating layer, thereby removing the charge storage region and the charge storage region. said second covering the area between
18. The method of claim 17, further comprising the step of providing a uniform thickness of the insulating layer. (21) A semiconductor device structure that supports a plurality of capacitive Bits, comprising a plurality of regions having a 1-1 band of a first polarity,
The region is provided on the surface of the semiconductor susceptor tray and includes a plurality of regions extending on the surface thereof and containing a second ai dopant; The region is roughly divided to form a P-N junction at the boundary between the first and second polar dopant regions to electrically isolate the first polar dopant region. 1st
further comprising an insulating layer disposed between the polar dopant regions and covering the first and second polar dopant regions;
The thickness of the insulating layer covering the second polarity dopant region is 1000 angstroms or more and 1τ, and further comprising an S conductive layer covering the insulating layer, thereby forming the conductive layer and the first polarity dopant region. 13--A semiconductor device structure, wherein a portion of the insulating layer overlying the conductive region and the first polarizing region forms the permissive device. (22) The thickness of the insulating layer covering the first polar dopant region is in the range of 300 to 500 Angs 1 to 1-Rohm, and the thickness of the insulating layer covering the second polar dopant region is 450- Device M4 construction according to claim 4, in the range of 650 Angstroms. (23) The concentration OJ of the first polarity doban 1- and the concentration of the second polarity doban l- are such that when the conductive layer is held at ground, adjacent capacitor devices are electrically isolated from each other. 23. The device structure of claim 22, wherein the avalanche breakdown voltage of the P-N junction between the first and second polarity dopant regions is selected to be greater than 11 volts.