JPS598085B2 - Antenna input circuit of high frequency amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an antenna input circuit of a high frequency amplifier circuit which is combined with a signal source having capacitive impedance to have high gain and good AGC characteristics. The present invention relates to an antenna input circuit suitable for a tuning device that can perform tuning.

In general, when a Rondo antenna is used, such as in a car medium-wave radio receiver, and the connection to the receiver is made with a coaxial cable, the length of the antenna is short compared to the wavelength of the incoming radio waves, so the Rondo antenna is Since the antenna equivalently has capacitive impedance and the coaxial cable also exhibits a fairly large capacitive impedance, various practical problems have arisen.

In addition, the JIS standard stipulates the equivalent circuit of an antenna circuit for use in automobile medium wave radio receivers as shown in Figure 1, and it is used as a pseudo antenna in the output circuit of a standard signal generator (50Ω). I have decided to do so.

This is due to the capacitive impedance Z1 due to the antenna and the capacitive impedance Z2 due to the coaxial cable.The signal line has a capacitive impedance of 80 pF when viewed from the side, and when actually installed in a vehicle, the capacitance value varies, and the input The tuning of the circuit was often incomplete.

In addition, since the signal source has a large capacitance such as 80 pF, the receiver uses a tuning device using a variable inductance, which is heavy and expensive, but due to the above reasons, the adjustment of the antenna tuning circuit is difficult. There was a problem that sensitivity decreased due to completeness.

Furthermore, attempts have been made to detune the input circuit to improve sensitivity, but as the sensitivity improves, the characteristics at the time of large signal input deteriorate, and the output voltage at the time of large signal increases due to input distortion. Problems such as rise in voltage and distortion in the output voltage were occurring.

The present invention eliminates the above-mentioned drawbacks, and provides an antenna input circuit for a high frequency amplifier circuit which has input detuning to improve sensitivity and at the same time improve AGC characteristics.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An antenna input circuit of a high frequency amplifier circuit according to the present invention will be described below with reference to drawings of embodiments.

FIG. 2 shows an example of the configuration of the antenna input circuit of the high frequency amplification circuit of the present invention. In FIG. FET) etc. are used.

An input terminal 2 to which a signal voltage induced in an antenna (not shown) is applied is connected to an input electrode (gate) of the FETI, and one end of a coil 3 is connected thereto.

The other end of the coil 3 is directly connected to the base of a transistor 50, and the emitter of this transistor 5 is connected to a reference voltage point 14.

Further, the source of the FET 1 is also connected to the reference voltage point 14 via a source resistor 15 set so that an appropriate bias current flows.

The source resistor 15 is a relatively low resistance of about several tens of ohms in order to stabilize the operation of the FET 1 through appropriate self-biasing and to simplify the circuit, as will be described later.

Also, select the coil 3 whose Q is not very high.
Due to the capacitive impedance of the antenna connected to the input terminal 2, it resonates at a frequency lower than the lower end of the reception frequency band.

For example, the Q of the above coil 2 is 500KH in medium wave band etc.
Any material that resonates at a frequency of approximately z may be used.

A connection point 4 between the coil 3 and the base of the transistor 5 is connected to an AGC voltage generation circuit (not shown) via a high resistance 9, and a bias voltage and an AGC voltage are applied to the FET 1.

7 is a bias circuit that defines the start level of the AGC operation, as will be described later.

This is connected between the source of the FET 1 and the ground via a source resistor 15, but it is desirable to stabilize the DC voltage at the reference voltage point 14 so that it does not change due to the drain current of the FET 1.

Further, the bias circuit 7 may be omitted when a sufficiently large reverse voltage can be obtained for the AGC voltage, and the reference voltage point may be operated with the same potential as the ground.

8 is a bypass capacitor of the bias circuit 7,
It is connected in parallel with the bias circuit 7 mentioned above.

An operating voltage of 10 B is applied to the bias circuit I via a resistor 16 to determine a reference voltage.

The emitter of the transistor 6 and a capacitor 12 are further connected to the reference voltage point 14, the other end of the capacitor 12 is connected to the base of the transistor 6, and the base of the transistor 60 is directly connected to the collector of the transistor 5 described above.

The collector of transistor 6 is connected to the input electrode of active element 10 via capacitor 19.

The collector current of the transistor 5 and the base bias voltage of the transistor 60 are supplied from the power supply 10B to which one end of the resistor 13 is connected, and the capacitor 10 determines the charging/discharging time constant of the voltage change at this point.
The other end of the transistor 5 is directly connected to the base of the transistor 5.

A tuning element 17 tuned to the input signal and a tuning coil 18 are connected to the drain of the FET 1 to form a resonant circuit, and the signal amplified by the secondary winding of the coil 18 is transmitted to the next stage amplifier circuit. .

The other end of the resonant circuit is connected to an operating voltage of 10B,
A drain current is supplied through the coil 18.

Here, the tuning element 17 is a variable capacitance element, but it is clear that a configuration using a voltage variable capacitance diode may also be used.

Next, the operation of the antenna input circuit of the high frequency amplifier circuit configured as described above will be explained.

The signal voltage induced in the antenna passes through an antenna equivalent circuit with capacitive impedance as shown in FIG. 1 and is applied to an input terminal 2 of a receiver (not shown).

Here, if the signal voltage arriving at the input terminal 2 is small, no AGC voltage is generated, and the forward bias voltage is set between the base and emitter of the transistor 50 so that the collector and emitter are completely turned on. I'll keep it.

In this state, the voltage between the base and emitter of the transistor 60 is Ov, so the collector impedance is high, and the collector side of the transistor 6 of the capacitor 19 is in an open state.

In this configuration, the coil 3 is connected in parallel with the capacitance z2 of the coaxial cable of the antenna, and the capacitive impedance Z2 of the coaxial cable can be equivalently reduced.

Therefore, the input voltage of the FET 1, which is an active element connected to the input terminal 2, can be increased.

If the coil 3 is dropped, the voltage will be divided by the capacitive impedances Z1 and Z2 as shown in Figure 1, and the voltage will be approximately 3A (-14
dB) reaches the active element 1.

The voltage division effect of Z1 and z2 is also affected by the impedance characteristics of the receiver input circuit, and the lower the signal frequency, the thicker the
There is a tendency for the reception sensitivity of the reception band to decrease.

In order to eliminate the above phenomenon, the coil 3 contributes to supplying the DC bias of the FETI, and the coil 3 is selected to have a value that has resonance characteristics at about 500 KHz with the antenna capacitive impedances z1, Z2, etc. Loss can be reduced.

On the other hand, when the signal voltage arriving at the input terminal 2 becomes large, a third
It is possible to generate an AGC voltage as shown by the curve 20 in the figure, and when this is applied to one end of the AGC resistor 9, it has the effect of reducing the drain current of the FETI as the AGC voltage decreases, thereby reducing the gain.

However, if the gain attenuation of the high-frequency amplification stage of the receiver is started when the input signal level is low, the S/N characteristics of the receiver will deteriorate. It is better to set it to .

In other words, it is a delayed AGC. In the above circuit configuration, A
The delay AGC described above is realized using transistors 5 and 6 as a GC circuit, and its operation will be sequentially explained next.

The AGC voltage shown by curve 20 in FIG.
becomes the gate bias voltage of FET1, but at the same time becomes the base current of transistor 50, the voltage at connection point 4 stabilizes at a voltage higher than the voltage at reference voltage point 14 by the contact potential of transistor 5, which is 0.7v, and this becomes the gate bias voltage of FET1. This becomes the gate bias voltage (curve 21 in FIG. 3).

Therefore, the drain current of FET 1 continues to remain constant at the value set by source resistor 15.

From this state, the input signal further increases, and the AGC voltage 20
is the reference voltage 14 and the contact potential 0. When the voltage starts to drop below the voltage value of 7 V, the gate bias voltage of FET1 also starts to drop and the drain current decreases.
decrease the amplification gain.

If the input level at which this gain reduction starts is selected to be about 80 dB, the input voltage vs. output voltage characteristic will be as shown by curve 30 in Figure 4.
As shown in the figure, it is possible to withstand input signal levels up to about 115 dB.

The above effect is a delay AGC operation using the diode characteristics between the base and emitter of the transistor 50.

Here, the above source resistor 15 will be explained.

This source resistor 15 functions to lower the gate bias voltage slightly below the gate-source saturation voltage by self-biasing.

For example, when the FET 1 is of the jump cushion type and a bias of 0.7 V is applied between the gate and the source, the voltage between the gate and the source reaches a saturation value and the operation of the FET 1 becomes extremely unstable.

Here, if the source resistance 15 is 40Ω and the source current is 5 mA, the gate bias voltage is lowered by 0.2 V from the saturation value due to self-biasing, and the operation is stabilized.

Furthermore, since this source resistance 15 has a low value, it functions as a negative feedback circuit for AC signals, but the gain does not substantially change.

If the value of the source resistance 15 is large, the gain in amplification of the FET 1 will decrease, so a bypass capacitor may be added to prevent this.

By making the value of the source resistor 15 relatively small as in this embodiment, the FET 1 can be operated stably by self-biasing, and the circuit can be simplified.

Next, to further improve the AGC effect, transistor 6
The operation of the circuit constructed by adding the following will now be described.

As mentioned above, while the base current of the transistor 50 is flowing, the voltage of the collector connected to 10B through the load resistor (relatively high resistance) 13 is in the ON state, so it is approximately equal to the reference voltage 14. Therefore, the base current of transistor 60 does not flow.

The input signal increases to about 80 dB, and at the same time the current in transistor 5 stops flowing, the collector voltage rises and the base current of transistor 6 starts to flow.

The change in base voltage with respect to the input signal level is shown by curve 22 in FIG. 3. When transistor 6 enters the ON region, the impedance between collector and emitter becomes low, and one end of capacitor 19 connected to the gate of FET 1 becomes low impedance. becomes grounded in an alternating current manner, and the input signal to FET1 is attenuated.

In this way, while the attenuation effect of the transistor 6 is occurring, the change in the AGC voltage is kept constant, and the level at which the gate voltage of the FET 1 starts decreasing can be further delayed.

The flat characteristic in the region greater than 80 dB in FIG. 3 shows this.

By configuring a delayed AGC using transistors 5 and 6 in this way, the large signal input characteristics can be dramatically improved, and its A
The GC characteristics are 1 3 3 as shown in curve 31 in Figure 4.
Can withstand up to dB input signals.

In the configuration example shown in FIG. 2, capacitor 10 is a capacitor that determines the response time constant of the AGC circuit, and capacitor 1
2 is a bypass capacitor.

Normally, in an AM receiving circuit, the AGC voltage is formed from the average DC voltage of the detection output stage, etc.
When the voltage is not sufficiently converted to direct current, that is, when AM modulation components remain, the gain of the antenna input circuit may fluctuate and abnormal operations such as oscillation may occur.

The capacitor 10 is intended to prevent this abnormal operation.

When the capacitor 10 is discharged, the AG applied to the connection point 4
The AM modulation component remaining in the C voltage is amplified by the transistor 5, and the transistor 6 is repeatedly turned on and off, which is different from the predetermined operation and is extremely inconvenient.

The capacitor 10 is configured so that the transistor 6 does not respond due to negative feedback to high frequency fluctuations such as the AM modulation component.
The transistor 6 is configured to operate only in response to slow changes such as changes in voltage.

Since the operation of the transistor 6 causes attenuation of more than 10 dB, it is important to prevent malfunctions due to residual AM modulation components.
This has a very large effect on stabilizing the operation of the GC loop.

Note that the bias circuit 7 may be simply one resistor, but as the AGC voltage decreases, the drain current decreases and the source voltage also decreases, finally reaching zero. This may complicate the AGC circuit.

Therefore, if a varistor diode or the like is used for stabilization, the above problem can be eliminated and the AGC effect can be increased.

As mentioned above, it is possible to de-tune the input circuit in a high-frequency amplifier circuit to avoid the effect of input capacitance on the sensitivity, and also to compensate for the characteristics for large signal input, and to It is now possible to use
It can greatly contribute to cost reduction, downsizing, and weight reduction.

Although we have explained here an example of an untuned input circuit using F'ET for a medium wave radio receiver for automobiles, the same effect can be obtained in a high frequency amplification circuit using an emitter follower type transistor. Needless to say.

As is clear from the above explanation, the high frequency amplifier circuit of the present invention uses the non-tuned input method to equivalently reduce the capacitance of the capacitive antenna to obtain high gain, and also provides extremely good performance by applying a large delay AGC. It can realize AGσ characteristics, prevent large signal input distortion, and withstand up to large signal input levels.

In addition, since a non-tunable input circuit can be realized, variable capacitance tuning, which was previously thought to be impossible, is now possible, and electronic tuning can be achieved, as well as being able to significantly reduce size, weight, and cost. It has characteristics.

[Brief explanation of the drawing]

Fig. 1 is a pseudo antenna circuit diagram of a general medium wave radio receiver for automobiles, Fig. 2 is a circuit connection diagram of an antenna input circuit of a high frequency amplification circuit showing an embodiment of the present invention, Figs.
The figure is a diagram of its characteristic curve. 1... Active element, 2... Input terminal, 3
... Coil, 5 ... AGC transistor, 6 ... Attenuator transistor, 7 ... "
... Voltage stabilizing element, 8 ... Bypass capacitor, 9 ... AGC resistance, 10 ... Capacitor, 12 ... Bypass capacitor, 13 ...
...Load resistance, 14...Reference voltage point, 15
...Source resistance, 16...Bias resistance, 17...Tuning capacitance/amount, 18...Tuning coil, 19...For attenuator capacitor.

Claims (1)

[Claims] 1. An active element having a high voltage impedance, a human electrode connected to an antenna input terminal, a common electrode connected to a reference voltage point via a low resistance for self-biasing to ensure stable operation, and the above active element. An AGC transistor whose base and emitter are connected in cascade through a coil between the input electrode of the active element and the reference voltage point, and a collector-emitter connected in cascade through a capacitor between the input electrode of the active element and the reference voltage point. the collector of the AGC transistor and the base of the attenuator transistor are directly connected to apply a bias voltage through a resistor; A bias and AGC voltage generation circuit for the input electrode of the active element is connected to the connection point via a high resistance, and a switching time constant is determined to slow down the response speed of the attenuator transistor to stabilize the operation. An antenna input circuit for a high frequency amplifier circuit, characterized in that a delay AGC is configured such that a capacitor is inserted between the base and collector of the AGC transistor to start gain attenuation from an arbitrary input level.