JPS5980036A - Fault detector of multiplex transmission control system - Google Patents

Abstract

PURPOSE:To improve the reliability of a titled system, by checking both main and secondary clock pulses of a multiplex transmission system to detect a system fault due to a trouble of a controller and generate an alarm, etc. CONSTITUTION:Plural repeaters 3 are connected to a cable 2 connected to a receiver 1, and a terminal device group 4 including a smoke sensor, a smoke ventilator, etc. is connected to each relay 3. A fault detector 5. This detector 5 contains three signal insulating/extracting circuits 6 consisting of resistances R1 and R2, a diode D1, a capacitor C1 and a photocoupler PC1, respectively. Then main and secondary clock pulses and a data pulse are extracted out of main clock, secondary clock and data pulse lines, respectively. Then these three pulses are checked to detect a fault of a multiplex transmission system due to a trouble of a transmission controller. Thus the system reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality detection device for a multiplex transmission control system.

FIG. 1 shows a block diagram of a conventional automatic fire alarm system using a multiple transmission control method. This automatic fire alarm system connects a plurality of repeaters 3 to a cable 2 pulled out from a receiver 1, and each of the plurality of repeaters 3 has a smoke detector,
Terminal equipment 4 such as a smoke prevention device is connected. cable 2
is the power line that supplies +12V power from the receiver 1 to the repeater 3, the ground line, and the line shown in Figure 2 (Bl, fAl
The main clock line and sub-clock line that send the main clock pulse CP and sub-clock pulse CP shown in FIG. The main clock pulse CP2 is a reference clock pulse. The sub clock pulse CP
is the data pulse DP at an intermediate timing between the main clock pulse CP and the same period as the main clock pulse CP2.
A group of numbers equal to the number of bits occur repeatedly. The data pulse DP consists of a 16-bit pulse, and the first
~8 bits are repeater address signals, 9th to 16th bits are control signals, and each bit of the data pulse DP is transmitted at the same timing as each of the main clock pulses CP2 that immediately follows each of the group of sub-clock pulses CP. is transmitted, and the return data RD consists of an 8-bit reply signal.
It is transmitted at the same timing as each of the eight immediately following main clock pulses CP2 after the group of wide clock pulses CP2.

In such an automatic fire alarm system, even if the receiver 1 breaks down, there is no means to detect it, and the reliability of the system is low.

Therefore, an object of the present invention is to improve the reliability of a multiplex transmission control system.

As shown in FIG. 3, this invention includes an abnormality detection device 15 and detects system abnormalities due to failures in the main body of the control device by checking the main clock pulse, ivy pulse, sub clock pulse, etc. of the multiplex transmission control system. This will improve the reliability of the system by issuing warnings, etc.

An embodiment of the present invention will be described based on FIGS. 4 to 7. This abnormality detection device 5 includes a resistor R, a diode Dlo, a capacitor C, and a diode Dlo as shown in FIG. 4 (C1).
Signal insulation extraction circuit 6 consisting of engineering and photocoupler PC engineering
By using three main clock lines, sub clock lines and data pulse lines, fBl, fAl,
(The main clock pulse CP2 as shown in C1, the sub clock pulse CP1 and the data pulse DP are respectively taken out in an insulated state from the automatic fire alarm system. i'D2゜Capacitor C2 and photocoupler P
By using the signal insulation extraction circuit 7 consisting of C2, inverted return data f1, which is the inverted return data RD as shown in FIG. 5, is extracted. In this case, the power source E on the light emitting element side of the photocouplers PC1 and PC2 is the same power source as the power source of the automatic fire alarm system.
The power supply r on the light receiving element side of C11PC2 is a separate power supply independent of the power supply of the automatic fire alarm system.

In addition, inverters N□-IN3 are connected to an oscillation circuit 8 consisting of resistors R5, R6 and capacitor C3 as shown in FIG.
By outputting a pulse signal as shown in FIG. This frequency-divided pulse is transferred to a 4-pit shift register S.
It is added to R and SR2 as a clock input.

The voltage and voltage of the power source E/ are respectively applied as data inputs to the shift registers SR□ and SR2 of the cholera.

The shift register SR1 also has a sub clock pulse C.
The inverted sub-clock pulse obtained by inverting P by an inverter N, the main clock pulse CP2, and the shift register SR.
The output Q3 of 2 is applied as the reset manual power R through the 3-man clock gate NO, and the shift register SR2 receives an inverted main clock pulse obtained by inverting the sub clock pulse CP1 and the main clock pulse CP2 by the inverter N5, and the output of the 3-man gate N02. is added as a reset input via the three-way gate N03, and the output Q of the shift register SR is input to the three-way gate N02.
3 is inverted by the inverter IN6 and a low level voltage are applied directly, and the voltage of the power source E' is applied via the switch SW and the resistor.

The output of No. 2 is connected to a relay wipe circuit 10 consisting of a transistor Tr and resistors R8 and R9.
It is designed to control a relay RY connected to a power source E' via a power source E'. D3 is a diode.

In addition, the data pulse DP is generated by the transistor Tr2, the resistor R1o, the R circuit, the R circuit, and the other drive circuit 1.
Control the light emitting element LED through 1 and return data RD,) transistor Tr3 and resistor R.

The output 14 is transmitted via a drive circuit 12 consisting of R and R.
15 Optical element is designed to control ED2.

The operation will be explained in detail below. shift register S
R, SR2 outputs data input in synchronization with clock input C (FIG. 5(F)). -Q3, but the sub clock pulse CP and the main clock pulse C
If P is occurring normally, 3 person Kaa gate NO
As shown in FIG. The output of the shift register SR3 is reset before it becomes , and the output of the shift register SR3 becomes
In order to maintain the rLJ state as shown in Jl and the output of the three-person gate NO2 to maintain the "L" state as shown in Figure 5, the transistor Tr3 of the relay drive circuit 10 is turned off and the relay RY is energized. Therefore, no abnormality display or alarm notification is performed.

In this case, the period of the divided pulse of the frequency divider circuit 9 (is set to 0 or more than 1.6 times the period of the main clock pulse CP, and the last one of the sub clock pulses CP of one group is used to register the shift register. After the SR signal is reset, the shift register SR□ is reset by the first of the sub-clock pulses CP of the next group.
It is ensured that no more than four clock inputs are applied to R.

However, if the sub clock pulse CP always changes to the rLJ state as shown in Figure 6 due to a failure in the central processing unit of receiver 1, the output of the three-man clock gate NO□ will change to the state shown in Figure 6 (Gl). As shown in FIG.
As shown in Fig. 6 (Kl), the output of the human cover gate NO2 becomes rHJ and the transistor Tr□ is turned on, and the relay RY is energized and an abnormality notification is performed. By becoming "H",
The output of the three-tooth Noah gate N03 also constantly changes to "L" as shown in FIG. 6 (Hl), and then the shift register s
After counting 4 pieces of R2, at time t the output Q3 is shown in Figure 6 (Jl
As shown in , it becomes "H", and then the sub clock pulse c
Even if P1 begins to occur, the state is maintained. To release this state, the switch SW should be turned on momentarily to set the output of NO3 to rLJ.

Note that the above operation is mainly performed at the time of O-sock pulse CP27jfK.
The same applies when a failure resulting in HJ occurs.

On the other hand, the sub clock pulse CP□ is
If a fault occurs that causes constant rHJ as shown in Figure 7, the output of the three-man gate NO3 will always be
9, the reset input is no longer applied to the shift register SR2, and after counting 4 clock inputs, the output Q3 of the shift register SR2 is shown in Figure 7 (Jl
As a result, the output of the three-man gate NO□ is always “L” as shown in No. 71m (G).
'', and after the shift register SR counts 4 clock inputs, the output Q3 of the shift register SR always becomes rHJ as shown in Fig. 7 (11), and the output of the three-man gate NO2 becomes as shown in Fig. 7 (■). As shown, rHJ becomes active, transistor Tr2 turns on, relay RY is energized, and abnormality notification is performed.
- Since the signal No. 2 becomes "H", the notification state is maintained in the same manner as above, and to release this, turn on the switch sw.

Nao, the above operation is based on main clock pulse CP2 RrL
The same applies when a failure of J occurs.

Next, when the data pulse DP is normally output as shown in FIG.
As shown in Figure fcl and Figure 7 (C1), when rLJ is constant, transistor Tr2 is always off and the light emitting diode LED1 goes out; conversely, when rHJ is constant, transistor Tr2 is always on and emits light. The diode LED □ lights up brightly.

On the other hand, when the return data RD is output normally as shown in FIG. 5 (DJ), the transistor Tr3 is turned on and off, and the light emitting diode LED2 is dimly lit, as shown in FIG. 6) or FIG. 7). If it is always rHJ like this, the transistor Tr3 is always off and the light emitting diode L is turned off.
When ED2 is turned off and rLJ is always on, the transistor Tr3 is always on and the light emitting diode LED2 is brightly lit.

In this way, this embodiment uses shift registers SR1, S
An abnormality notification signal is output when R2 counts a certain number of frequency-divided pulses, and when normal, the sub clock pulse CP and the main clock /7/<rus CP,
Therefore, until shift registers SR1 and SR3 count a certain number, shift register SR.

Since SR2 is configured to be reset, an abnormality can be notified when either the sub clock pulse CP or the main clock pulse CP2 is no longer output due to a failure in the receiver 1, and the power supply E' Since it is separate from the power supply E of the automatic fire alarm system, there is no power interference from the automatic fire alarm system.
The reliability of automatic fire alarm systems can be improved.

As described above, the abnormality detection device for a multiplex transmission control system of the present invention is an abnormality detection device for a multiplex transmission control system driven by an independent power source different from the driving power source of the multiplex transmission control system, and the abnormality detection device for the multiplex transmission control system a clock extraction circuit that insulates and extracts control pulses transmitted therein; a clock pulse generation circuit that generates abnormality detection clock pulses; and a clock pulse generation circuit that generates abnormality detection clock pulses that are reset by the control clock pulses. A counter that generates an output when a certain number of clock pulses are counted; and an abnormality notification circuit that responds to the output of this counter; Since the period of the abnormality detection clock pulse is set so as to be reset by the normal clock pulse, there is an effect that the reliability of the multiplex transmission control system can be improved.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the automatic fire alarm system, Figure 2C
AL to FD+ are waveform diagrams of each part, FIG. 3 is a block diagram for explaining the invention in detail, and FIG. 4 (At to +D
+ indicates a circuit diagram of an abnormality detection device according to an embodiment of the present invention;
Figure (N ~ (IO is a waveform diagram of each part during normal operation, Figure 6 (A)
~ ■ and Figure 7 (5) ~ (The illusion is a waveform diagram of each part at the time of abnormality. 1... Receiver, 2... Cable, 3... Repeater,
5... Abnormality detection device, 6.7... Signal insulation extraction circuit, 8... Oscillation circuit, 9...'' - Frequency dividing circuit, SR engineering,
SR2...F0 Register, RY...Relay 4 (j, Director General of the License Agency 1. Display of the incident 1982 Patent Application No. 191548 2, Name of the invention Abnormality detection of multiplex transmission control system tj, j !,, IH Ren 3, Relationship with the person making the amendment Applicant Address 1048 Bold Kadoma, Kadoma City, Osaka Name (
583) Denji Matsushita Co., Ltd. Representative Kobayashi
Iku 4, Agent 5, Date of amendment order Month, Showa
Voluntary amendment 6, Specification subject to amendment 7, Contents of amendment

Claims (1)

[Claims] An abnormality detection device for a multiplex transmission control system driven by an independent power source different from the driving power source of the multiplex transmission control system, the clock extraction circuit for insulating and extracting control clock pulses transmitted in the multiplex transmission control system. a clock pulse generation circuit that generates an abnormality detection clock pulse; a counter that is reset by the control clock pulse and generates an output when a certain number of abnormality detection clock pulses have been counted; and an abnormality notification circuit that responds to the output, and the period of the abnormality detection clock pulse is set so that the counter is reset by the control clock pulse before the counter counts a certain number of the abnormality detection clock pulses. Abnormality detection device for the configured multiplex transmission control system.