JPS5979395A - Control circuit for display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] With the dawn of the technological IM field, improved control circuits, especially navigation display power,
This invention relates to an improved program control circuit for controlling the on/off operation of display devices such as dimming lights or foghorns.

BACKGROUND OF THE INVENTION With recent advances in semiconductor technology, navigational indicator flashing lights and night! Considerable improvements have been made in the area of controlling the on and off operation of display devices such as whistles. Due to their small size, semiconductor logic circuits are effective in reducing the overall size and weight required to form individual display equipment units, making them very suitable for the above-mentioned applications. ing. Particularly in the case of navigation indicator flashing lights, the number of equipment units used is large, so this is of great significance. Also, because semiconductor devices consume relatively little power, they can be used in remote locations where only battery power is available to the device unit.

Furthermore, semiconductor logic circuits are generally reliable, which is especially important in remote locations where power supply is difficult.

Advances in semiconductor technology have created a number of devices, particularly for navigational indicators, that utilize programmable control means. For example, US Pat. No. 4,124,842, US Pat. No. 4,029,994, US Pat.
This is the system shown in No. 91, No. 3810150, and No. 3781853. These patents demonstrated the use of only battery energy to provide a desired signal, such as a Morris Code signal. Therefore, it is suitable for remote use.

However, despite this development, there are many problems in this field. In particular, the problem of which unit to program should be selected is unavoidable, and this problem becomes one in which one has to choose between several units, each with its own unique drawbacks. It is.

For example, one currently common programming unit that may be employed in such systems is a programmable read-only memory (FROM). 1. In general, the program to execute the desired blinking sequence (Seq, uence) can be stored in advance as a code, and then an appropriate code language can be selected and the language turned on.
It is utilized in an appropriate address circuit for sending data to a display device that controls off-operation.

For typical examples, FROM is 0MO8 (complementary metal oxide semiconductor),
It is also TTL (Run Sister Transistor Logic). A number of commercial models of each are currently available. However, before making a choice for creating a control system, you must consider the advantages and disadvantages of each.

First, regarding this selection, it should be noted that the number of OMO8-FROMs currently available is smaller than the number of TTL-FROMs. Also, CMOS units are expensive, OMO8-FROMs are sensitive to handling, and are generally less stable than TTL-FROMs. However, 0MO8-FROM has extremely large advantages over TTL-FROM. This means that the power consumption is considerably lower.

TTL-FROM has the disadvantage of relatively high power consumption, which quickly depletes the limited battery energy, which is a major problem in remote navigation displays.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved program control circuit for controlling the on/off operation of a display device, and another object is to provide an improved program control circuit for controlling the on/off operation of a display device. It makes it possible to use the sequence programmable unit [7], but at the same time TTL-FRO.
An improved programmable control circuit is provided for controlling the on/off operation of a display device while minimizing power consumption.

To achieve the above and other objectives, in addition to TTL-FROM, a plurality of low power consumption CMOS units are used to construct a program control circuit. TTL
-FROM has a plurality of memory cells (+ncmory cellp) programmed in a plurality of Comodo languages, and address means using 0MO8 is connected to this FROM, and an address to be addressed to the memory cell is connected to the FROM. utter language. This address operation is to activate the FROM and output the code language in parallel form. This is connected to a parallel-to-serial converter using 0MO8, which receives the code language in parallel form from the FROM and converts it into a serial code output signal. This serial code output signal is used to operate the display.

In order to reduce the power consumption of the entire system, an intermittent power-up circuit is connected to the above-mentioned FROM, and the PRIM performs the addressing operation and the code language is transferred from the FROM to the parallel-series connection. All that is required is to turn on the power 17 to the I'ROM and put it into operation only during the time period necessary for sending the data to the converter.

In FIG. 1, the program control circuit (overall) 10 is as follows:
Display rr! In the following explanation, this display device 12 is assumed to be a DC incandescent lamp with 1.6 lights. However, it may also be a fog horn or a flow control program. FIG. 2 is an example of a detailed layout diagram of FIG. 1. In FIG. 2, all gates are configured with negative outputs (e.g. NAND-NOR).
However, it should be understood that all logic circuits can be constructed by combining logic gates using either affirmative or negative logic. To explain the diagram in detail, the clock signal is clock circuit 1
4 to the 1QIJ control circuit 10. The 4 circuit is then divided by a frequency divider 1G to a frequency appropriate for the operation of the circuit. Therefore, in preparation for this, it is better to be able to output a division ratio of different frequencies.For example, as shown in Fig. 2, if the clock circuit 14 is If a clock vibrometer is used, the divider can be set to a 320 or 180 hertz output, depending on whether it is used around resistor 16A or 16B on the output side of the divider. The power output used depends on the total time required for the entire sequence to be transmitted. Choosing 180 hertz would require a longer time span for the entire sequence.

The output of the frequency divider 16 is T T T, -PROM
Performs addressing work for 20. ↓ ripple counter
) I can't tell. The ripple counter 18 also acts as a basic unit of time for the other elements of the control circuit, and also controls the entire time sequence of flashing lights upon the onset of the reset signal (details to follow). It works to make a new start.

Typical examples include Ripple Counter 18 Zuba, P
Differences between FROM and ROM 20 are: 1. Parallel attribution for specifying the location of the portion; utter a /s language. This calling A
CCESS), FROM outputs a parallel code language.

As an example of TTL-FROM7, one suitable for the present invention is TB manufactured by Teyaza 2-Instrument Co., Ltd.
P24S1n or National Semiconductor's SN-74-287.

Both of these P ROF,i are 256×4 memories, but the invention is not limited thereto.

For example, FROM! The code language that was placed (S T Q RE ) is supposed to be a 4-bit control language representing the number 6'131 (which operates the blinking light and therefore matches the ρ Morris code). It is.

Pidpakun (B
It PATTERN) is used as a reset code for the ripple counter 18, as will be described later.

The parallel code language from PROM 20 is sent to the parallel inputs of parallel-to-serial shift register 22. As mentioned above, this code language is PR from Ripple Counter 18.
Represents a unique hexadecimal number determined by the address sent to OM2Q. As can be seen from Figure 1.2,
Shift register 22 has a serial output 24 and two parallel outputs 26,28. The serial output 24 can be made to specify one of the positions of up to N essential pits of the 4-bit parallel code language that has been sent to the shift register. In the embodiment shown in FIG. 2, the most significant bit is removed and the next most significant bit is used to provide the serial output 24.

The two parallel outputs 26,28 may be the two least significant bits (LSBs) in the input code language. The shift register 22 is connected by a line 30 so as to receive the clock output from the ripple counter 18 (see Figure 2).This allows the conversion of the hexadecimal code from the shift register at intervals of 50 milliseconds. carry out.

The serial output 24 of the shift register 22 is AND (AN
D) Connects to the indicator light 12 from the amplifier circuit 34 via the gate 32 (in FIG. 2, the logical output is obtained by a NAND gate 32A and an inverter 32B). As shown in FIG. 2, the amplification section may be a pair of transistors 34Aslsn. Also shown in FIG. 2, an output run sister 36 controlled by the outputs of amplifying transistors 34A and 34B provides the final control output for the light body 12. In this way, the flashing characteristics of the light body 12 are determined by the series output 24 of the shift register 22. This system can be achieved by appropriately setting the code in FROM2Q. Q? It can be matched to any blinking sequence, not just Morris codes or other codes.

The AND gate 32 (consisting of a NAND 32A and an inverter 32B in FIG. 2) has a shift register 2
In addition to being supplied with the series output 24 of 2, the daylight control circuit 3
A daylight control signal from 8 is provided. The daylight control circuit as shown in FIG.
2 (receiving an input from a photocell 40 and a DC voltage Vcc), a NOR gate 44 whose all inputs are connected to the output side of a NAND gate, and a resistor 46 and a capacitor 48. It consists of a delay circuit.

Daylight control circuit 38 operates as follows:
When the impedance of is high (when the light intensity is low), the positive signal is the gate 32 (combination of 32A and 32A, Fig. 2).
The code signal from the serial output 24 of the shift register 22 activates the output quadrant sister 3G;
Turn on the lamp 12.

On the other hand, during the daytime when the amount of light is high, the impedance of the optical cell 40 is low. The NOR gate 44 will then have a low output, preventing the serial output 24 of the shift register 22 from passing to the output l run register 36. A delay circuit including a resistor 46 and a capacitor 36 prevents any incident temporary lamp light from reaching the gate 32Δ until the serial output 24 of the shift register 22 temporally disappears. At night, the flickering light itself acts to prevent the operation of the light body 12 from being interrupted.

As mentioned above, in addition to the serial output 24, the shift register 2
2 has a pair of parallel output terminals 2628, which means that the parallel output of the other terminals 26.28 from the PROM 20 becomes a 2-bit code, which also outputs the ripple counter 18-\reset signal to the program control circuit. 1191 to other program control circuits connected to 10.
(5YNC) Functions to emit a signal.

This reset means that the temporal sequence of all timing and attribution functions performed by ripple counter 18 begins anew.

To perform this reset and tuning operation, the parallel output terminals 26 and 28, along with the series output 24, are connected to a reset code finder 50, as shown in FIG. The vessels are Noah Gate 50A and Nando's.
59B. The particular circuit in Figure 2 has a unique code word of 01O (i.e.
Set to not detect binary 2). This code language was chosen as a seven-bit code language (the most significant bit of the four-bit code language sent to shift register 22 is omitted to indicate -C). Of course, other code languages and logic gate circuits may be employed for the reset operation, and the circuit shown in FIG. 2 is for illustrative purposes only.

When reset code detector 50 detects the presence of a predetermined reset code, a reset output signal is generated (e.g.,
2, at the output side of NOR gate 50B). This reset output signal is output from the OR gate 52 (this is the NOR gate in Figure 2).
(consisting of a gate 52A and an inverter 52B) and is sent to the reset terminal of the ripple counter 18. In this way, the ripple counter 18 is reset to a predetermined value. A typical example is when reset causes F.
The ROM addresses start at address 0000, and the flashing light 120 time sequence begins exactly the same again.

In addition to commanding the ripple counter 18 to reset
, the reset signal output of the reset code finder 50 is also sent to the tuning terminal 8YNC. In FIG. 2, this may be done through output transistor 54. The advantage of this circuit is that this control circuit 10 notifies other control circuits that control flashing lights in a manner similar to this control circuit 10 that the ripple counter 18 has been reset. It is. Thus, the other control circuits also reset their ripple counters at the same time, so that all lamp flashes scoot together.

At the same time, when a reset detection signal is generated in another control circuit, the tuning terminal 5YNC outputs an uncontrolled circuit +1'3'I O
The ripple counter 18 is reset to -V+ stage. This is accomplished by having a tuning terminal connected to the input of OR gate 52 (comprised of NOR gate 52A and inverter 52B in FIG. 2). Thus, when a reset detection signal from another program control circuit reaches the tuning terminal 5YNC, it is as if the reset signal is detected by the reset code detector 50 of the main control circuit 10.
The reset terminal-1 of the ripple counter 18, OR game 1, 52 in the same manner as if issued by
It can be conveyed through the process. Based on this loquat, this control circuit 10
can both reset other circuits and be reset by other circuits.

In connection with the connection to the power source, the system described so far controls the blinking sequence (or other similar on/off operation) of the light body7, and the system that controls the blinking sequence of the light body (or other similar on/off operation). However, as mentioned in the Background of the Invention section, CMO3 can be used for many elements in this circuit. (For example, clock generator 14, frequency divider 16, ripple counter 18, shift register 2
2) However, as PROM20, T T L
-PRO), 4 is advantageous due to the many advantages of TTL-FROM over cMos-pitoM. However, T T T, -F ROM has the disadvantage of high power consumption. For example, currently commercially available TTL-FRO
M carries a current of approximately 100-150 milliamps.

Therefore, the program control circuit of the present invention includes special means for reducing power consumption, which will be described below.

Returning to FIG. 1, the reduction in power consumption of the present invention is achieved by connecting the power supply terminals of PROM 20 to intermittent energization (powE).
This is achieved by configuring an intermittent energization gate circuit 56 by connecting the output terminals 58 of the one-knot pull counter 18 that generates the Rup) signal. As shown in more detail in FIG. 2, the intermittent energization circuit 56 includes a voltage regulator 60 in communication with a power supply 62 that provides a regulated output voltage; Source 62 is 6 ports or 1
Although the DC output voltage is 2 volts, in either case, a voltage regulator 60 set to stably establish a DC output voltage adjusted to 5 volts may be provided. This regulated output voltage is supplied to an emitter terminal of a control PNP run sister 64 whose collector terminal is connected to the power supply terminal of the FROM. The base terminal of the control transistor 64 is connected to the NAND gate 66 and the inverter 6.
8 to the output terminal 58 of the ripple counter. The other input to NAND gate S6 is tied to the output of NOR gate 52A.

In operation, the output terminal 58 of the ripple counter 18 is normally positive when FROM is supposed to be off. This positive signal is sent to one of the inputs of NAND gate 66.

The other input to NAND gate 66 from NOR gate 52A is normally positive (unless a reset signal is present), so the output of NAND gate 66 is normally negative. This is inverted by inverter 68 and becomes a positive signal to the base terminal of PNP run sister 64, which remains off. Therefore transistor 64
does not transmit the adjusted voltage from voltage regulator 60 to PROM 20.

On the other hand, when the PROM 20 is supposed to be energized, the output of the terminal 58 of the ripple counter 18 becomes negative. This then makes the output of NAND gate 66 positive.

This positive signal is inverted by the inverter 68 and becomes a negative signal to the base terminal of the PNP run sister 64, turning it on (energized state). Thus, the adjustment pressure from voltage regulator 60 is transmitted to I'ROM 20 and energizes it.

Similarly, if a reset signal is asserted, the output of NOR gate 52A will be negative.

This has the same effect of turning on transistor 64. Therefore, if a negative energizing pulse is issued by the ripple counter 18 or a reset pulse is generated by the present control circuit 10 or any other control circuit,
PROM 20 is energized.

I would like to point out the following points here. That is, the operation of energizing the F ROM (which is essentially an OR operation since the FROM is energized if one of the two conditions exists) is performed by the NAND gate 66, Inverter 6
Although described in terms of the operation of the I) N P transistor 64 associated with the negative pulse from the terminal 58 of the counter 18, the same operation can be performed, if desired, by the It can be executed using the positive and negative signals from the OR gate.

Regarding the timing of the negative intermittent energization signal from ripple counter 18, this is sufficient time to allow ripple counter 18 to address FROM and move the code language to shift register 22. However, in the specific example shown in FIG. 2, the frequency divider output is 320 or 180 Hz, 256
Assuming an output clock of 50 milliseconds for RUM, Shift 1/Sister, it has been found that sustaining a negative pulse of 200 microseconds every 0.2 seconds is sufficient to generate a negative intermittent energization signal. Ta.

Therefore, it can be seen that significant power savings can be achieved since the FROM is energized for a small amount of time every 0.2 seconds. This may be understood by the fact that the specific operating conditions shown in FIG. 2 require a current consumption of less than 5 milliamps. Of course, the specific time periods described above are merely exemplary, and the specific timing used for a particular system will depend on the conditions governing the system.

Although the present invention has been described with reference to the preferred embodiment shown in FIG. 2, other changes and modifications may be made in carrying out the claimed invention. For example, the present invention has been described from the perspective of using a ripple counter for address and time designation, and a parallel-to-serial conversion register to control the flashing sequence and reset, but the principles of the present invention have been described. However, those skilled in the art can easily conceive of many different arrangements of circuits and elements without departing from the scope and spirit of the present invention, and these belong to the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a specific example of a program control circuit according to the present invention, and FIG. 2 shows an example of a circuit arrangement for implementing the specific example of FIG. 10...Program control circuit (whole) 12...Display device 14...Clock circuit 16...Frequency divider 18...Ripple counter 20...TTL-FROM 22...Parallel → serial shift register 24 ...Series output 26.28...Parallel output 32...AND gate 34...Amplification circuit 36...Output transistor 38...Daylight control circuit 40...Light cell 42... ... NAND gate 44 ... NOR gate 46 ... Resistor 48 ... Capacitor 50 ... Reset code detector 52 ... OR gate 54 ... Output run Sister 56...Intermittent energization (POWERuP) gate circuit 5
8... Ripple counter output terminal 60... Voltage regulator 62/Power supply source 64... Control PNP transistor agent 3
Masao Taku and 1 other person

Claims (1)

[Scope of Claims] (+) TTI with multiple memory cells programmed with multiple code languages, -FROM: FRO as mentioned above.
Addressing means by 0MO8 that is connected to M and issues an address language for specifying the memory cell address of the FROM, activates the FROM, and outputs a code language in parallel format according to the address language: receives a parallel form of code language from
0MO8 parallel-to-serial conversion means arranged to convert the parallel code language into a serial code output signal; receiving a code output signal from the CMO8 parallel-to-serial conversion means; , output means arranged to actuate the display means; and said FROM only for a period of time necessary to perform an addressing operation and transfer the parallel code language from said FROM to the parallel-to-serial conversion means. A control circuit for a display device, comprising: an intermittent energizing circuit connected to the FROM so as to be energized and energized. (2) The addressing means by 0MO8 is operated by a clock circuit which generates a counting sequence to cause the FROM to perform the addressing operation. (3) The parallel-to-serial conversion means includes a parallel-to-serial soft register. A control circuit according to claim 1, characterized in that: (4) The control circuit according to claim 1, wherein the display device is a light body. (5) The control circuit according to claim 1, wherein the display device is a foghorn. (6) an intermittent energization circuit is disposed between the output of the counter that generates the intermittent power control signal and the energization input terminal of the FROM; : a voltage regulator connected to the DC power supply and generating a regulated DC voltage at its output terminal; and a connecting conduit located between the output terminal of the voltage regulator and the energization input terminal of the PROM; and a control terminal arranged to receive an intermittent energization control signal from said counter, wherein said intermittent energization control signal is transmitted to said PROM through a connection conduit to said PROM's energization terminal. The control circuit according to claim 2, further comprising: switch means for closing the connecting conduit when the output regulated DC voltage is passed. (7) Voltage The regulator is adapted to convert both the 6 volt and 12 volt power sources to a predetermined voltage, and the intermittent energization circuit has a terminal in communication with the DC power source, which power source is either 6 volt or 12 volt. 12 volts, and these 6 volt or 12 volt power supplies (d
7. The control circuit according to claim 6, wherein the program control circuit can operate without any modification. (s) the p a OM is programmed to include a reset code for resetting said counter to a predetermined value, and said reset code includes at least a 2-bit parallel format code language; , and the program control circuit further includes: output terminals of a pair of parallel-to-serial conversion means for outputting a parallel reset code language corresponding to the reset code hit position indicated by the code word in parallel format; When this is sent to the serial conversion means and recognized as a reset code by a pair of parallel output terminals, it is connected to a pair of parallel output terminals that receive the reset code language and generate a reset detection output signal. and a reset feedback conduit connecting between the counter reset terminal and the detection means for providing a reset detection output signal for resetting the counter. A control circuit according to scope 6. 9. The reset feedback conduit includes a tuning terminal leading to at least one other program control circuit for providing commands to the other program control circuit that generated the reset detection output signal. A control circuit according to claim 8. 10 A gate connected to a tuning terminal for receiving commands from another program control circuit that has issued a reset detection signal so that the counter is reset when a reset detection output signal is issued by another program control circuit. 1
．． 10. A control circuit as claimed in claim 9, characterized in that it includes a cut feedback conduit. 11. The intermittent energization circuit receives and receives the intermittent energization control signal from the counter, and when the intermittent energization control signal is generated by the counter and the reset detection output signal is generated. The intermittent energization circuit includes a gate in communication with a reset feedback path to receive the reset sense output signal to energize the FROM. A control circuit according to claim 8. 12. TTL-FROM having multiple memory cells programmed with multiple code languages: In order to operate the above-mentioned FROM so as to output code languages in parallel format according to the count of the counter, A CMOS connected to a FROM to address memory cells in parallel with a predetermined number of bits of address language.
Counter: Receives a code language in parallel form from FROM, and a serial output for providing a serial code signal corresponding to one bit position of said code language in parallel form and another of said code language in parallel form. a parallel-to-serial shift register utilizing a CMO8 having at least two parallel output terminals for providing an auxiliary parallel code language corresponding to two bit positions; output means for receiving the serial code signal therefrom and operating the display means in response to the nuclear serial code signal; and output means necessary for addressing the FROM and moving the parallel code from the FROM to the parallel-to-serial shift register. An energizing terminal of a counter that intermittently emits an energizing signal such that the FROM becomes energized only during a time period, and the FRO
1. An intermittent energization circuit connected between M and M. A control circuit for a display device, characterized in that it includes: 13 The auxiliary parallel code language includes a reset code signal and a reset terminal of the counter and two of the shift registers for resetting the counter when a predetermined reset code signal is generated at the two parallel output terminals. 13. The control circuit according to claim 12, further comprising a reset circuit connecting two parallel output terminals. 14. The reset circuit includes a tuning terminal for coupling to at least one other program control circuit so that the counter can be reset immediately upon receiving a tuning reset signal from another program control circuit. 14. The control circuit according to claim 13, characterized in that: 15 When the intermittent energization signal is issued by the counter and when the counter is reset, the FROM
The control circuit according to item 12 of the scope of the patent application, characterized in that a reset circuit is connected to an intermittent energizing circuit for energizing the circuit to bring it into a energized state. 16 When the intermittent energization signal is issued by the counter and when the counter is set, the FRO
In an intermittent energizing circuit for energizing M and making it energized,
15. The control circuit according to claim 14, characterized in that the reset circuits are connected in series.