JPS5976122U - AGC circuit - Google Patents

AGC circuit

Info

Publication number
JPS5976122U
JPS5976122U JP17119682U JP17119682U JPS5976122U JP S5976122 U JPS5976122 U JP S5976122U JP 17119682 U JP17119682 U JP 17119682U JP 17119682 U JP17119682 U JP 17119682U JP S5976122 U JPS5976122 U JP S5976122U
Authority
JP
Japan
Prior art keywords
agc circuit
circuit
agc
input signal
control element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17119682U
Other languages
Japanese (ja)
Inventor
今川 敏幸
Original Assignee
クラリオン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クラリオン株式会社 filed Critical クラリオン株式会社
Priority to JP17119682U priority Critical patent/JPS5976122U/en
Publication of JPS5976122U publication Critical patent/JPS5976122U/en
Pending legal-status Critical Current

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Landscapes

  • Circuits Of Receivers In General (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は共に本考案を説明するための特性
図、第3図は本考案実施例を示すブロック図である。 3・・・分岐回路、6・・・RF増幅回路、■・・・第
1のループ(第1のAGC回路)、■・・・第2のルー
プ(第2のAGC回路)、Ql、Q2・・・トランジス
タ、Q3・・・FET0
1 and 2 are characteristic diagrams for explaining the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. 3... Branch circuit, 6... RF amplifier circuit, ■... First loop (first AGC circuit), ■... Second loop (second AGC circuit), Ql, Q2 ...Transistor, Q3...FET0

Claims (1)

【実用新案登録請求の範囲】 1 チューナの一部に入力信号に対する第1のAGC回
路および第2のAGC回路を設け、入力信号レベルが増
加した時先ず上記第1のAGC回路を動作させ、さらに
入力信号レベルが増加して第1のAGC回路が飽和レベ
ルに達した時次いで上記第2のAGC回路を動作させる
ように構成したことを特徴とするAGC回路。 2 上記第1のAGC回路および第2のAGC回路が各
々第1の回路制御素子および第2の回路制御素子を含み
、上記第1の回路制御素子の出力力釦−レベルになった
時上記第2の回路制御素子をオンさせるように構成した
ことを特徴とする実用新案登録請求の範′囲第1項記載
のAGC回路。 3 上記第1のAGC回路が入力信号を第1のAGC回
路および第2のAGC回路に分岐させるための分岐回路
を含むことを特徴とする実用新案登録請求の範囲第1項
又は第2項記載のAGC回路。
[Claims for Utility Model Registration] 1. A part of the tuner is provided with a first AGC circuit and a second AGC circuit for an input signal, and when the input signal level increases, the first AGC circuit is operated first, and An AGC circuit characterized in that when the input signal level increases and the first AGC circuit reaches a saturation level, the second AGC circuit is operated. 2. The first AGC circuit and the second AGC circuit each include a first circuit control element and a second circuit control element, and when the output power button of the first circuit control element reaches the level 2. The AGC circuit according to claim 1, wherein the AGC circuit is configured to turn on two circuit control elements. 3. Utility model registration claim 1 or 2, characterized in that the first AGC circuit includes a branch circuit for branching the input signal into the first AGC circuit and the second AGC circuit. AGC circuit.
JP17119682U 1982-11-12 1982-11-12 AGC circuit Pending JPS5976122U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17119682U JPS5976122U (en) 1982-11-12 1982-11-12 AGC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17119682U JPS5976122U (en) 1982-11-12 1982-11-12 AGC circuit

Publications (1)

Publication Number Publication Date
JPS5976122U true JPS5976122U (en) 1984-05-23

Family

ID=30373510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17119682U Pending JPS5976122U (en) 1982-11-12 1982-11-12 AGC circuit

Country Status (1)

Country Link
JP (1) JPS5976122U (en)

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