JPS5969543U - Mute amount adjustment circuit - Google Patents

Mute amount adjustment circuit

Info

Publication number
JPS5969543U
JPS5969543U JP16673282U JP16673282U JPS5969543U JP S5969543 U JPS5969543 U JP S5969543U JP 16673282 U JP16673282 U JP 16673282U JP 16673282 U JP16673282 U JP 16673282U JP S5969543 U JPS5969543 U JP S5969543U
Authority
JP
Japan
Prior art keywords
mute
adjustment circuit
amount adjustment
mute amount
amount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16673282U
Other languages
Japanese (ja)
Inventor
井川　佳久
Original Assignee
富士通テン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通テン株式会社 filed Critical 富士通テン株式会社
Priority to JP16673282U priority Critical patent/JPS5969543U/en
Publication of JPS5969543U publication Critical patent/JPS5969543U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の簡略化した回路図、第２図
はソフトミュート量が調整されることを説明するための
グラフである。 １・・・ＦＭ放送受ｉ機、２・・・ワイヤレスマイク、
７・・・集積回路、１３・・・端子、ＳＷ・・・スイッ
チ、Ｒ１，Ｒ２・・・抵抗。FIG. 1 is a simplified circuit diagram of an embodiment of the present invention, and FIG. 2 is a graph for explaining how the amount of soft mute is adjusted. 1...FM broadcast receiver, 2...Wireless microphone,
7... Integrated circuit, 13... Terminal, SW... Switch, R1, R2... Resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 周波数変調放送受信機におけるソフトミュート′　　　
　　量を決める端子に異なる抵抗値を有する複数の抵抗
がスイッチを介して切替え自在に接続されて成ることを
特徴とするミュート量調整回路。Soft mute in frequency modulation broadcast receiver′
1. A mute amount adjustment circuit, characterized in that a plurality of resistors having different resistance values are connected to terminals for determining the amount of mute in a switchable manner via a switch.
JP16673282U 1982-11-01 1982-11-01 Mute amount adjustment circuit Pending JPS5969543U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16673282U JPS5969543U (en) 1982-11-01 1982-11-01 Mute amount adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16673282U JPS5969543U (en) 1982-11-01 1982-11-01 Mute amount adjustment circuit

Publications (1)

Publication Number Publication Date
JPS5969543U true JPS5969543U (en) 1984-05-11

Family

ID=30364954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16673282U Pending JPS5969543U (en) 1982-11-01 1982-11-01 Mute amount adjustment circuit

Country Status (1)

Country Link
JP (1) JPS5969543U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127114A (en) * 1976-04-19 1977-10-25 Hitachi Ltd Muting circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127114A (en) * 1976-04-19 1977-10-25 Hitachi Ltd Muting circuit

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