JPS5962969A - Production management system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

The present invention relates to a production control system for on-site management of factory operations, and particularly, but not exclusively, to the management of various functions in a clothing manufacturing factory. In today's operating conditions, clothing manufacturers. If they are to survive, they need to tightly manage both their factory costs and their investments in cash on hand and work in progress.
In recent years, organizing and managing a clothing manufacturing company has become
While generally becoming increasingly complex, the tools available to assist managers and supervisors in managing factory operations have not seen much change. Therefore, one of the purposes of the production management system disclosed herein is to control the main functions within a garment manufacturing factory, such as production planning, production schedule planning, factory surplus management, progress management, and section/line balance. adjustment. It is to provide real-time management of work-in-progress level management, and total wage and labor cost management. While existing systems historically report what happened in the factory yesterday, the purpose of the online production control system disclosed here is to achieve ultra-modern control of manufacturing operations so that they can report on what might happen in the future. It is about being able to take corrective action to prevent a problem. According to one aspect of the invention, a production or factory work management system for a factory environment is provided, which system includes multiple card readers located at nine worker work stations. It consists of an input device and a multiplexer/concentrator consisting of a microcomputer and a microprocessor pair, which continuously scans the operator input device. The microcomputer includes one microsequencer that receives data to be sent to a microcomputer, and the microcomputer receives data from the operator input device by the microsequencer as the card is read on the one operator input device. It checks the validity of the input data, writes good data into short-term memory, and returns a signal to the microsequencer indicating whether each data input is valid or not. The microcomputer has a human output port for communication with a host computer, such as a minicomputer. Microprocessor/micro sequencer. It may be a single level pi-blind type bipolar bit slice microprocessor driven by writable microcode. The microcomputer. It may also be a Z80 computer board. According to another feature of the invention, a worker input device is provided for use in a system of production or factory work control, which device can be used to hang cards or slips with encoded data. a card reader that scans the card and generates electrical signals representing the coded data described above; a cable for providing low voltage external power to the operator input device through a set of electrical lines; an output signal of the card reader; A pulse train generation circuit for obtaining a stream of pulses of at least two different durations representing encoded data in response to fj? and short-circuiting means for short-circuiting said first set of lines for a time corresponding to the duration of said pulses in response to said pulse flow with said first set of lines as a power source; This allows the data on the card or slip to be entered by the operator using the input device. It is routed through the same first set of cables that power the operator input devices. The shorting means can also be driven by an optical isolator having a radiation emitter to which the aforementioned pulsed stream is applied and a receiver that is electrically isolated by a diode or the like and is responsive to the reflected line from the aforementioned emitter. In the preferred embodiment, each card or ticket has two parallel barcode trunks, the first being a clock trunk with equally spaced narrow bars, and the second being a clock trunk with equally spaced thin bars. The data 1-rank is located at a position corresponding to each thin bar bit of the clock track and does not indicate "1" or "0" but has a thick bar or gap, and the scanning means scans the clock track. A first emitter/receiver combination scans the data trunk and a second emitter/receiver combination scans the data trunk. The operator input device includes two monostable circuits with different times for generating pulses of different widths and a data input device in response to signals from the receiver of the scanning emitter/receiver.
and logic circuitry for directing each clock pin 1- to the trigger input of either monostable circuit depending on whether the I rank indicates a par or a gap at the same time. The outputs of the two monostable circuits are gated together to provide a pulse stream that is applied to a transistor that provides an output to the light emitting diode of the optical isolator. The worker input device further includes an audio and/or visual response device;
The device is energized by an external power cable when the polarity of the voltage applied to a set of cable lines is reversed. According to a further feature, the communication between the multiplexer/concentrator and the host minicomputer is established by a serial link that also includes an optical isolation device. Power is transferred through one transformer. The system tasks factories with producing the optimal combination of styles, allowing them to meet customer delivery demands while maintaining target production levels.
Product levels can be maintained at the level required for efficient factory operation, and manufactured orders are systematically manufactured and appear as finished products in the warehouse within a minimum throughput time. Although much of the hardware used in the systems described here has been designed and constructed specifically to meet the needs of the garment industry, these hardware can also be used in many other industries, especially the A worker input device can be used as a means for inputting information about a worker, his particular task, and the work to be performed into a computer processor. One worker input device is installed at each worker's station and is used to read barcoded worker cards, work carts, and handle cards submitted by one worker. Each operator input device is connected to a microcomputer controlled data console or multiplexer. The multiplexer performs a type of examination on the data provided by one operator input device and then transmits the data to a central computer system for processing.
This central computer system is a minicomputer system, such as a Heuleno 1-.
Paso Card HP 1000 may also be used. Each supervisor may have a terminal device containing a small display device that is connected to the central computer system and used to enter information into and retrieve data from the computer. The worker input device allows each worker to record turn-in and turn-out times at the beginning and end of the day, eliminating time wasted in front of a traditional time clock. The worker can see what work is currently being done and which jobs/jobs.
Also for reporting to the central computer whether work on a lot is in progress. Use this device. This allows the central computer to calculate gross wages completely automatically. Workers have three types of cards, viz. A personal card that he/she uses to record entry and exit times, a work cart that he/she uses to indicate the work he/she is performing, and The operator uses the Job 1 card to indicate which Job 1 he is working on. Supervisor A1!1's terminal device is a television type. It is equipped with a keyboard, which supervisors can use. How much work did each worker do on that day? information about how fast he/she is working;
Information on where each job/lot is located in the factory and information on which jobs are waiting at each worker's station can be called up, allowing for a better balance of work flow within the factory. It is possible to supervise to achieve the following. From the screen, the supervisor can also obtain an accounting report showing all section rejects and worker downtime in terms of hours per worker and costs. The whole system is real time and that is. Whenever a supervisor requests information, it means that the information is up-to-date. This system can solve all types of problems, such as production falling below the minimum amount per hour in an operation;
7. Alarms can be issued from the supervisor's terminal device to supervisors regarding specific machines remaining out of order for more than a certain period of time, or when the amount of work at a specific station exceeds a warning level. I can do it. The configuration based on the present invention will be described below by way of example with reference to the accompanying drawings. FIG. 1 is a perspective view of an operator input device with a card reader. FIGS. 2A and 2B are circuit diagrams of a three-worker input device. FIG. 3 shows a barcoded card of the type that is captured by the card reader of one operator input device. FIG. 4 is a diagram showing an emitter and receiver configuration for scanning a cart in a card reader. FIG. 58 and FIG. 5B show that one operator input device is scanned,
This is a circuit diagram of a micro sequencer that receives and responds to data input from it. FIG. 6 is a circuit diagram of one of the eight channels used by the microsequencer to communicate with operator input devices. FIG. 7 shows a circuit diagram of one of a number of subchannels that each channel shown in FIG. 6 can use to communicate with a group of worker input devices. Figures 8Δ to 8J are circuit diagrams of a block of a ) 280 microcomputer that performs full control of the microsequencer of Figures 5A and 5B and interfaces with the post computer. FIG. 9 is a circuit diagram of an isolating adapter circuit for interfacing the 780 microcomputer shown in FIGS. 8Δ to 8J with a Bost minicomputer, and further. FIG. 1θΔ and FIG. 10B are timing diagrams of the channels and subchannels of FIGS. 6 and 7. The operator's power equipment is driven by a multiplexer. This device is standard HI) 26
The software driving the 3113 printer can read optical barcodes created elsewhere. The operator input device reads the data and the clock track and sends the results to the multiplexer concentrator. The multiplexer concentrator returns the reading status to the worker input device, which in turn communicates this to the worker by audio/visual response. This device consists of two microprocessors (one micro-coquenzer or human slicer and a Z80 computer board). . A combination of microcode and Fargoware allows data from up to 128 working °H input devices to be permanently stored and updated to a database 11
Allows the storage device to temporarily store data for up to 8 hours as a backup for data transmitted to the PIOOO central amplifier. The database provides real-time information to the field equipment. data transfer between the multiplexer/concentrator and the central 21 computer is based on the R3423 protocol.
This is done via an isolating adapter circuit that allows interfacing with the S232 SOLE. Data transfer between the multiplexer/concentrator and the worker input devices, and power supply from the multiplexer/concentrator to the worker input devices, is performed by a system of channels and subchannels. Software for the above hardware includes: Microsequencer Software A microsequencer or focus slicer is provided with microcode that allows it to scan operator input devices and respond to data input from one operator input device. Z80 Software Z80 Software is a program that loads microcode into a microsequencer; and the main program that allows the Z80 to control all operations of the multiplexer/concentrator. Now, let's consider the operator input device (Fig. 1).The external appearance of this device is a box 10, and a card reading slot 11.
Side leader representing 12. and green and red light emitting diode signal lamps 13 and 14 attached to the front of the two boxes.
have. One set of twisted cables provides a link between one operator input device and the multiplexer/concentrator, and five data signals between the operator input device and the multiplexer/concentrator and the multiplexer/concentrator.
It also carries the 24V power supply from the concentrator to the operator input devices. As previously mentioned, the multiplexer/concentrator can support up to 128 operator input devices. Box 1 of worker-powered equipment
0 accommodates one printed circuit board. There are three types of data entered through operator input devices. They are. Identification of an employee (worker). Identification of one work (workpiece). It is identification of one work iuniso 1- (job・roso t-). The operator-powered equipment itself does not have the ability to manipulate different types, but merely detects signals and sends the detected signals to the multiplexer/concentrator. When power is applied, the green lamp 13 remains lit to indicate that the two-worker input device is in operation.
When the card is passed through the reading slot 11, the data is read and sent to the multiplexer/concentrator where it is checked for three possible states. One of these conditions is returned to the operator input device where both an audio signal and a visual signal by the red light 14 are emitted. The three states returned to the operator input device are: That is: 10. If the "OK" car reading is accepted without any physical or logical errors, a single audio tone and a single red lamp pulse are emitted from the operator input device. The 9 worker can then return to his/her work. 2. A woman's appearance However, in reality, the award system allows two job lots to be hung in one go before the acceptance is accepted. It is designed that the identity of the worker (employee) and the type of job (task) must be entered in this order. That is. Sequences other than 'AJ invalidate the processing of one work ticket, and therefore prevent one worker from successfully reading the correct input in (1) above. A red lamp and audio signal generator return a train of six alternating long and short pulses to allow two operators to distinguish between logical and physical errors. 3. Machida” pull

[Amusement car physical errors are caused by misreading features on the input card (of either type). This can occur due to damage to the card, incorrectly inserting the card into the reader, or a malfunctioning operator input device.
Operator input device. The green lamp 13 is designed to turn off if there is a physical malfunction. In case of a physical error, a train of eight short constant pulses is emitted by the audio signal generator and the red lamp. When the operator input device reads a barcoded card, the black-to-white ratio on the bar card is detected by an infrared sensing element and converted to a digital pulse of the correct width. Depending on the bar card read, the multiplexer/concentrator responds by sending a coded tone to the operator input device indicating a good read. Identify whether the error is physical or logical. The channels of the multiplexer/concentrator to which the operator input devices are connected connect one line A to one 12
Hold it at +12V through a 0Ω resistor and hold the other line B at -12V through another 120Ω resistor. If this is your circuit's pass state and you want the multiplexer/concentrator channel to acknowledge some reading, the polarity is reversed and the audio signal generator in the operator input device and excite the lamp. The steady state current is about 20 mA and a voltage of about 18 V is available at the terminals of the operator input device. The operator input device itself generates a signal by non-conductively shorting the line for a short period of time. 0 bit by 100 microsecond pulse. Each bit is represented by a 300 microsecond pulse. In fact, they are drawn to within about 4 inches of each other rather than a short circuit. Referring to FIGS. 2A and 2B, the circuitry for the two operator input device is as follows. The voltage applied between input terminals 15 (line A) and 16 (line B) is
through line isolating diode 7 to reservoir capacitor 18, which is charged to approximately IGV (line minus two diode drops). This feeds the 12V regulator 19, which powers the rest of the circuitry, but excludes the audio device 20 and red lamp 14, which are
When the terminal reels 15 and 16 are at lightning voltage, they are cut off by a diode 21. The series chain includes a brightness adjustment resistor 22 and three light emitting diodes, one of which is a green (ready) lamp 12 and the other two are infrared light emitting diodes 23, which track the clock and data on the card.・】・Illuminates the rack. The data trunk and clock track on the card are each illuminated by a light emitting diode.
They are read by respective phototransistors 26 and their outputs are fed to respective identical circuits 24 and 25. Circuits 24 and 25 each include one cascade 27 and one MOS FET operational amplifier 'N+!
It includes a device buffer 28. Resistance chain 29 is 5
Both circuits 24 and 25 cascade and amplifier 39 are biased. Operational amplification z: (28 is the card being read.) The second black bar has a high output. The duration of the worker input device, 1-, is 300 microphones 1: J seconds 1'< stable circuit 31 (I pinot 1~) and 1
00 mic l: 1 second determined by the monostable circuit 32 (obi, g). Using the 3-game 1-.1-l thick circuit 30, the 1-circuit 25 signal I-I-1-thick signal output is determined by the data track signal υ output of the 2-gate circuit 24.
It is switched to the monostable circuit 31 to generate a bit (data black), or it can generate a 0 bit (data black).
The monostable circuit 32 is switched to generate a white signal (white). A transition from white to black on the clock track will therefore cause either of the rl'4 stabilizing circuits 31 and 32 to reset. The outputs of both vehicle ballast circuits are combined into a single pulse train in one OR gate 33, the output of which is applied to the base of a drive transistor 34, which drives an optoisolator 35. Opto-isolator 35, 1 to photodiode 36 in series with transistor 34. and a 1-) run sister 37. Hollow transistor 37 and output quadrant sister 38 forming a Darlington circuit. Through isolating diode 41 and damping resistor 42 lines 39 and 40 are effectively shorted. Line polarity reversal by multiplexer/concentrator at terminals 15 and 16. an audio signal generator 20 and a lamp 14 in parallel with it;
Excite via diode 21 and then. The remaining operator input device circuits are blocked by diode 17. FIG. 3 shows a typical barcoded card 43 read by nine operator input devices. Clock tracks 44 and data tracks 45 are located one directly below the other, and the clock trunks are thin vertical bars evenly spaced horizontally that carry data tracks.
The truck is. They are thick bars arranged irregularly. The clock track contains 60 OR symbols, and the data 1-rank is marked by hanging the cursor symbol under the corresponding clock pulse.
There, the data bit will be 1. bottom edge of card 46
The data, I, rank and clock track are printed in the 4II11 to 17 fin range from the bottom. Barcode, 1 to rank &J,
Printed on a relatively thin white flexible sheet by an IIP 263113 printer. Each card, for example a job lot card, is in the form of a tag so that it can be easily stapled to a workpiece. Cards can also be printed on sheets with the combined width of several cards and then cut with a cutting machine. FIG. 4 shows the reader 12 inside the input device 10 for one worker.
The scanning mechanism of the emitter and receiver of is shown. The zero reference end 46 of the card 43 rests on the horizontal upper end 47 of the shim plate 48 at the bottom of the card reader slot 11. Cards are placed horizontally. It is moved through the leader slot from the back of the leader to the front. two infrared light emitting diodes 23
illuminates clock track 44 and data track 45, respectively, and two bottom transistors 26 each receive the reflected light from these trunks. Bol
-) The transistors 26 are angled diagonally to provide adequate spacing, and the clock trunks 44 and data trunks 45 are scanned through wedge-shaped transparent blocks 49 and 50, respectively; The blocks are separated by opaque bodies 51 and further. Opaque bodies 52 and 53 are placed above and below the transparent block. The body portion 54 of the reader 12 located on the side of the slot 11 remote from the emitter 23 and receiver 26 can be removed. It is opaque and non-reflective. Referring again to Figure 3, the format of the barcode on each card (starting from the tip when hung on the reader) is as follows (each byte is read least significant bit first): Note): 1. 4 run-in pitches: '1010 + 2. 1 synchronous hide (ASCII
(ASCII hexadecimal): '01101000J = 8 bits I.3, most significant high 1 - 4 data hides with lowest high 1 sent first - 32 bits 4. 1 error correction code 1 - (ECC ) Hyde - 8 pins 5. 1 parity high 1 - 8 hits A total of 60 bytes. 16 bits of parity river and E for error detection and correction
CC Hyde understands the nature of the card and the purpose for which it will be used to better protect your data. As already mentioned, the multiplexer/concentrator consists of two microprocessors, I! II. Includes one Z80 board and one micro sequencer. The Z80 computer board controls all operations of the network multiplexer and interfaces with the host H100 (lE) minicomputer via a serial link. 280 microprocessor and the operator input device. It is a bipolar pill-slice microprocessor driven by writable microcode, which executes 128 pulses in an unending sequence. scans the sub-channels and services one operator input device,
Data between them and the 780 is buffered in both directions. The 128 subchannels are grouped into groups of four. Four groups of four (16 channels) are served by each of the eight main channel boards,
The board is serviced by a micro sequencer. The microsequencer (Figures 5A and 5B) is based on the Advanced Micro Devices 2900-series integrated circuit. Basically. It is a standard AMD2901 single level pi-blind microprocessor. The microprogram is organized into a 256 word x 32 bit array and contains 4
, X 8 Pino 1-Static RAM) are stored in the memory array 55. Microprogram sequencer 56 is 8 bits wide and consists of two cascaded 2909 chips. The order of only two (=
Joke mode is used: i.e. sequentially (SO=31=0
), or direct branch (SO=31=1). A direct branch can be modified by the three S-Pino 1~ of the status register 57 to perform a different 8B branch depending on the state of the subchannel when received at 8G. Microprogram words are denynoded and latched into various chips 58-64 at the beginning of each clock cycle. Whenever a microword field is encoded (e.g., four "data
'in' path is encoded in bits 25/24),
The decoder chip (eg 61) is second stream to the latch (eg 62) to increase speed. For microwords, the “data out” field (bits 28-
26) according to the value in 2-branch or arithmetic logic unit (Δ■
, U74) Specify the instruction cycle. If all of these bits are 1 (ζ including branch instructions), the microb 1 cogram branches or continues depending on the following conditions. 1111:). a, one “ of the mask field (bits 18-8)
1”, there is a status register with a value of “1”.
Whether there is a bit or not. 11 pin-・Status・
The register is logically ORed with the 11 bit mask field and the resulting 11 bits are ORed together. b, state of one R-Pi1-(21). In the case of 0, one branch is performed for any "1" under the mask. Otherwise, the sense of one branch is reversed. c, one S-bi, 7l-(20) condition. "1"
In the case of , the contents of S-Pi1~ of the status register are ORed and entered into the branch address. This will be the 8B branch. The branch address is D-field 1,'(
7-0). ■-Field (ΔL U
instructions) are always 0 (NOP) for branches. Prevent ΔLU from changing any registers. 1] - The in field is not important for branch instructions. If the D-out field is not all ones, an eight LU instruction is indicated, however, in this case bit 1G is just 'IJ. The reduction of the I-field from the corresponding 9 pino1- to 8 bits creates a more convenient scheme for assigning the microphone l-1 word pino1-. 1-field is I]
- If specifying input from human power, this is obtained from one of the four sources indicated by the D-field (Pino l-25, 24). these are. 0-Microphone L:1 (N data field in command (Pino L-7-0) 1-280 combination parallel output (e.g. microsequencer manual power from control computer) 2-8L U
74 Carry-in-zero: Data RAM with 1 73 3-1 timer cycle ALU Data RAM with carry-in-zero, everything else. Near the end of the microcycle (t==200 nanoseconds), the output of ALU 74 is strobed to the destination specified by the D-out field, as follows. ○ - None 1 - Data RAM 73 2 - 280 parallel inputs (e.g. microsequencer output to control computer) 3 - Low (i7 RAM address register 654 A
RAM address register 665 - Low RAM address output to channel and subchannel AND External (E) register 67 (i-E register 67 only (71- (branch instruction) ) is latched into the "scope trigger" register 68. This is for diagnostic tracking purposes only. The clock is a standard 8 MIIz oscillator 69. This oscillator is followed by a binary divider ν:) 70. , 4.M1
It generates 12 square waves (basic clock pulses). This goes into one delay line 71 with five 50 nanosecond taps, and the decoder 72 has three auxiliary clocks.
Generates a pulse. Rising at t=Q t=250
In relation to the basic clock (CI-3) falling at , these auxiliary clocks are: i.e. OA-stands at 〇' and falls at 25. Lotus・
Temporarily disable the data in bus to avoid contention. It falls at 013-150 and rises at 200. Activate the data RAM write enable pin. It rises at QC-200 and falls at 250. Clock the data out register. All clock signals are 780 output capo-1-P I O
When bit 7 of B is "1", interrupts are disabled. Timer 75 is a free-running LM555 oscillation that operates at approximately 16 Hz! :4. This oscillation [:,
i is caused by 1 circuit 76 and microphone 1-1 and 11 grano. Synchronized. -7i//l:l:,:I-During the initialization cycle, register 77 is connected to the microword address line and four registers 78 (32 bits) are connected to the data line. Connected. The 280 software loads each of the five registers for each microword and finally loads the array T! 71.Stripe the i-load line r:1- and fill the array with words 71. Get into it. Boats A and +3 (Z80 computers) are the data and control/address boards I for this operation. - After one code of the I-1 code. Bit 6 of boat B is set to 0, which converts the above configuration to minute Ii! lt L , generates a normal pipelined data file 1-1-. Then bit 7 of boat B
is set to O, which enables clock pulses. The circuit 79 causes the microphone Elp II graph J1 to start cleanly from address O.
Register 80 is addressed via register 85 to specify the (\route) of Z80 data from ~8. Register 82 is used to specify the i\route city of the data to Z80. Stabilizer circuits 83 and 84 provide Δ and B pulses for timing of bidirectional huffing to the boat. A list of timer 1j2 1-1 for microphone 1-1 sequencer shown in the figure is in the old specification (
=J record 1 and appendix. Zoshi1 Grano, ha! ! I? fib! 7. Operates on a cycle of 7. Run tab channels 0 to 127 (decimal) for 1 yen. The board has 8 high I...work...on each pear channel river.
including the area, which is first formatted by the reset function. Each work area, 1. All 6 slots, including the current state, current tights, out value, and current Hyde and Hihino 1 to Karan 1 of the ``Sheeny Jannel'' are initialized as follows. That is. Status-0 Time Alarm I・-15 High 1-(cell)-2 Bit-〇. The cycle starts at position 0. If the reset line (from 280) is true, a branch is made to the reset routine. The subchannel counter is incremented and
Then the 1.2 line (to the channel) is activated. (If the subchannel is 0. This pulse is extended and if this is a timer cycle, the 'r-status is set.) The state of the subchannel is determined by the current state. Microphone 1.1 :: Used to branch immediately to the entry point of I-1'. The state of each subchannel changes as follows. That is. State 0-Stop: Enter from recess 1-. As soon as there is a request for an operator input device, the state moves to state 1. State 1 - Reading synchronous characters: Enter from state 0. As soon as a synchronization character is detected, state 2 is entered. When the timeout expires, the state moves to state 3. State 2-data #7+; Transfer: Enter state 1. When the last end of the data is received, or when the exit is completed, the state moves to state 3. State 3 - Completed color preparation for sending φm to Z80: State 1 or 2
Enter from. When the path of microsequence No. 7110 is vacant, the state moves to state 4. Dark! , u:, 4- Data transfer to Z s o: state 3
Enter empty. 9 high I・(subchannel address and 8 high i・
- Manok area) is transferred, it moves to state 5. State 5--Z80 is empty: Enter from state 4. When Z80 returns Acrunoji-1-de and Morse ml-de hF'''j is created in the soak area, the state moves to state 6. State 6 - Acrunoji to operator manual equipment: State 5 Enter from Morse... for each timer...
The next bit of the 1-code is sent to the operator input device. Once all J-do bits have been sent, state 7 is entered. State 7 - Enter from state 6. Selectively subchannel
After cleaning the work area seven times, it moves to state O. Sho: States 4 and 5 can be used for a single subchannel at a time. All other states are shareable. FIG. 6 shows the circuitry of one of the eight channel boards that serves as the inkface between the microsequence of FIGS. 5A and 5B and the working qN human power equipment (via subchannels). Each channel has its own unique channel address (bits 0-7) and activates a switch on the board. It can support up to 16 subchannels. Each subchannel maintains one worker-powered device. The microsequence number is connected to the channel timing (Figures 108 and 1013) via a hackplane line (SYSCK/EC) inputting to the channel at 116.
2). The microprogram causes this line to deliver a pulsed stream at the beginning of the subchannel period. At the beginning of the subchannel O period, this pulse is 1ffI, which is 750-1 to 2 seconds, and is extended to 1500 nanoseconds. Each cycle is 128 Zazo channels long. At the trailing edge of each 1.1 pulse, a monostable circuit 88 is activated to emit a pulse of approximately 150 rhinoseconds. This pulse is sent through one delay line 89 with 100 nanosecond taps. The original pulse and the first three delayed pulses are referred to as ']'O,'I'1'1'2 and '1'3, respectively. Second monostable circuit 90 (period 11
00 nanoseconds) is clocked at 1" at the leading edge of the R1 dock pulse and clocked at 11 o'clock at 'l". Ishi1-
If it is, it is cleared, and if it is not, it is incremented. The effect of this is that all channels' counters keep pace with the microsequence number. The upper 3 bits of the 7 bits counter are connected to the comparator circuit 9.
3, it is compared with the address set by address switch 94. Equal status means that this channel is selected, which activates subchannel decoders 95 and 96. The same signal is ANDed with T3 at 97 and becomes 98
The subchannel decoders 95 and 96 drive one line per subchannel and output the channel clear J (CHCL R) signal to the counters 91 and 9.
A subchannel is selected according to the lowest four hits of No.2. The basic subchannel circuit is shown in FIG. The line drive circuit 99 is simply a bidirectional switch. In the energized state (low input), line 8 is set to 120
Hold at +12V through an ohm resistor and connect line B to 120 ohms.
It is held at -12V via a resistor. Therefore, 1 normally line A is positive and line B is negative, and due to the constant current of the operator input device of about 20 mA, the actual voltage is about +/-9. The operational amplifier E:'r l 00 examines the - pair of lines using a balanced differential large-capacity software 101, and its output is 1 after performing clamping and filtering at 102.
Under normal line conditions, input point 1 to the monostable circuit 104
03 is a logic zero. The operator input device inputs the OJ bit signal to line 10.
Send by 0 microsecond short circuit pulse and by bin 1-300 microsecond pulse of "1". At the leading edge of this pulse, monostable circuit 104 is activated for a period of 200 microseconds. At time 70, flip-flops 105 and 10G are clocked and 'F1
Sometimes they have 0 and 1 respectively. For example, when the Q:4 stable circuit 104 falls, 〆1 (flip-flop 1
07 indicates receipt of a new bit from the operator input device. Data flip-flop 108
is cleared or cleared according to the current line state, which is the same as the data bit value. When a subchannel is accessed, flip-flops 107 and 108
The contents of are applied to internal bus 109 by game 1-110. Data flip-flops and preparation solver-flops. When subchannels are selected, they are cleared through gate 111 at 13:00, ie, as soon as they transfer their contents to the common data/preparation circuit 112 of the parent channel boat. 2 selected subchannels at T2: tlB flip-flop 10 data flip-flop 108
is clocked into the common data and preparation flip-flops 113 and 114 of the parent channel;
These are the hackbrains that go back to the microsequencer.
line through gate 115. The Microphone Sequencer can activate the 117' line reversal J backplane line during the subchannel cycle to activate the red light and audio signals of the 9 operator powered equipment. Signal (LINE REVER
SE/-EΔ) is received by the channel board and routed to the input 118 of each subchannel circuit to trigger the (lj stabilization circuit 119 in the 2 selected subchannel circuits). This monostable 1? product stretches the pulses into groups of 1/1 Gsec. Bidirectional switch 99 is actuated to reverse the polarity of line AB. The other input to monostable circuit 119 is the subchannel selector. Z80, which controls the operation of the network multiplexer, is driven by line 120 to ensure that the correct subchannel responds.
The board is shown in Figures 88-8J. In the initial configuration, Bau 1-' microphones the microcode) and loads it into the Nokenzer, causing it to perform a full system reset. After that, the Z80 board receives the Menosenoji block from the microsequencer,
Inspect them and send back the appropriate accursogi code. A good Zorotsuk is high 1 on that 256--memory 1.1! and transmitted to the host computer via a direct link. The Z80 board is highly modular in design and arrangement. The board contains the following functional blocks:
That is. 1. Central processing unit (CPU) 121 2. Read only memory (ROM) 1223, Random access memory (RAM) 124, Clock 125 5. Wait state/reset circuit 126, 1276, Input/output decoder 128 7. Memory Mapping circuit 219 8, Counter/timer/1000 knobs (C, TC) 13
09. Serial interface to post computer
(SIO) 131 10, Parallel interface to micro sequencer (
PIO) 132°1, CPU This is a standard 4 MHz-280 processor chip 121. Since direct memory access (DMA) is not used, the address lines are latched and inosored only in the outward direction. The data lines are connected directly to the common bus. Control lines are routed outward. 2.ROM 1? OM array 122 is a 2716 type E'PRO
Consists of 8 sockets for M5124. After reset, this array is mapped to the first 16 runts of the Z80 address range (high 1--power 1).C
I) [Execution of J begins at memory location zero. The board has a ROM program that stores all eight calculations in RAM.
Copy it to the first IGK. It is designed with the premise that you can then move on to it. ROM l:1 - The reader uses this as a memory master.
This is done by simultaneously switching the ROM online and the first 16 of the RAM online, using a parallel port controlling the input circuit ++'8. After that, the CPU cannot access the ROM. It doesn't work. The I'20M data output is filtered to reduce capacitive loading. 3. RAM This array is an array of 4 x 8 64 K Guinaminoku R to M chips 123 that are powered. The address bus to this array is 18 bits wide, consisting of the 3 (upper) bits from the master nopping circuit plus the lower 15 bits of the Z80 address bus. 4. Clock This circuit is a standard 4 MHz clock 125. 5. Wait State/Receive 1-Circuit These are standard mostic circuits 126 and 127. The wait state function 126 allows one wait state to be
is inserted into all memory accesses while the memory is available. This only happens during initial setup and RO
This is due to the slow access time of the M chip. Reset circuit 127 is activated by power-on or an external button. For this board, there is no need to save the contents of RAM upon reset, so a very simple circuit is sufficient. 6. Human output data CTC, SIO, micro sequencer Pro. Decipher the four ports 1 to selection codes (1-4) for mapping PIO from the address line. This decoding is not exhaustive, since no further input/output chips are required. 7. Memory mapping episode 11! 'r 129 mapping I) I O Δ baud 1-136 low 4 via 1,
controls this feature. after reset. These bits all take high values. In this state, Z
80 is R in the lower quadrant of that atlus space
The OM array is examined and access to this quadrant 1- and the next I' runt of RAM is disabled. R
The OM coat is intended to directly set Pino 1-1-3 to cello (leaving Pino l-0 high), and in this state, if the field is set to low 32 in RAM, Z8
0 Appears in the upper half of the address space. with this,
The ROM loader can copy all the code into the lower part of the RAM and the code will remain there for the duration of the normal operation. Upon exiting the ROM tJ-S, it sets a zero to bit 0 of the port, immediately removes the ROM memory (and any standby state), and maps the RAM field into the royal half of the 780 address space. The Z80 continues to execute instructions, but the instructions now come from RAM. By storing one 3-bit address of the eight 32-RAM fields in bits 3-1 of the
can access this field in the second half of its address space. 8. CTC standard Z80C'FC chip 130° Cascade channels 2 to 3 to create a 1 second clock. Channel 0 provides a 16X9600 baud SIO bit rate clock. 9.3IO A power supply circuit using a charge pump generates →-/-12V for the R3232 interface. sro
Chip 131, two independent R32 of 9600 po
Provides 32 full duplex serial channels. 10. PIO mark to micro sequencer
34 bidirectional, baud) 13135 control output. The ROM loader program is not shown in Appendix ■. The main 280 program (Appendix III) is basically. As shown in the flowchart in Appendix IV, it consists of a simple hack loop that interacts with five foreground interrupt routines. After reset, the program goes to label 5TAR'r. Jump and perform various initialization functions: 1. Set the 280 interrupt mode (Mo12). 2. Set the I- register to point to the page containing the 1 interrupt vector. 3.3P- Cent the register and point the top of the M area to R, which is dedicated to the stack. 4. Initialize the values of the variables (cello except for the "number of remaining scotts" and "serial number" fields). 5. , zero the parity/ECC work area. 6. All subchannel status areas and 1-
Zero out the ranzaktion memory area. 7. Set the IX-register to perform parity work.
Specifies the area (this register does not change). 8. Set the CTC hexvex to instruct the 1-second interrupt routine. 'CT' to interrupt at 1 second intervals
Prepare C channels 2 and 3 (make a cascade). 9. Set the P2O interrupt vector and instruct the input/output routine. Boat, eight-way. B - Prepare to control out (interrupts masked). 10.Sent 3IO interrupt vector, 5IOVEC
Points to the vector block labeled with ・U
Ru. Initialize channel 8 control register. 11. Copy the microcode from memory location 500011 (where it was placed by the ROM loader) to the rl device, marked 71-loadable control, in the microsequencer. 12, Resetso 1-・Pip 1 is set. 13. Enable the microsequencer clock. 14. Wait about 1/4 second for the sequencer to reset itself. 15. Clear the Reseno 1 flag to allow the micro sea unit to enter its normal cycle. 16. Execute temporary PIO readout and set T3 RD Y line in Z80 microsequencer interface. 17. Branches into Huckland loop. Pack-ground loop ((as summarized in Table 1) micro-coquenzer or III) 1
If there is no complete input block from 000 (post), Z80 is idle. The only important feature is the diagnostic display, which reads the 8-bit switch array and
Add this hide to 41■1 and address the hide in the variable storage area. It consists of displaying the contents of this address on a light emitting diode array. The 280 person calculations from Hoss 1 are as follows: * Message block defined for the 16-word post multiplexer message (labeled llTl
There is one (starting with ). * It is prefixed with a flag byte (HTIFLG) and a count byte (TIBCT). * HTIFLG has the values 0 - free, 1 - in use (foreground), 2 - in use. Take medium (bank ground). * If 310 takes the first character, 1 interrupt becomes 5.
Vectoring to JARCA foreground routine. If HTIFLG is 2 (error), it is apo-1-L, and if IITIFLG is O, TITIFLG is set to 1 by 7sols. The message block II T I B
It is stored at high 1- corresponding to C'1', and the counter is incremented from 1 to 1. * If the counter is 32, the entire message block has been received and IITIFLG is set to 2. At this stage, the hack grand I routine is. Accept input messages to process rather than bypass that section of code. * At the end of the hackground process, HTIFLG and HTIBCT allow the process to repeat when the post sends the next block. Set to zero. The 280 input routines from the microsequencer operate in exactly the same way, with the exceptions noted below. 1. Message blocks, flags and counter labels begin with MSI. 2. The message block length is 9 bytes,
It consists of the subchannel address followed by the eight addresses of that subchannel's RAM memory slot. 3. The interrupt routine label is PIAIN. The 780 output calchin to the host is the inverse of the host input routine described above. *Labels begin with If TO. * Flag settings 1 and 2 have interchanged meanings (1 is not actually used). * The background routine starts the operation, sets the hide counter to 1, sets the flag to 2, and outputs the first character to 310 characters. * When SIO sends this character, it is in position 5I.
Interrupt ATBE. This foreground routine sends the next character and increments the counter. * When the same counter as 32 is entered in BE to Sl 8. The r Transmit Buffer Empty condition is flushed, the counters and flags are set to zero, and the operation completes. The 780 output calchin to the micro sequencer is boss 1.
Similar to output, except: 1. Labels start with MSO. Since only the 2.1 hide (accursor code) is sent, the Tsumeabrand routine simply flushes the resulting interrupt. Then clear the flag. 3. Byte counters are redundant for the same reason. As already explained, this system has one tl P 1000 minicomputer at the center of the network of devices, with which the system communicates via an asynchronous serial link. These devices will normally have an R5232 interface. R5232 interface has 15
It is not rated for operation at distances greater than 300 m, but under certain conditions it may function adequately up to 3.4 times this distance. However, in the factory environment for which this system is intended, these interfaces are considered inappropriate, especially given the intended operational data rate <9 GOO baud). Newer interfaces, particularly R3422 and its derivatives, operate using a balanced differential approach. If the circuit is made using a single twisted pair of telephone wire,
R3423 is fast and works well. RS 423 to RS
Despite the significant non-electrical improvements that become apparent when compared to R8423, factory use of R8423 remains limited. The reason is that there is a limit to the maximum allowable common mode noise on the line. For this reason. A fully isolated communication approach is used, which uses optical isolators on the data lines,
A transformer is used for the remote end self-power circuit. Using this technique, the minicomputer's ground and the remote 0111
between the ground of the terminal equipment. There are no C connections of any kind. Figure 9 shows the electrical circuit of a single channel. Data circuit - local to remote: Local (IIPlooO) transmitter signal at position 140 is transmitted to 26LS33 flat f%i differential receiver 141
The resulting 'rT L signal is picked up by the 26LS3L driver 1 which drives cable pair 1.
42. At the far end, the line pair is
It is terminated by a 1° resistor 143 and a reverse clamped opto-isolator 144. Bottom 1-Ransistor 14
5 is one JFETFET-rate operational amplifier 146
This operational amplifier generates a signal compatible with RS 232 147 for terminal equipment. Data circuit - 148 terminal R3232 signal from remote to 1-cal is LF352 (JFE
The operational amplifier circuit 149 is differential, so it is more immune to noise than ordinary circuits. Therefore, this circuit is the same as that used by the operator input device reader, with opto-isolator 150 driven by transistor 151. It consists of a transistor 153 that shorts line pair 2 and a phototransistor 152 connected to the Darlington pair, which draws current symmetrically through two 120Ω termination resistors 154. The differential signal is decoded by a JFET operational amplifier circuit 155, which drives an R3232 receive data line 156. - In this respect, it is desirable to ensure compatibility with R3432. The signal is clamped at 157 to about 1/-6v. Power circuit power is supplied to the remote interface box through the third pair of the three-pair telephone cable. This line pair is driven by a 12 dc power supply 158 which is grounded at the local end. The positive line is protected by fuse 159. The power supply is connected to one reserve capacitor 16 at the remote end.
0 and supplies power to the primary side 165 of transformer 161. One CMOS oscillator 1-2 is set to operate at approximately 50 II z, and this signal, via transistor 163, switches the primary current of the transformer. The center tap flybank voltage is clamped by one 20V Zener diode 164. The center sop primary coil 166 drives two rectifier/ballast circuits 167 that generate local +/-12V power with respect to terminal ground. The total current obtained is on the order of 20 m, which is twice what the local circuit requires. The isolating adapter circuit described here is
This is one of the elements that makes this system particularly suitable for factory environments. However, there are many other features that help with this. The worker input devices placed at each work station are simple and inexpensive, yet extremely rugged. Cards or slips read by worker input devices are particularly inexpensive and easy to print. However, cards can withstand much abuse: even crumpled cards and torn carts can usually be laid out flat and read reliably. Each operator input device is parasitically supplied with completely safe 24 V level power via its data transmission and control links, but can be installed anywhere in the factory. The multiplexer/concentrator receives data from worker input devices that provides a complete and up-to-date status of the work on hand in the factory, represents the progress of a particular order, detects malfunctions or failures, and provides information to employees. track turnout and work speed, and overall, plan to meet deadlines, use available employees and facilities in the most efficient manner, monitor inventory, calculate wages, and troubleshoot problems. Provides the information in l'Q necessary to predict and take preventive measures. The multiplexer/concentrator microcomputer is equipped with a battery power bank amplifier to prevent failure in the event of a nine-line power outage. The various data formats used in the system rlJ are listed in the appendix■
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[Brief explanation of drawings]

FIG. 1 is a perspective view of an operator input device with a card reader. 2A and 2B are circuit diagrams of one worker input device. FIG. 3 shows a barcoded card of the type read by the card reader of one operator input device. FIG. 4 shows an emitter and receiver configuration for scanning a card in a card reader. 5A and 5B, one operator input device is scanned,
A circuit diagram of a micro sequencer that receives and responds to data input from it. FIG. 6 is a circuit diagram of one of the eight channels used by the microsequencer to communicate with operator input devices. FIG. 7 is a circuit diagram of one of a number of subchannels that each channel shown in FIG. 6 may use to communicate with a group of operator input devices. Figures 8A through 8J are block circuit diagrams of the 780 microcomputer that provides overall control of the mic l'' sequencers of Figures 5A-1 and 5B and interfaces with the host minicomputer. Figure 9 shows the 8th
Figures Δ through 8J are circuit diagrams of isolating adapter circuits used by the Z80 microphone 1 cocomputer to interface with a host minicomputer. 10A and 10B are timing diagrams of the channels and subchannels of FIGS. 6I7I and 7. Patent applicant's agent name Purity of drawings (no change in content) FIG, 1 FIG, 8CFIG, 8D FIG, 8E Continued from page 1 Priority claim @ May 14, 1982 ■ United Kingdom (GB
) [Yes] 8214091 Procedural amendment (voluntary) July 21, 1980 Kazuo Wakasugi, Commissioner of the Patent Office, Mr. 1, Indication of case 1984 '19 ft↑ Application No. 84871 2, Title of invention Production control system 5, [Date of amendment order] 1989, Month, Day, Procedural amendment, 1982, 8th day, 0th day, Patent Office Commissioner, Kazuo Wakasugi, 1, Indication of the case, 1982 Patent Application No. 84871
No. 2, Title of the invention: Production control system 5, date of the amendment order. 6, Showa month, day 6, Amendment to the specification procedure subject to the amendment. August 11, 1980. Mr. Kazuo Wakasugi, Commissioner of the Japan Patent Office. Small case indication. 1982. 1958 Patent Application No. 8487
1 No. 2. Name of the invention Production management system 5.
"Amendment Directive Date" Showa Year, Month, Year 6,
Amendment (7) Target Description and drawings 7, Contents of amendment (1) Akira, 1 (+1 Tadaka, page 42, line 12, “Publication ■
” will be corrected to “Table 1”. (2) "Publishing II J" on page 56, line 7, "Table 2"
Please correct it first. (3) Change “(I) Roku 111) J” in the 8th line of No. 56 Tei to “
(Table 6)”. (4) ``Appendix ■'' on page 56, line 9 of the same page r F'IG
, corrected to 11 J. (5) On page 58, line 19, “(Published......
・)" to "(Ii"IG, 11!ko...)"
First, correct it. (6) ``Appendix V'' on page 67, lines 19-20 has been amended to ``Table 4.'' Correct it to 〇(8) rAPl) ENDIX 1 on page 83, line 1.
1" to "Table 2" 〇(9) Page 89, line 1, rAPPENDIX 1l
lji Correct to "Table 6". 001riJ pages 126 to 128 (Publishing■) will be deleted. αη Revise "Appendix ■" in the first line of page 129 to "Table 4". 0 Various quantities, page 131, line 9, after "...subchannel timing diagram", ", Figure 11 (a) (b)
(c) is a flowchart of the background 0 loose of the main z80 program. ” is added. 03 Drawing (FIG, 11) will be added as shown in the attached sheet. (b) (C) Procedural amendment dated October 4, 1980. Indication of the case of Mr. Kazuo Wakasugi, Commissioner of the License Agency, 1982 Patent Application No. 84871
Title of invention Production management system FIG, 11 (b) FIG, 11 (C)

Claims (1)

[Scope of Claims] (1) An operator input device used in a production or work management system that scans a card or vote indicating coded data when it is hung, and reads the coded data as described above. a card reader that generates an electrical signal representative of the data output signal; a cable that provides low voltage external power to the worker-powered device through a set of electrical lines; a pulse train generation circuit which derives its power from the aforementioned bare line for obtaining pulse streams of different duration; and shorting means receiving power from said bare line and responsive to said pulse flow to substantially short said line for a time corresponding to the duration of said pulse;
whereby data from a card or form is transmitted by a worker input device through the same cable bearer that powers one worker input device. (2. In an operator input device according to claim 1, said short-circuiting means connects one radiation emitter to which said pulsed stream is applied and is electrically responsive to radiation from said emitter. is driven by an optical isolator having two diodes, for example G, and a receiver isolated therefrom. (3) In a worker-powered device according to claim 2. is one light-emitting diode powered by one switching transistor to which a pulsed current is applied, the said receiver is one transistor, and further the said shorting means is one (4) Each card read by the operator input device according to claim 1 or 2 or 3. or the slip carries a black and white bar code and the card reader includes scanning means for illuminating the bar code track and detecting light reflected therefrom. (5) Work according to claim 4. Each card or slip carries two parallel barcode trunks, the first being a clock track of equally spaced narrow bars, and the second being a data barcode trunk.
a first emitter in the track having a thick bar or gap indicative of 'IJ' or 'OJ' at a position corresponding to each thin bar bit of the clock trunk, and a scanning means scanning the clock track; /receiver combination and a second emitter/receiver scanning the data trunk. (6) In the operator input device according to claim 5. Each emitter/receiver combination includes one infrared light emitting diode and one phototransistor. (7) According to claim 5 or 6. Two monostable circuits with different times to generate pulses of different widths and either monostables depending on whether the data tracks simultaneously exhibit bars or gaps in response to signals from the receiver of the scanning emitter/receiver. and a logic circuit for directing each clock bit to the power of the stabilizing circuit. (8) An operator input device according to claim 7. The outputs of the two monostable circuits are gated together to provide a pulsed stream that is applied to the 1-transistor that powers the light emitting diode of the optical isolake. (9) An operator input device according to any one of the preceding claims, further including an audio and/or visual response device, which device is connected to the line of its external power supply cable.
The one excited by the aforementioned external cable when the polarity of the voltage in the pair is reversed. (10) An operator input device according to claim 31, paragraphs 5 and 9, for emitter/receiver scanning. The circuit of the human powered device is
A storage capacitor receives power from a line that is held at a predetermined voltage by a storage capacitor and a voltage regulator. and the audio and/or visual response means each receive power from an external power source on a common line pair via isolating diodes of reverse polarity. (11) In production or work management systems for factory environments. a worker input device with a plurality of card readers located at the worker's work station;
The microprocessor consists of a multiplexer/concentrator consisting of a combination of two microcomputers and one microprocessor, which continuously scans the operator input device and It includes one microsequencer that obtains J data to be sent to the computer, and this microcomputer checks the validity of the data input from the operator input device by the microsequencer as the card is read by one operator input device. It tests the validity of the data, stores good data in short-term memory, and sends a signal indicating whether each data entry is valid or not to the microsequencer, which sends those data to individual worker-powered devices. The microphone I-1 computer returns a signal indicating whether the input is valid or not.
- Something with an input/output port for communication between host computer tables such as computers. (+2) Based on the 11th term of the mN calculation range, where the microphone 11 processor/microsequence number is one single level pi-blind type bipolar bit slice microb one processor. (13) A system according to claim 11 or 12, wherein the minicomputer is one Z 80 two-inch computer board. (14) Claim 11 or 12 or 1
In the system according to Section 3, a microsequencer communicates with a large number of worker input devices via one group of two channels, and each of the aforementioned channels connects one group of subchannels to each worker input device. Individual sub-channels. (15) A system according to claims 11 to 14, in which a card reader of each worker input device is provided. A device that reads the barcode 1-rack printed on the card or slip that is swiped by the worker. (16) In the system according to item 15 of the range of ii search, 3
There are two types of cards or votes: ie. 1) A worker card or badge that identifies another worker ii) A work card that indicates the specific work being performed l11) A job/lot/badge that identifies a batch of work
card or vote. (17) A system according to any one of claims 11 to 16, wherein communication between one operator input device and a corresponding subchannel of a microsequencer is performed by a single twist via a pair cable, through which the operator input device is parasitically supplied with power at a safe voltage from the microsequencer (any of claims 11 to 17) In a one-item system, a microsequencer provides power to each individual operator input device by maintaining the voltage on a pair of solenoid lines, and one operator input device supplies data to the microsequencer essentially. (19) on a card read by an operator input device in a system according to claim 18; After receiving the data, a microsequencer transmits a signal from the microcomputer indicating the validity of the data to each operator input device by means of a pulse generated by temporarily reversing the polarity of the power line. (20) In the system J according to any one of claims 11 to 19, the validity of data from two individual worker input devices is checked when there are nine worker input devices. It also includes checking whether a worker has loaded a plurality of different cards into a card reader in the correct order at a work station. (21) Any one item of Claims 11 to 20. In this system, each worker input device
An operator input device according to any one of claims 1 to 10. (22) A serial link for communication between one host computer and one microcomputer or one terminal device, including two pairs of cables, each pair providing a one-way communication channel. one optical isolator. (23) With the link according to claim 22, the channels from the host to the microphone 1'' computer/terminal device are in turn connected to one balanced differential receiver driver.
Cable Pair - Clamped Optical Isolator
- one chain containing operational amplifiers; and channels from the microcomputer/terminal to boss 1~, in turn. 1 operational amplifier - optical isolator 1 line
− 1-transistor for M path − Cable pair −
Operational amplifier decoder - 1 including clamped output circuit
one containing two chains. (24) A link according to claim 22 or 23, including a third cable pair for supplying power from the post to the microcomputer/αfXi terminal device,
The power supply chain comprises, in order, one boss 1 to power source - cable pair - oscillator - transformer - rectifier and ballast circuit. (25) Any one of claims 11 to 21
A system according to one item of Claims 22 to 24, including a link from one microcomputer to a post-mini JJ computer according to any one of claims 22 to 24; Icosesoza also has a battery power hackup to overcome main line power outages.