JPS5953411U

JPS5953411U - pinboard matrix

Info

Publication number: JPS5953411U
Application number: JP14876882U
Authority: JP
Inventors: 遠藤　弘三; 一宏辻; 藤岡　信照; 酒井　昌男
Original assignee: 富士通株式会社; 日本電信電話株式会社
Priority date: 1982-09-30
Filing date: 1982-09-30
Publication date: 1984-04-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のこの種ピンボード・マトリックスの一例
を要部斜視図で示し、第２図は本考案の１実施例を理解
に便なるよう各層を露呈した一部剥離した斜視図イと交
叉位置の貫通孔付近の側断面Ｎ０を示す。図において１はマトリックス筐体、２．１６は表面板、
３．２３はショートプラグ、Ｘ、Ｙはコネクター列、５
ｘ、５ｙは圧着端子、１１．１２は夫々ＸおよびＹ方向
配線パターン、１３．１４はプリント配諜板、１５は絶
縁スペーサ、１７゜１８は交叉位置の貫通孔、２１．２
２は導電層を示す。・　　５Ｘ　　　＼ −７（ＹＯ−−７ｎ）Fig. 1 shows an example of a conventional pinboard matrix of this type in a perspective view of the main parts, and Fig. 2 shows an embodiment of the present invention in a perspective view with each layer partially peeled away to make it easier to understand. A side cross section N0 near the through hole at the intersection position is shown. In the figure, 1 is the matrix case, 2.16 is the front plate,
3.23 is a short plug, X and Y are connector rows, 5
x and 5y are crimp terminals, 11.12 are wiring patterns in the X and Y directions, 13.14 is a printed distribution board, 15 is an insulating spacer, 17° and 18 are through holes at the intersection position, 21.2
2 indicates a conductive layer.・5X ＼ -7(YO--7n)

Claims

[Scope of utility model registration request]

Two printed wiring boards each having a conductive layer on their inner surface at an overlapping intersection position, an X-direction wiring pattern connected to the through-hole, and a Y-direction wiring pattern, and two printed wiring boards inserted into the through-hole. A pinboard matrix characterized by consisting of pin plugs that electrically connect individual wiring patterns.